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| m pd78076 m pd78078 m pd78p078 m pd78076y m pd78078y m pd78p078y m pd78078, 78078y subseries 8-bit single-chip microcontrollers document no. u10641ej4v0um00 (4th edition) date published december 1997 n 1994 user? manual printed in japan
2 [memo] 3 fip, eeprom, iebus, and qtop are trademarks of nec corporation. ms-dos, windows, and windowsnt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. ibm dos, ibm pc/at, and pc dos are trademarks of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. ethernet is a trademark of xerox corporation. osf/motif is a trademark of open software foundation, inc. news and news-os are trademarks of sony corporation. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. 4 the application circuits and their parameters are for reference only and are not intended for use in actual design-ins. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. license not needed: m pd78p078kl-t, 78p078ykl-t the customer must judge the need for license: m pd78076gc-xxx-7ea, 78076gc-xxx-8eu, 78076gf-xxx-3ba, m pd78076ygf-xxx-3ba m pd78078gc-xxx-7ea, 78078gc-xxx-8eu, 78078gf-xxx-3ba, m pd78078ygf-xxx-3ba m pd78p078gc-7ea, 78p078gc-8eu, 78p078gf-3ba, 78p078ygf-3ba the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is standard unless otherwise specified in necs data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5 5 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j97. 8 6 major revisions in this edition page description throughout the following products have been changed from under development to already developed. m pd78078y subseries: m pd78076y, 78078y, 78p078y the following packages have been added to the m pd78078y subseries. 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness 1.4 mm) p. 139 to 143, block diagrams of ports have been changed. 149, 153 figure 6-5. block diagram of p20, p21, p23 to p26, figure 6-6. block diagram of p22 and p27, figure 6-7. block diagram of p20, p21, p23 to p26, figure 6-8. block diagram of p22 and p27, figure 6-9. block diagram of p30 to p37, figure 6-16. block diagram of p71 and p72, figure 6-20. block diagram of p100 and p101 p. 169 table 7-2. relationship between cpu clock and minimum instruction execution time has been added. p. 181 8.1 outline of timers incorporated into m pd78078, 78078y subseries has been added. p. 241 figure 9-10. square wave output operation timing has been added. p. 262 figure 10-13. square wave output operation timing has been added. p. 277 figure 12-1. block diagram of watchdog timer has been corrected. p. 316, 366 precautions have been added to 17.1, 18.1 serial interface channel 0 functions . p. 323, 374 precautions have been added to 17.3 (2), 18.3 (2) serial operating mode register 0 (csim0) . p. 372 note about the bsye flag in figure 17-5. serial bus interface control register format has been changed. p. 336 precautions have been added to 17.4.3 (2) (a) bus release signal (rel), (b) command signal (cmd) . p. 449 19.4.3 (3) (d) busy control option, (e) busy & strobe control option , and (f) bit slippage detection function have been changed to (4) synchronization control , and the explanation has been improved. p. 481 20.4.2 (2) (d) reception conditions of intsr generation when receive error occurrs has been corrected. p. 482 figure 20-10. receive error timing has been corrected, and note has been added. p. 490 20.4.3 (3) msb/lsb switching as the start bit has been added. p. 491 20.4.4 restrictions on using uart mode has been added. p. 569 precautions have been added to table 27-1. differences between m pd78p078, 78p078y and mask rom versions . p. 597 appendix a differences between m pd78078, 78075b subseries and m pd78070a has been added. p. 599 to 612 appendix b development tool entirely revised: supports in-circuit emulator ie-78k0-ns p. 613, 614 appendix c embedded software entirely revised: fuzzy inference developing support system has been deleted. the mark shows major revised points. 7 introduction readers this manual has been prepared for user engineers who understand the functions of the m pd78078 and 78078y subseries and design and develop its application systems and programs. the m pd78078 and 78078y subseries consist of the following members. ? m pd78078 subseries: m pd78076, 78078, 78p078 ? m pd78078y subseries: m pd78076y, 78078y, 78p078y caution of the above members, the following devices with the suffix kl-t should be used only for experiment or function evaluation, because they are not intended for use in equipment that will be mass-produced and do not have enough reliability. ? m pd78p078kl-t and 78p078ykl-t purpose this manual is intended for users to understand the functions described in the organization below. organization the m pd78078 and 78078y subseries manual is separated into two parts: this manual and the instructions edition (common to the 78k/0 series). m pd78078, 78078y subseries 78k/0 series users manual users manual (this manual) instructions ? pin functions ? cpu functions ? internal block functions ? instruction set ? interrupt ? explanation of each instruction ? other on-chip peripheral functions how to read this manual before reading this manual, you should have general knowledge of electric and logic circuits and microcontroller. when you want to understand the functions in general: ? read this manual in the order of the contents. how to interpret the register format: ? for the circled bit number, the bit name is defined as a reserved word in ra78k/ 0, and in cc78k/0, already defined in the header file named sfrbit.h. when you know a register name and want to confirm its details: ? read appendix d register index to know the differences between the m pd78054 and 78054y subseries: ? see sections 1.10 and 2.10 , titled differences with m pd78054 subseries and differences with m pd78054y subseries , respectively. to know the m pd78078 and 78078y subseries instruction function in detail: ? refer to 78k/0 series users manualinstructions (u12326e) to know the application example of each function of the m pd78078 and 78078y subseries: ? refer to separately available application note. 8 chapter organization : this manual divides the descriptions for the m pd78078 and 78078y subseries into different chapters as shown below. read only the chapters related to the device you use. chapter m pd78078 m pd78078y subseries subseries chapter 1 outline ( m pd78078 subseries) ? chapter 2 outline ( m pd78078y subseries) ? chapter 3 pin function ( m pd78078 subseries) ? chapter 4 pin function ( m pd78078y subseries) ? chapter 5 cpu architecture ?? chapter 6 port functions ?? chapter 7 clock generator ?? chapter 8 16-bit timer/event counter ?? chapter 9 8-bit timer/event counters 1 and 2 ?? chapter 10 8-bit timer/event counters 5 and 6 ?? chapter 11 watch timer ?? chapter 12 watchdog timer ?? chapter 13 clock output control circuit ?? chapter 14 buzzer output control circuit ?? chapter 15 a/d converter ?? chapter 16 d/a converter ?? chapter 17 serial interface channel 0 ( m pd78078 subseries) ? chapter 18 serial interface channel 0 ( m pd78078y subseries) ? chapter 19 serial interface channel 1 ?? chapter 20 serial interface channel 2 ?? chapter 21 real-time output port ?? chapter 22 interrupt and test functions ?? chapter 23 external device expansion function ?? chapter 24 standby function ?? chapter 25 reset function ?? chapter 26 rom correction ?? chapter 27 m pd78p078, m pd78p078y ?? chapter 28 instruction set ?? 9 differences between m pd78078 and m pd78078y subseries the m pd78078 and m pd78078y subseries are different in the following functions of the serial interface channel 0. mode of serial interface channel 0 m pd78078 m pd78078y subseries subseries 3-wire serial i/o mode ?? 2-wire serial i/o mode ?? sbi (serial bus interface) mode ? i 2 c (inter ic) bus mode ? ? : supported : not supported legend data significance : high digits on the left and low digits on the right active low representations : xxx (line over the pin and signal names) note : description of note in the text caution : information requiring particular attention remark : additional explanatory material numeral representations : binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? related documents for this subseries document name document no. english japanese m pd78078, 78078y subseries users manual this manual u10641j m pd78076, 78078 data sheet u10167e u10167j m pd78p078 data sheet u10168e u10168j m pd78076y, 78078y data sheet u10605e u10605j m pd78p078y data sheet u10606e u10606j 78k/0 series users manualinstructions u12326e u12326j 78k/0 series instruction table u10903j 78k/0 series instruction set u10904j m pd78078 subseries special function register table iem-5607 m pd78078y subseries special function register table iem-5601 78k/0 series application note basics (iii) u10182e u10182j caution the above documents are subject to change without prior notice. be sure to use the latest version when starting design. 10 development tool documents (user?s manuals) document name document no. english japanese ra78k series assembler package operation eeu-1399 eeu-809 language eeu-1404 eeu-815 ra78k series structured assembler preprocessor eeu-1402 u12323j ra78k0 assembler package operation u11802e u11802j language u11801e u11801j structured assembly u11789e u11789j language cc78k series c compiler operation eeu-1280 eeu-656 language eeu-1284 eeu-655 cc78k0 c compiler operation u11517e u11517j language u11518e u11518j cc78k0 c compiler application note programming know-how eea-1208 u13034j cc78k series library source file u12322j pg-1500 prom programmer eeu-1335 u11940j pg-1500 controller pc-9800 series (ms-dos tm )-based eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dos tm )-based u10540e eeu-5008 ie-78k0-ns to be prepared to be prepared ie-78001-r-a to be prepared to be prepared ie-78k0-r-ex1 to be prepared to be prepared ie-78078-ns-em1 to be prepared to be prepared ie-78078-r-em u10775e u10775j ep-78064 eeu-1469 eeu-934 sm78k0 system simulator windows tm -based reference u10181e u10181j sm78k series system simulator external part user open interface specifications u10092e u10092j id78k0-ns integrated debugger reference to be prepared u12900j id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539e u11539j id78k0 integrated debugger windows based guides u11649e u11649j caution the above documents are subject to change without prior notice. be sure to use the latest version when starting design. 11 documents for embedded software (user?s manuals) document name document no. english japanese 78k/0 series real-time os basics u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 basics u12257e u12257j ? other documents document name document no. english japanese ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system u10983e u10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j guide to quality assurance for semiconductor devices mei-1202 microcomputer product series guide u11416j caution the above documents are subject to change without prior notice. be sure to use the latest version when starting design. 12 [memo] 13 table of contents chapter 1 outline ( m pd78078 subseries) ................................................................................. 33 1.1 features ............................................................................................................................... ... 33 1.2 application fields .................................................................................................................. 34 1.3 ordering information ............................................................................................................. 34 1.4 quality grade ......................................................................................................................... 35 1.5 pin configuration (top view) ............................................................................................... 36 1.6 78k/0 series expansion ........................................................................................................ 42 1.7 block diagram ........................................................................................................................ 44 1.8 outline of function ................................................................................................................ 45 1.9 mask options .......................................................................................................................... 47 1.10 differences with m pd78054 subseries ................................................................................ 47 chapter 2 outline ( m pd78078y subseries) .............................................................................. 49 2.1 features ............................................................................................................................... ... 49 2.2 application fields .................................................................................................................. 50 2.3 ordering information ............................................................................................................. 50 2.4 quality grade ......................................................................................................................... 51 2.5 pin configuration (top view) ............................................................................................... 52 2.6 78k/0 series expansion ........................................................................................................ 58 2.7 block diagram ........................................................................................................................ 60 2.8 outline of function ................................................................................................................ 61 2.9 mask options .......................................................................................................................... 63 2.10 differences with m pd78054y subseries ............................................................................. 63 chapter 3 pin function ( m pd78078 subseries) ....................................................................... 65 3.1 pin function list .................................................................................................................... 65 3.1.1 normal operating mode pins ...................................................................................................... 65 3.1.2 prom programming mode pins ( m pd78p078 only) ................................................................. 69 3.2 description of pin functions ............................................................................................... 70 3.2.1 p00 to p07 (port 0) ..................................................................................................................... 70 3.2.2 p10 to p17 (port 1) ..................................................................................................................... 70 3.2.3 p20 to p27 (port 2) ..................................................................................................................... 71 3.2.4 p30 to p37 (port 3) ..................................................................................................................... 72 3.2.5 p40 to p47 (port 4) ..................................................................................................................... 72 3.2.6 p50 to p57 (port 5) ..................................................................................................................... 73 3.2.7 p60 to p67 (port 6) ..................................................................................................................... 73 3.2.8 p70 to p72 (port 7) ..................................................................................................................... 74 3.2.9 p80 to p87 (port 8) ..................................................................................................................... 74 3.2.10 p90 to p96 (port 9) ..................................................................................................................... 75 3.2.11 p100 to p103 (port 10) ............................................................................................................... 75 3.2.12 p120 to p127 (port 12) ............................................................................................................... 75 3.2.13 p130 and p131 (port 13) ............................................................................................................ 76 3.2.14 av ref0 ............................................................................................................................... ........... 76 3.2.15 av ref1 ............................................................................................................................... ........... 76 3.2.16 av dd ............................................................................................................................... .............. 76 14 3.2.17 av ss ............................................................................................................................... .............. 76 3.2.18 reset ............................................................................................................................... .......... 76 3.2.19 x1 and x2 ............................................................................................................................... ..... 76 3.2.20 xt1 and xt2 ............................................................................................................................... 76 3.2.21 v dd ............................................................................................................................... ................ 77 3.2.22 v ss ............................................................................................................................... ................. 77 3.2.23 v pp ( m pd78p078 only) ................................................................................................................ 77 3.2.24 ic (mask rom version only) ...................................................................................................... 77 3.3 input/output circuits and recommended connection of unused pins ........................ 78 chapter 4 pin function ( m pd78078y subseries) ................................................................... 83 4.1 pin function list .................................................................................................................... 83 4.1.1 normal operating mode pins ...................................................................................................... 83 4.1.2 prom programming mode pins ( m pd78p078y only) ............................................................... 87 4.2 description of pin functions ............................................................................................... 88 4.2.1 p00 to p07 (port 0) ..................................................................................................................... 88 4.2.2 p10 to p17 (port 1) ..................................................................................................................... 88 4.2.3 p20 to p27 (port 2) ..................................................................................................................... 89 4.2.4 p30 to p37 (port 3) ..................................................................................................................... 90 4.2.5 p40 to p47 (port 4) ..................................................................................................................... 90 4.2.6 p50 to p57 (port 5) ..................................................................................................................... 91 4.2.7 p60 to p67 (port 6) ..................................................................................................................... 91 4.2.8 p70 to p72 (port 7) ..................................................................................................................... 92 4.2.9 p80 to p87 (port 8) ..................................................................................................................... 92 4.2.10 p90 to p96 (port 9) ..................................................................................................................... 93 4.2.11 p100 to p103 (port 10) ............................................................................................................... 93 4.2.12 p120 to p127 (port 12) ............................................................................................................... 93 4.2.13 p130 and p131 (port 13) ............................................................................................................ 94 4.2.14 av ref0 ............................................................................................................................... ........... 94 4.2.15 av ref1 ............................................................................................................................... ........... 94 4.2.16 av dd ............................................................................................................................... .............. 94 4.2.17 av ss ............................................................................................................................... .............. 94 4.2.18 reset ............................................................................................................................... .......... 94 4.2.19 x1 and x2 ............................................................................................................................... ..... 94 4.2.20 xt1 and xt2 ............................................................................................................................... 94 4.2.21 v dd ............................................................................................................................... ................ 95 4.2.22 v ss ............................................................................................................................... ................. 95 4.2.23 v pp ( m pd78p078y only) .............................................................................................................. 95 4.2.24 ic (mask rom version only) ...................................................................................................... 95 4.3 input/output circuits and recommended connection of unused pins ........................ 96 chapter 5 cpu architecture ................................................................................................... . 101 5.1 memory spaces .................................................................................................................... 101 5.1.1 internal program memory space .............................................................................................. 104 5.1.2 internal data memory space ..................................................................................................... 106 5.1.3 special function register (sfr) area ........................................................................................ 106 5.1.4 external memory space ............................................................................................................ 106 5.1.5 data memory addressing .......................................................................................................... 107 15 5.2 processor registers ............................................................................................................ 110 5.2.1 control registers ........................................................................................................................ 110 5.2.2 general registers ....................................................................................................................... 113 5.2.3 special function register (sfr) ................................................................................................ 114 5.3 instruction address addressing ....................................................................................... 118 5.3.1 relative addressing ................................................................................................................... 118 5.3.2 immediate addressing ............................................................................................................... 119 5.3.3 table indirect addressing .......................................................................................................... 120 5.3.4 register addressing .................................................................................................................. 121 5.4 operand address addressing ........................................................................................... 122 5.4.1 implied addressing .................................................................................................................... 122 5.4.2 register addressing .................................................................................................................. 123 5.4.3 direct addressing ...................................................................................................................... 124 5.4.4 short direct addressing ............................................................................................................. 125 5.4.5 special function register (sfr) addressing ............................................................................. 126 5.4.6 register indirect addressing ..................................................................................................... 127 5.4.7 based addressing ...................................................................................................................... 128 5.4.8 based indexed addressing ....................................................................................................... 129 5.4.9 stack addressing ....................................................................................................................... 129 chapter 6 port functions ..................................................................................................... .... 131 6.1 port functions ...................................................................................................................... 131 6.2 port configuration ............................................................................................................... 136 6.2.1 port 0 ............................................................................................................................... .......... 136 6.2.2 port 1 ............................................................................................................................... .......... 138 6.2.3 port 2 ( m pd78078 subseries) ................................................................................................... 139 6.2.4 port 2 ( m pd78078y subseries) ................................................................................................ 141 6.2.5 port 3 ............................................................................................................................... .......... 143 6.2.6 port 4 ............................................................................................................................... .......... 144 6.2.7 port 5 ............................................................................................................................... .......... 145 6.2.8 port 6 ............................................................................................................................... .......... 146 6.2.9 port 7 ............................................................................................................................... .......... 148 6.2.10 port 8 ............................................................................................................................... .......... 150 6.2.11 port 9 ............................................................................................................................... .......... 151 6.2.12 port 10 ............................................................................................................................... ........ 153 6.2.13 port 12 ............................................................................................................................... ........ 155 6.2.14 port 13 ............................................................................................................................... ........ 156 6.3 port function control registers ....................................................................................... 157 6.4 port function operations ................................................................................................... 163 6.4.1 writing to input/output port ....................................................................................................... 163 6.4.2 reading from input/output port ................................................................................................. 163 6.4.3 operations on input/output port ................................................................................................ 163 6.5 selection of mask option ................................................................................................... 164 16 chapter 7 clock generator .................................................................................................... 165 7.1 clock generator functions ................................................................................................ 165 7.2 clock generator configuration .......................................................................................... 166 7.3 clock generator control register ..................................................................................... 167 7.4 system clock oscillator ..................................................................................................... 171 7.4.1 main system clock oscillator ..................................................................................................... 171 7.4.2 subsystem clock oscillator ........................................................................................................ 172 7.4.3 divider ............................................................................................................................... ......... 174 7.4.4 when no subsystem clocks are used ...................................................................................... 174 7.5 clock generator operations .............................................................................................. 175 7.5.1 main system clock operations .................................................................................................. 176 7.5.2 subsystem clock operations ..................................................................................................... 177 7.6 changing system clock and cpu clock settings .......................................................... 178 7.6.1 time required for switchover between system clock and cpu clock ..................................... 178 7.6.2 system clock and cpu clock switching procedure ................................................................. 179 chapter 8 16-bit timer/event counter .................................................................................. 181 8.1 outline of timers incorporated into m pd78078, 78078y subseries ............................. 181 8.2 16-bit timer/event counter functions ............................................................................. 183 8.3 16-bit timer/event counter configuration ...................................................................... 185 8.4 16-bit timer/event counter control registers ............................................................... 190 8.5 16-bit timer/event counter operations ........................................................................... 198 8.5.1 interval timer operations ........................................................................................................... 198 8.5.2 pwm output operations ............................................................................................................ 200 8.5.3 ppg output operations .............................................................................................................. 203 8.5.4 pulse width measurement operations ...................................................................................... 204 8.5.5 external event counter operation ............................................................................................. 211 8.5.6 square-wave output operation ................................................................................................. 213 8.5.7 one-shot pulse output operation .............................................................................................. 215 8.6 16-bit timer/event counter operating precautions ....................................................... 219 chapter 9 8-bit timer/event counters 1 and 2 ................................................................... 223 9.1 8-bit timer/event counters 1 and 2 functions ............................................................... 223 9.1.1 8-bit timer/event counter mode ................................................................................................. 223 9.1.2 16-bit timer/event counter mode ............................................................................................... 226 9.2 8-bit timer/event counters 1 and 2 configurations ...................................................... 228 9.3 8-bit timer/event counters 1 and 2 control registers ................................................. 231 9.4 8-bit timer/event counters 1 and 2 operations ............................................................. 236 9.4.1 8-bit timer/event counter mode ................................................................................................. 236 9.4.2 16-bit timer/event counter mode ............................................................................................... 242 9.5 8-bit timer/event counters 1 and 2 precautions ........................................................... 246 17 chapter 10 8-bit timer/event counters 5 and 6 ................................................................. 249 10.1 8-bit timer/event counters 5 and 6 functions ............................................................... 249 10.2 8-bit timer/event counters 5 and 6 configurations ...................................................... 252 10.3 8-bit timer/event counters 5 and 6 control registers ................................................. 254 10.4 8-bit timer/event counters 5 and 6 operations ............................................................. 259 10.4.1 interval timer operations ........................................................................................................... 259 10.4.2 external event counter operation ............................................................................................. 261 10.4.3 square-wave output .................................................................................................................. 262 10.4.4 pwm output operations ............................................................................................................ 264 10.5 8-bit timer/event counters 5 and 6 precautions ........................................................... 267 chapter 11 watch timer ....................................................................................................... ...... 269 11.1 watch timer functions ....................................................................................................... 269 11.2 watch timer configuration ................................................................................................ 270 11.3 watch timer control registers ......................................................................................... 271 11.4 watch timer operations ..................................................................................................... 274 11.4.1 watch timer operation ............................................................................................................... 274 11.4.2 interval timer operation ............................................................................................................. 274 chapter 12 watchdog timer .................................................................................................... . 275 12.1 watchdog timer functions ................................................................................................ 275 12.2 watchdog timer configuration ......................................................................................... 277 12.3 watchdog timer control registers .................................................................................. 278 12.4 watchdog timer operations .............................................................................................. 281 12.4.1 watchdog timer operation ......................................................................................................... 281 12.4.2 interval timer operation ............................................................................................................. 282 chapter 13 clock output control circuit ........................................................................ 283 13.1 clock output control circuit functions .......................................................................... 283 13.2 clock output control circuit configuration .................................................................... 284 13.3 clock output function control registers ....................................................................... 285 chapter 14 buzzer output control circuit ...................................................................... 289 14.1 buzzer output control circuit functions ........................................................................ 289 14.2 buzzer output control circuit configuration .................................................................. 289 14.3 buzzer output function control registers ..................................................................... 290 chapter 15 a/d converter ..................................................................................................... .... 293 15.1 a/d converter functions .................................................................................................... 293 15.2 a/d converter configuration ............................................................................................. 293 15.3 a/d converter control registers ...................................................................................... 296 15.4 a/d converter operations .................................................................................................. 300 15.4.1 basic operations of a/d converter ............................................................................................ 300 15.4.2 input voltage and conversion results ....................................................................................... 302 15.4.3 a/d converter operating mode .................................................................................................. 303 15.5 a/d converter cautions ...................................................................................................... 305 18 chapter 16 d/a converter ..................................................................................................... .... 309 16.1 d/a converter functions .................................................................................................... 309 16.2 d/a converter configuration ............................................................................................. 310 16.3 d/a converter control registers ...................................................................................... 312 16.4 d/a converter operations .................................................................................................. 313 16.5 d/a converter cautions ...................................................................................................... 314 chapter 17 serial interface channel 0 ( m pd78078 subseries) .................................... 315 17.1 serial interface channel 0 functions ............................................................................... 316 17.2 serial interface channel 0 configuration ......................................................................... 318 17.3 serial interface channel 0 control registers .................................................................. 321 17.4 serial interface channel 0 operations ............................................................................. 328 17.4.1 operation stop mode ................................................................................................................. 328 17.4.2 3-wire serial i/o mode operation .............................................................................................. 329 17.4.3 sbi mode operation .................................................................................................................. 333 17.4.4 2-wire serial i/o mode operation .............................................................................................. 357 17.4.5 sck0/p27 pin output manipulation .......................................................................................... 363 chapter 18 serial interface channel 0 ( m pd78078y subseries) ..................................... 365 18.1 serial interface channel 0 functions ............................................................................... 366 18.2 serial interface channel 0 configuration ......................................................................... 368 18.3 serial interface channel 0 control registers .................................................................. 372 18.4 serial interface channel 0 operations ............................................................................. 380 18.4.1 operation stop mode ................................................................................................................. 380 18.4.2 3-wire serial i/o mode operation .............................................................................................. 381 18.4.3 2-wire serial i/o mode operation .............................................................................................. 385 18.4.4 i 2 c bus mode operation ............................................................................................................ 390 18.4.5 cautions on use of i 2 c bus mode ............................................................................................ 408 18.4.6 restrictions in i 2 c bus mode .................................................................................................... 411 18.4.7 sck0/scl/p27 pin output manipulation .................................................................................. 413 chapter 19 serial interface channel 1 .............................................................................. 415 19.1 serial interface channel 1 functions ............................................................................... 415 19.2 serial interface channel 1 configuration ......................................................................... 416 19.3 serial interface channel 1 control registers .................................................................. 418 19.4 serial interface channel 1 operations ............................................................................. 425 19.4.1 operation stop mode ................................................................................................................. 425 19.4.2 3-wire serial i/o mode operation .............................................................................................. 426 19.4.3 3-wire serial i/o mode operation with automatic transmit/receive function ........................... 429 chapter 20 serial interface channel 2 .............................................................................. 457 20.1 serial interface channel 2 functions ............................................................................... 457 20.2 serial interface channel 2 configuration ......................................................................... 458 20.3 serial interface channel 2 control registers .................................................................. 461 20.4 serial interface channel 2 operation ............................................................................... 469 20.4.1 operation stop mode ................................................................................................................. 469 20.4.2 asynchronous serial interface (uart) mode .......................................................................... 471 20.4.3 3-wire serial i/o mode ............................................................................................................... 484 20.4.4 restrictions on using uart mode ........................................................................................... 491 19 chapter 21 real-time output port ........................................................................................ 495 21.1 real-time output port functions ..................................................................................... 495 21.2 real-time output port configuration ............................................................................... 495 21.3 real-time output port control registers ........................................................................ 497 chapter 22 interrupt functions ............................................................................................ 499 22.1 interrupt function types .................................................................................................... 499 22.2 interrupt sources and configuration ................................................................................ 500 22.3 interrupt function control registers ............................................................................... 504 22.4 interrupt servicing operations .......................................................................................... 513 22.4.1 non-maskable interrupt request acknowledge operation ........................................................ 513 22.4.2 maskable interrupt request acknowledge operation ................................................................ 516 22.4.3 software interrupt request acknowledge operation ................................................................. 518 22.4.4 multiple interrupt servicing ........................................................................................................ 519 22.4.5 interrupt request reserve .......................................................................................................... 522 22.5 test functions ..................................................................................................................... 523 22.5.1 registers controlling the test function ...................................................................................... 523 22.5.2 test input signal acknowledge operation ................................................................................. 525 chapter 23 external device expansion function ........................................................... 527 23.1 external device expansion functions ............................................................................. 527 23.2 external device expansion function control register ................................................. 531 23.3 external device expansion function timing .................................................................. 534 23.3.1 timings in multiplexed bus mode ............................................................................................ 534 23.3.2 timings in separate bus mode ................................................................................................ 539 chapter 24 standby function .................................................................................................. 545 24.1 standby function and configuration ............................................................................... 545 24.1.1 standby function ........................................................................................................................ 545 24.1.2 standby function control register .............................................................................................. 546 24.2 standby function operations ............................................................................................ 547 24.2.1 halt mode ............................................................................................................................... . 547 24.2.2 stop mode ............................................................................................................................... 550 chapter 25 reset function .................................................................................................... ... 553 25.1 reset function ..................................................................................................................... 553 chapter 26 rom correction .................................................................................................... . 559 26.1 rom correction functions ................................................................................................. 559 26.2 rom correction configuration .......................................................................................... 559 26.3 rom correction control registers ................................................................................... 561 26.4 rom correction application .............................................................................................. 562 26.5 rom correction example ................................................................................................... 565 26.6 program execution flow .................................................................................................... 566 26.7 cautions on rom correction ............................................................................................. 568 20 chapter 27 m pd78p078, 78p078y .................................................................................................. 569 27.1 internal memory size switching register ........................................................................ 570 27.2 internal extension ram size switching register ........................................................... 571 27.3 prom programming ............................................................................................................ 572 27.3.1 operating modes ....................................................................................................................... 572 27.3.2 prom write procedure .............................................................................................................. 574 27.3.3 prom reading procedure ......................................................................................................... 578 27.4 erasure procedure ( m pd78p078kl-t and 78p078ykl-t only) ..................................... 579 27.5 opaque film masking window ( m pd78p078kl-t and 78p078ykl-t only) ................ 579 27.6 screening of one-time prom versions .......................................................................... 579 chapter 28 instruction set ................................................................................................... ... 581 28.1 legends used in operation list ........................................................................................ 582 28.1.1 operand identifiers and description methods .......................................................................... 582 28.1.2 description of operation column ............................................................................................ 583 28.1.3 description of flag operation column ..................................................................................... 583 28.2 operation list ....................................................................................................................... 584 28.3 instructions listed by addressing type .......................................................................... 592 appendix a differences between m pd78078, 78075b subseries, and m pd78070a ...... 597 appendix b development tools .............................................................................................. 599 b.1 language processing software ......................................................................................... 602 b.2 prom writing tools ............................................................................................................ 604 b.2.1 hardware ............................................................................................................................... .... 604 b.2.2 software ............................................................................................................................... ...... 604 b.3 debugging tools .................................................................................................................. 605 b.3.1 hardware ............................................................................................................................... .... 605 b.3.2 software ............................................................................................................................... ...... 607 b.4 os for ibm pc ...................................................................................................................... 609 b.5 system upgrading from former-type in-circuit emulator for 78k/0 series to ie-78001-r-a .................................................................................................................... 609 appendix c embedded software ............................................................................................ 613 appendix d register index .................................................................................................... ..... 615 d.1 register name index ........................................................................................................... 615 d.2 register symbol index ........................................................................................................ 619 appendix e revision history .................................................................................................. ... 623 21 list of figures (1/9) figure no. title page 3-1 list of pin input/output circuits ................................................................................................... 80 4-1 list of pin input/output circuits ................................................................................................... 98 5-1 memory map ( m pd78076, 78076y) ........................................................................................... 101 5-2 memory map ( m pd78078, 78078y) ........................................................................................... 102 5-3 memory map ( m pd78p078, m pd78p078y) ............................................................................... 103 5-4 data memory addressing ( m pd78076, 78076y) ....................................................................... 107 5-5 data memory addressing ( m pd78078, 78078y) ....................................................................... 108 5-6 data memory addressing ( m pd78p078, 78p078y) .................................................................. 109 5-7 program counter configuration ................................................................................................. 110 5-8 program status word configuration .......................................................................................... 110 5-9 stack pointer configuration ....................................................................................................... 112 5-10 data to be saved to stack memory ........................................................................................... 112 5-11 data to be reset from stack memory ....................................................................................... 112 5-12 general register configuration .................................................................................................. 113 6-1 port types ............................................................................................................................... .... 131 6-2 block diagram of p00 and p07 .................................................................................................. 137 6-3 block diagram of p01 to p06 ..................................................................................................... 137 6-4 block diagram of p10 to p17 ..................................................................................................... 138 6-5 block diagram of p20, p21, p23 to p26 ................................................................................... 139 6-6 block diagram of p22 and p27 .................................................................................................. 140 6-7 block diagram of p20, p21, p23 to p26 ................................................................................... 141 6-8 block diagram of p22 and p27 .................................................................................................. 142 6-9 block diagram of p30 to p37 ..................................................................................................... 143 6-10 block diagram of p40 to p47 ..................................................................................................... 144 6-11 block diagram of falling edge detection circuit ...................................................................... 144 6-12 block diagram of p50 to p57 ..................................................................................................... 145 6-13 block diagram of p60 to p63 ..................................................................................................... 147 6-14 block diagram of p64 to p67 ..................................................................................................... 147 6-15 block diagram of p70 ................................................................................................................. 148 6-16 block diagram of p71 and p72 .................................................................................................. 149 6-17 block diagram of p80 to p87 ..................................................................................................... 150 6-18 block diagram of p90 to p93 ..................................................................................................... 152 6-19 block diagram of p94 to p96 ..................................................................................................... 152 6-20 block diagram of p100 and p101 ............................................................................................. 153 6-21 block diagram of p102 and p103 ............................................................................................. 154 6-22 block diagram of p120 to p127 ................................................................................................. 155 6-23 block diagram of p130 and p131 ............................................................................................. 156 6-24 port mode register format ........................................................................................................ 159 6-25 pull-up resistor option register format .................................................................................. 160 6-26 memory expansion mode register format ............................................................................... 161 6-27 key return mode register format ............................................................................................ 162 22 list of figures (2/9) figure no. title page 7-1 block diagram of clock generator ............................................................................................ 166 7-2 subsystem clock feedback resistor ........................................................................................ 167 7-3 processor clock control register format ................................................................................. 168 7-4 oscillation mode selection register format ............................................................................. 170 7-5 main system clock waveform due to writing to osms .......................................................... 170 7-6 external circuit of main system clock oscillator ..................................................................... 171 7-7 external circuit of subsystem clock oscillator ......................................................................... 172 7-8 examples of oscillator with bad connection ............................................................................ 172 7-9 main system clock stop function ............................................................................................. 176 7-10 system clock and cpu clock switching .................................................................................. 179 8-1 16-bit timer/event counter block diagram .............................................................................. 186 8-2 16-bit timer/event counter output control circuit block diagram ......................................... 187 8-3 timer clock selection register 0 format ................................................................................. 191 8-4 16-bit timer mode control register format ............................................................................. 192 8-5 capture/compare control register 0 format ........................................................................... 193 8-6 16-bit timer output control register format ........................................................................... 194 8-7 port mode register 3 format ..................................................................................................... 195 8-8 external interrupt mode register 0 format ............................................................................... 196 8-9 sampling clock select register format .................................................................................... 197 8-10 control register settings for interval timer operation ............................................................ 198 8-11 interval timer configuration diagram ........................................................................................ 199 8-12 interval timer operation timings .............................................................................................. 199 8-13 control register settings for pwm output operation .............................................................. 201 8-14 example of d/a converter configuration with pwm output .................................................... 202 8-15 tv tuner application circuit example ....................................................................................... 202 8-16 control register settings for ppg output operation ............................................................... 203 8-17 control register settings for pulse width measurement with free-running counter and one capture register ......................................................................................................... 204 8-18 configuration diagram for pulse width measurement by free-running counter .................. 205 8-19 timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) ................................................................. 205 8-20 control register settings for two pulse width measurements with free-running counter ................................................................................................................ 206 8-21 timing of pulse width measurement operation with free-running counter (with both edges specified) ....................................................................................................... 207 8-22 control register settings for pulse width measurement with free-running counter and two capture registers ............................................................................................................... 208 8-23 timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) ............................................................... 209 8-24 control register settings for pulse width measurement by means of restart ...................... 210 8-25 timing of pulse width measurement operation by means of restart (with rising edge specified) ...................................................................................................... 210 23 list of figures (3/9) figure no. title page 8-26 control register settings in external event counter mode ..................................................... 211 8-27 external event counter configuration diagram ........................................................................ 212 8-28 external event counter operation timings (with rising edge specified) ............................... 212 8-29 control register settings in square-wave output mode ......................................................... 213 8-30 square-wave output operation timing .................................................................................... 214 8-31 control register settings for one-shot pulse output operation using software trigger ..... 215 8-32 timing of one-shot pulse output operation using software trigger ..................................... 216 8-33 control register settings for one-shot pulse output operation using external trigger ...... 217 8-34 timing of one-shot pulse output operation using external trigger (with rising edge specified) ..................................................................................................... 218 8-35 16-bit timer register start timing ............................................................................................ 219 8-36 timings after change of compare register during timer count operation .......................... 219 8-37 capture register data retention timing .................................................................................. 220 8-38 operation timing of ovf0 flag ................................................................................................. 221 9-1 8-bit timer/event counters 1 and 2 block diagram ................................................................. 228 9-2 block diagram of 8-bit timer/event counter output control circuit 1 .................................... 229 9-3 block diagram of 8-bit timer/event counter output control circuit 2 .................................... 229 9-4 timer clock select register 1 format ...................................................................................... 232 9-5 8-bit timer mode control register 1 format ............................................................................ 233 9-6 8-bit timer output control register format ............................................................................. 234 9-7 port mode register 3 format ..................................................................................................... 235 9-8 interval timer operation timing ................................................................................................ 236 9-9 external event counter operation timings (with rising edge specified) ............................... 239 9-10 timing of square wave output operation ................................................................................ 241 9-11 interval timer operation timing ................................................................................................ 242 9-12 external event counter operation timings (with rising edge specified) ............................... 244 9-13 8-bit timer registers 1 and 2 start timing ............................................................................... 246 9-14 external event counter operation timing ................................................................................. 246 9-15 timing after compare register change during timer count operation ................................. 247 10-1 8-bit timer/event counters 5 and 6 block diagram ................................................................. 252 10-2 block diagram of 8-bit timer/event counters 5 and 6 output control circuit ....................... 253 10-3 timer clock select register 5 format ...................................................................................... 254 10-4 timer clock select register 6 format ...................................................................................... 255 10-5 8-bit timer output control register format ............................................................................. 256 10-6 8-bit timer output control register 6 format .......................................................................... 257 10-7 port mode register 10 format ................................................................................................... 258 10-8 8-bit timer mode control register settings for interval timer operation .............................. 259 10-9 interval timer operation timings .............................................................................................. 259 10-10 8-bit timer mode control register setting for external event counter operation ................. 261 10-11 external event counter operation timings (with rising edge specified) ............................... 261 10-12 8-bit timer mode control register settings for square-wave output operation .................. 262 10-13 timing of square wave output operation ................................................................................ 262 24 list of figures (4/9) figure no. title page 10-14 8-bit timer control register settings for pwm output operation .......................................... 264 10-15 pwm output operation timing (active high setting) ............................................................... 265 10-16 pwm output operation timings (crn0 = 00h, active high setting) ...................................... 265 10-17 pwm output operation timings (crn0 = ffh, active high setting) ..................................... 266 10-18 pwm output operation timings (crn0 changing, active high setting) ................................ 266 10-19 8-bit timer registers 5 and 6 start timings ............................................................................. 267 10-20 external event counter operation timings ............................................................................... 267 10-21 timings after compare register change during timer count operation ............................... 268 11-1 watch timer block diagram ...................................................................................................... 271 11-2 timer clock select register 2 format ...................................................................................... 272 11-3 watch timer mode control register format ............................................................................ 273 12-1 watchdog timer block diagram ................................................................................................ 277 12-2 timer clock select register 2 format ...................................................................................... 279 12-3 watchdog timer mode register format ................................................................................... 280 13-1 remote controlled output application example ....................................................................... 283 13-2 clock output control circuit block diagram ............................................................................. 284 13-3 timer clock select register 0 format ...................................................................................... 286 13-4 port mode register 3 format ..................................................................................................... 287 14-1 buzzer output control circuit block diagram ........................................................................... 289 14-2 timer clock select register 2 format ...................................................................................... 291 14-3 port mode register 3 format ..................................................................................................... 292 15-1 a/d converter block diagram .................................................................................................... 294 15-2 a/d converter mode register format ....................................................................................... 297 15-3 a/d converter input select register format ............................................................................ 298 15-4 external interrupt mode register 1 format ............................................................................... 299 15-5 a/d converter basic operation .................................................................................................. 301 15-6 relationships between analog input voltage and a/d conversion result ............................. 302 15-7 a/d conversion by hardware start ............................................................................................ 303 15-8 a/d conversion by software start ............................................................................................. 304 15-9 example of method of reducing current consumption in standby mode .............................. 305 15-10 analog input pin disposition ...................................................................................................... 306 15-11 a/d conversion end interrupt request generation timing ..................................................... 307 15-12 handling of av dd pin .................................................................................................................. 307 16-1 d/a converter block diagram .................................................................................................... 310 16-2 d/a converter mode register format ....................................................................................... 312 16-3 use example of buffer amplifier ................................................................................................ 314 25 list of figures (5/9) figure no. title page 17-1 serial bus interface (sbi) system configuration example ...................................................... 317 17-2 serial interface channel 0 block diagram ................................................................................ 318 17-3 timer clock select register 3 format ...................................................................................... 322 17-4 serial operating mode register 0 format ................................................................................ 324 17-5 serial bus interface control register format ........................................................................... 325 17-6 interrupt timing specify register format .................................................................................. 327 17-7 3-wire serial i/o mode timings ................................................................................................. 331 17-8 relt and cmdt operations ..................................................................................................... 331 17-9 circuit of switching in transfer bit order .................................................................................. 332 17-10 example of serial bus configuration with sbi .......................................................................... 333 17-11 sbi transfer timings .................................................................................................................. 335 17-12 bus release signal .................................................................................................................... 336 17-13 command signal ........................................................................................................................ 336 17-14 addresses ............................................................................................................................... .... 337 17-15 slave selection with address ..................................................................................................... 337 17-16 commands ............................................................................................................................... ... 338 17-17 data ............................................................................................................................... .............. 338 17-18 acknowledge signal ................................................................................................................... 339 17-19 busy and ready signals ........................................................................................................ 339 17-20 relt, cmdt, reld, and cmdd operations (master) ............................................................ 344 17-21 reld and cmdd operations (slave) ....................................................................................... 344 17-22 ackt operation .......................................................................................................................... 345 17-23 acke operations ........................................................................................................................ 346 17-24 ackd operations ....................................................................................................................... 347 17-25 bsye operation .......................................................................................................................... 347 17-26 pin configuration ........................................................................................................................ 350 17-27 address transmission from master device to slave device (wup = 1) ................................ 352 17-28 command transmission from master device to slave device ................................................ 353 17-29 data transmission from master device to slave device ......................................................... 354 17-30 data transmission from slave device to master device ......................................................... 355 17-31 serial bus configuration example using 2-wire serial i/o mode ........................................... 357 17-32 2-wire serial i/o mode timings ................................................................................................. 361 17-33 relt and cmdt operations ..................................................................................................... 361 17-34 sck0/p27 pin configuration ...................................................................................................... 363 18-1 serial bus configuration example using i 2 c bus ..................................................................... 367 18-2 serial interface channel 0 block diagram ................................................................................ 369 18-3 timer clock select register 3 format ...................................................................................... 373 18-4 serial operating mode register 0 format ................................................................................ 375 18-5 serial bus interface control register format ........................................................................... 376 18-6 interrupt timing specify register format .................................................................................. 378 18-7 3-wire serial i/o mode timings ................................................................................................. 383 18-8 relt and cmdt operations ..................................................................................................... 383 18-9 circuit of switching in transfer bit order .................................................................................. 384 26 list of figures (6/9) figure no. title page 18-10 serial bus configuration example using 2-wire serial i/o mode ........................................... 385 18-11 2-wire serial i/o mode timings ................................................................................................. 388 18-12 relt and cmdt operations ..................................................................................................... 389 18-13 example of serial bus configuration using i 2 c bus ................................................................ 390 18-14 i 2 c bus serial data transfer timing ......................................................................................... 391 18-15 start condition ............................................................................................................................ 392 18-16 address ............................................................................................................................... ........ 392 18-17 transfer direction specification ................................................................................................. 392 18-18 acknowledge signal ................................................................................................................... 393 18-19 stop condition ............................................................................................................................ 393 18-20 wait signal ............................................................................................................................... ... 394 18-21 pin configuration ........................................................................................................................ 399 18-22 example of communication from master to slave (with 9-clock wait selected for both master and slave) ......................................................... 401 18-23 example of communication from slave to master (with 9-clock wait selected for both master and slave) ......................................................... 404 18-24 start condition output ................................................................................................................ 408 18-25 slave wait release (transmission) ........................................................................................... 409 18-26 slave wait release (reception) ................................................................................................ 410 18-27 sck0/scl/p27 pin configuration .............................................................................................. 413 18-28 sck0/scl/p27 pin configuration .............................................................................................. 414 18-29 logic circuit of scl signal ........................................................................................................ 414 19-1 serial interface channel 1 block diagram ................................................................................ 416 19-2 timer clock select register 3 format ...................................................................................... 418 19-3 serial operation mode register 1 format ................................................................................ 419 19-4 automatic data transmit/receive control register format .................................................... 420 19-5 automatic data transmit/receive interval specify register format ....................................... 421 19-6 3-wire serial i/o mode timings ................................................................................................. 427 19-7 circuit of switching in transfer bit order .................................................................................. 428 19-8 basic transmission/reception mode operation timings ......................................................... 436 19-9 basic transmission/reception mode flowchart ....................................................................... 437 19-10 buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) ............................................................................................. 438 19-11 basic transmission mode operation timings ........................................................................... 440 19-12 basic transmission mode flowchart ......................................................................................... 441 19-13 buffer ram operation in 6-byte transmission (in basic transmit mode) ............................... 442 19-14 repeat transmission mode operation timing .......................................................................... 444 19-15 repeat transmission mode flowchart ...................................................................................... 445 19-16 buffer ram operation in 6-byte transmission (in repeat transmit mode) ............................ 446 19-17 automatic transmission/reception suspension and restart ................................................... 448 19-18 system configuration when the busy control option is used ................................................. 449 19-19 operation timings when using busy control option (busy0 = 0) ......................................... 450 19-20 busy signal and wait cancel (busy0 = 0) .............................................................................. 451 27 list of figures (7/9) figure no. title page 19-21 operation timings when using busy & strobe control option (busy0 = 0) ......................... 452 19-22 operation timing of the bit slippage detection function through the busy signal (busy0 = 1) ............................................................................................................................... . 453 19-23 automatic data transmit/receive interval ................................................................................ 454 19-24 operation timing with automatic data transmit/receive function performed by internal clock ......................................................................................................................... 455 20-1 serial interface channel 2 block diagram ................................................................................ 458 20-2 baud rate generator block diagram ........................................................................................ 459 20-3 serial operating mode register 2 format ................................................................................ 461 20-4 asynchronous serial interface mode register format ............................................................. 462 20-5 asynchronous serial interface status register format ............................................................ 464 20-6 baud rate generator control register format ........................................................................ 465 20-7 asynchronous serial interface transmit/receive data format ............................................... 478 20-8 asynchronous serial interface transmission completion interrupt request generation timing ............................................................................................................................... ........... 480 20-9 asynchronous serial interface reception completion interrupt request generation timing ............................................................................................................................... ........... 481 20-10 receive error timing .................................................................................................................. 482 20-11 state of receive buffer register (rxb) when receive operation is stopped and whether interrupt request (intsr) is generated or not ........................................................ 483 20-12 3-wire serial i/o mode timing .................................................................................................. 489 20-13 circuit of switching in transfer bit order .................................................................................. 490 20-14 receive completion interrupt request generation timing (isrm = 1) .................................. 491 20-15 period that reading receive buffer register is prohibited ..................................................... 492 21-1 real-time output port block diagram ....................................................................................... 495 21-2 real-time output buffer register configuration ....................................................................... 496 21-3 port mode register 12 format ................................................................................................... 497 21-4 real-time output port mode register format .......................................................................... 497 21-5 real-time output port control register format ........................................................................ 498 22-1 basic configuration of interrupt function .................................................................................. 502 22-2 interrupt request flag register format .................................................................................... 505 22-3 interrupt mask flag register format ......................................................................................... 506 22-4 priority specify flag register format ........................................................................................ 507 22-5 external interrupt mode register 0 format ............................................................................... 508 22-6 external interrupt mode register 1 format ............................................................................... 509 22-7 sampling clock select register format .................................................................................... 510 22-8 noise eliminator input/output timing (during rising edge detection) .................................... 511 22-9 program status word format .................................................................................................... 512 22-10 flowchart from non-maskable interrupt generation to acknowledge ..................................... 514 22-11 non-maskable interrupt request acknowledge timing ............................................................ 514 22-12 non-maskable interrupt request acknowledge operation ....................................................... 515 28 list of figures (8/9) figure no. title page 22-13 interrupt request acknowledge processing algorithm ............................................................. 517 22-14 interrupt request acknowledge timing (minimum time) ......................................................... 518 22-15 interrupt request acknowledge timing (maximum time) ........................................................ 518 22-16 multiple interrupt example .......................................................................................................... 520 22-17 interrupt request hold ............................................................................................................... 522 22-18 basic configuration of test function ......................................................................................... 523 22-19 format of interrupt request flag register 1l .......................................................................... 524 22-20 format of interrupt mask flag register 1l ............................................................................... 524 22-21 key return mode register format ............................................................................................ 525 23-1 memory map when using external device expansion function ............................................. 529 23-2 memory expansion mode register format ............................................................................... 531 23-3 internal memory size switching register format ..................................................................... 532 23-4 external bus type select register format ............................................................................... 533 23-5 instruction fetch from external memory in multiplexed bus mode ......................................... 535 23-6 external memory read timing in multiplexed bus mode ......................................................... 536 23-7 external memory write timing in multiplexed bus mode ......................................................... 537 23-8 external memory read modify write timing in multiplexed bus mode ................................... 538 23-9 instruction fetch from external memory in separate bus mode ............................................. 540 23-10 external memory read timing in separate bus mode ............................................................ 541 23-11 external memory write timing in separate bus mode ............................................................ 542 23-12 external memory read modify write timing in separate bus mode ...................................... 543 24-1 oscillation stabilization time select register format .............................................................. 546 24-2 halt mode released by interrupt request generation .......................................................... 548 24-3 halt mode released by reset input .................................................................................... 549 24-4 stop mode released by interrupt request generation ......................................................... 551 24-5 stop mode released by reset input .................................................................................... 552 25-1 block diagram of reset function .............................................................................................. 553 25-2 timing of reset by reset input ............................................................................................... 554 25-3 timing of reset due to watchdog timer overflow ................................................................... 554 25-4 timing of reset by reset input in stop mode ..................................................................... 554 26-1 block diagram of rom correction ............................................................................................ 559 26-2 correction address registers 0 and 1 format ......................................................................... 560 26-3 correction control register format ........................................................................................... 561 26-4 storing example to eeprom (when one place is corrected) ................................................ 562 26-5 connecting example with eeprom (using 2-wire serial i/o mode) ..................................... 562 26-6 initialization routine ................................................................................................................... 563 26-7 rom correction operation ......................................................................................................... 564 26-8 rom correction example ........................................................................................................... 565 26-9 program transition diagram (when one place is corrected) .................................................. 566 26-10 program transition diagram (when two places are corrected) ............................................. 567 29 list of figures (9/9) figure no. title page 27-1 internal memory size switching register format ..................................................................... 570 27-2 internal extension ram size switching register format ........................................................ 571 27-3 page program mode flowchart ................................................................................................. 574 27-4 page program mode timing ...................................................................................................... 575 27-5 byte program mode flowchart ................................................................................................... 576 27-6 byte program mode timing ....................................................................................................... 577 27-7 prom read timing .................................................................................................................... 578 b-1 development tool configuration ................................................................................................ 600 b-2 tgc-100sdw drawing (for reference only) .......................................................................... 610 b-3 ev-9200gf-100 drawing (for reference only) ....................................................................... 611 b-4 ev-9200gf-100 recommended footprints (for reference only) .......................................... 612 30 list of tables (1/3) table no. title page 1-1 mask options of mask rom versions ......................................................................................... 47 1-2 differences between m pd78078 subseries and m pd78054 subseries ..................................... 47 2-1 mask options of mask rom versions ......................................................................................... 63 2-2 differences between m pd78078y subseries and m pd78054y subseries ................................ 63 3-1 pin input/output circuit types ..................................................................................................... 78 4-1 pin input/output circuit types ..................................................................................................... 96 5-1 internal rom capacities ............................................................................................................ 104 5-2 vector table ............................................................................................................................... . 105 5-3 special function register list ................................................................................................... 115 6-1 port functions ( m pd78078 subseries) ...................................................................................... 132 6-2 port functions ( m pd78078y subseries) .................................................................................... 134 6-3 port configuration ....................................................................................................................... 136 6-4 pull-up resistor options for port 6 ............................................................................................ 146 6-5 pull-up resistor options for port 9 ............................................................................................ 151 6-6 port mode register and output latch settings when using alternate function .................... 158 6-7 comparison between mask rom version and the m pd78p078 and 78p078y ...................... 164 7-1 clock generator configuration ................................................................................................... 166 7-2 relationship between cpu clock and minimum instruction execution time ........................ 169 7-3 maximum time required for cpu clock switchover ............................................................... 178 8-1 timer/event counter operations ............................................................................................... 182 8-2 16-bit timer/event counter interval times ............................................................................... 183 8-3 16-bit timer/event counter square-wave output ranges ...................................................... 184 8-4 16-bit timer/event counter configuration ................................................................................ 185 8-5 intp0/ti00 pin valid edge and cr00 capture trigger valid edge ........................................ 188 8-6 16-bit timer/event counter interval times ............................................................................... 200 8-7 16-bit timer/event count square-wave output ranges ......................................................... 214 9-1 8-bit timer/event counters 1 and 2 interval times ................................................................. 224 9-2 8-bit timer/event counters 1 and 2 square-wave output ranges ........................................ 225 9-3 interval times when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counters ................................................................................ 226 9-4 square-wave output ranges when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counters ....................................................................................... 227 9-5 8-bit timer/event counters 1 and 2 configurations ................................................................. 228 9-6 8-bit timer/event counter 1 interval time ................................................................................ 237 9-7 8-bit timer/event counter 2 interval time ................................................................................ 238 9-8 8-bit timer/event counters 1 and 2 square-wave output ranges ........................................ 240 31 list of tables (2/3) table no. title page 9-9 interval times when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter .................................................................................. 243 9-10 square-wave output ranges when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter ....................................................... 245 10-1 8-bit timer/event counters 5 and 6 interval times ................................................................. 250 10-2 8-bit timer/event counters 5 and 6 square-wave output ranges ........................................ 251 10-3 8-bit timer/event counters 5 and 6 configurations ................................................................. 252 10-4 8-bit timer/event counters 5 and 6 interval times ................................................................. 260 10-5 8-bit timer/event counters 5 and 6 square-wave output ranges ........................................ 263 11-1 interval timer interval time ....................................................................................................... 269 11-2 watch timer configuration ......................................................................................................... 270 11-3 interval timer interval time ....................................................................................................... 274 12-1 watchdog timer runaway detection times ............................................................................. 275 12-2 interval times ............................................................................................................................. 27 6 12-3 watchdog timer configuration .................................................................................................. 277 12-4 watchdog timer runaway detection time ............................................................................... 281 12-5 interval timer interval time ....................................................................................................... 282 13-1 clock output control circuit configuration ............................................................................... 284 14-1 buzzer output control circuit configuration ............................................................................. 289 15-1 a/d converter configuration ...................................................................................................... 293 16-1 d/a converter configuration ...................................................................................................... 310 17-1 differences between channels 0, 1, and 2 ............................................................................... 315 17-2 serial interface channel 0 configuration .................................................................................. 318 17-3 various signals in sbi mode ..................................................................................................... 348 18-1 differences between channels 0, 1, and 2 ............................................................................... 365 18-2 serial interface channel 0 configuration .................................................................................. 368 18-3 serial interface channel 0 interrupt request signal generation ............................................. 371 18-4 signals in i 2 c bus mode ............................................................................................................. 398 19-1 serial interface channel 1 configuration .................................................................................. 416 19-2 interval timing through cpu processing (when the internal clock is operating) .................. 455 19-3 interval timing through cpu processing (when the external clock is operating) ................. 456 20-1 serial interface channel 2 configuration .................................................................................. 458 20-2 serial interface channel 2 operating mode settings ............................................................... 463 32 list of tables (3/3) table no. title page 20-3 relationship between main system clock and baud rate ...................................................... 467 20-4 relationship between asck pin input frequency and baud rate (when brgc is set to 00h) ....................................................................................................... 468 20-5 relationship between main system clock and baud rate ...................................................... 476 20-6 relationship between asck pin input frequency and baud rate (when brgc is set to 00h) ....................................................................................................... 477 20-7 receive error causes ................................................................................................................ 482 21-1 real-time output port configuration .......................................................................................... 495 21-2 operation in real-time output buffer register manipulation ................................................... 496 21-3 real-time output port operating mode and output trigger .................................................... 498 22-1 interrupt source list ................................................................................................................... 500 22-2 various flags corresponding to interrupt request sources .................................................... 504 22-3 times from maskable interrupt request generation to interrupt service ............................... 516 22-4 interrupt request enabled for multiple interrupt during interrupt servicing ............................ 519 22-5 test input factors ....................................................................................................................... 523 22-6 flags corresponding to test input signals ............................................................................... 523 23-1 pin functions in external memory expansion mode ................................................................ 527 23-2 state of port 4 to port 6 pins in external memory expansion mode ....................................... 527 23-3 pin functions in separate bus mode ........................................................................................ 528 23-4 state of port 4 to port 6 and port 8 pins in separate bus mode ............................................ 528 23-5 values when the internal memory size switching register is reset ...................................... 532 24-1 halt mode operating status .................................................................................................... 547 24-2 operation after halt mode release ........................................................................................ 549 24-3 stop mode operating status ................................................................................................... 550 24-4 operation after stop mode release ........................................................................................ 552 25-1 hardware status after reset ...................................................................................................... 555 26-1 rom correction configuration ................................................................................................... 559 27-1 differences between prom and mask rom versions ............................................................ 569 27-2 examples of internal memory size switching register settings ............................................. 570 27-3 examples of internal extension ram size switching register settings ................................. 571 27-4 prom programming operating modes ..................................................................................... 572 a-1 major differences between m pd78078, 78075b subseries, and m pd78070a ........................ 597 b-1 os for ibm pc ............................................................................................................................ 609 b-2 system upgrading from former-type in-circuit emulator for 78k/0 series to ie-78001-r-a ................................................................................................... 609 33 chapter 1 outline ( m pd78078 subseries) 1.1 features internal high-capacity rom and ram notes 1. the capacity of internal prom can be changed by means of the internal memory size switching register (ims). 2. the capacity of internal high-speed ram can be changed by means of the internal expansion ram size switching register (ixs). external memory expansion space: 64 kbytes minimum instruction execution time changeable from high speed (0.4 m s: @ 5.0-mhz operation with main system clock) to ultra-low speed (122 m s: @ 32.768-khz operation with subsystem clock) instruction set suited to system control bit manipulation possible in all address spaces multiply and divide instructions incorporated 88 i/o port pins: (including eight n-ch open-drain port pins) 8-bit resolution a/d converter: 8 channels 8-bit resolution d/a converter: 2 channels serial interface: three channels 3-wire serial i/o/sbi/2-wire serial i/o mode: 1 channel 3-wire serial i/o mode (automatic transmit/receive function): 1 channel 3-wire serial i/o/uart mode: 1 channel timer: seven channels 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 4 channels watch timer : 1 channel watchdog timer : 1 channel 24 vectored interrupt sources two test inputs two types of on-chip clock oscillator circuits (main system clock and subsystem clock) power supply voltage: 1.8 to 5.5 v program memory (rom) data memory part number type 48 kbytes 60 kbytes 60 kbytes note 1 1024 bytes note 2 m pd78076 m pd78078 m pd78p078 internal high-speed ram internal buffer ram internal expansion ram 1024 bytes 32 bytes 1024 bytes 34 chapter 1 outline ( m pd78078 subseries) 1.2 application fields cellular phones, cordless telephones, printers, av equipment, air conditioners, cameras, ppcs, fuzzy home appliances, vending machines, etc. 1.3 ordering information part number package internal rom m pd78076gc-xxx-7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) mask rom m pd78076gc-xxx-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) mask rom m pd78076gf-xxx-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) mask rom m pd78078gc-xxx-7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) mask rom m pd78078gc-xxx-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) mask rom m pd78078gf-xxx-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) mask rom m pd78p078gc-7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) one-time prom m pd78p078gc-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) one-time prom m pd78p078gf-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) one-time prom m pd78p078kl-t 100-pin ceramic wqfn (14 x 20 mm) eprom note under development caution two types of packages are available for the m pd78076gc, 78078gc, and 78p078gc. for the suppliable package, contact an nec sales representative. remark xxx indicates rom code suffix. 35 chapter 1 outline ( m pd78078 subseries) 1.4 quality grade part number package quality grades m pd78076gc-xxx-7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) standard m pd78076gc-xxx-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) standard m pd78076gf-xxx-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) standard m pd78078gc-xxx-7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) standard m pd78078gc-xxx-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) standard m pd78078gf-xxx-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) standard m pd78p078gc-7ea 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) standard m pd78p078gc-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) standard m pd78p078gf-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) standard m pd78p078kl-t 100-pin ceramic wqfn (14 x 20 mm) not assured (for function evaluation only) note under development caution of the above members, the following device with the suffix kl-t should be used only for experiment or function evaluation, because it is not intended for use in equipment that will be mass-produced and require high reliability. ? m pd78p078kl-t remark xxx indicates rom code suffix. please refer to quality grades on nec semiconductor devices(c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. 36 chapter 1 outline ( m pd78078 subseries) 1.5 pin configuration (top view) (1) normal operating mode 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) m pd78076gc-xxx-7ea, 78078gc-xxx-7ea m pd78p078gc-7ea 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) m pd78076gc-xxx-8eu note , 78078gc-xxx-8eu note m pd78p078gc-8eu note note under development 37 chapter 1 outline ( m pd78078 subseries) cautions 1. connect ic (internally connected) pin to v ss directly. 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . remark pin connection in parentheses is for the m pd78p078. 100 p13/ani3 p122/rtp2 p121/rtp1 p120/rtp0 p96 p95 p94 p93 p92 p91 p90 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103 p102 p101/ti6/to6 p100/ti5/to5 p67/astb p66/wait p65/wr 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck v ss p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p80/a0 p81/a1 p82/a2 p83/a3 p84/a4 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 91 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 reset xt1/p07 xt2 v dd x1 x2 ic (v pp ) p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 26 27 28 29 30 31 32 33 34 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 35 p85/a5 p86/a6 p87/a7 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd 38 chapter 1 outline ( m pd78078 subseries) 100-pin plastic qfp (14 x 20 mm) m pd78076gf-xxx-3ba, 78078gf-xxx-3ba m pd78p078gf-3ba 100-pin ceramic wqfn (14 x 20 mm) m pd78p078kl-t cautions 1. connect ic (internally connected) pin to v ss directly. 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . remark pin connection in parentheses is for the m pd78p078. 1 49 48 47 45 43 42 40 39 38 37 35 33 31 44 41 34 32 p16/ani6 2 3 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 4 5 17 26 27 28 29 30 p66/wait p65/wr p64/rd p61 p60 p57/a15 p56/a14 v ss p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p87/a7 p63 p62 p47/ad7 p86/a6 p85/a5 p84/a4 p83/a3 p82/a2 80 79 78 75 74 73 72 71 70 69 68 67 66 65 63 62 61 60 59 58 57 56 77 76 64 55 54 53 52 51 50 36 46 82 83 84 86 88 89 91 92 93 94 96 98 100 87 90 97 99 81 95 85 p120/rtp0 p121/rtp1 p122/rtp2 p125/rtp5 p126/rtp6 p127/rtp7 ic (v pp ) x2 x1 v dd xt2 xt1/p07 reset p00/intp0/ti00 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 av dd av ref0 p10/ani0 p123/rtp3 p124/rtp4 p01/intp1/ti01 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck v ss p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p80/a0 p81/a1 p96 p95 p94 p93 p92 p91 p90 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103 p102 p101/ti6/to6 p100/ti5/to5 p67/astb 39 chapter 1 outline ( m pd78078 subseries) pin identifications a0 to a15 : address bus ad0 to ad7 : address/data bus ani0 to ani7 : analog input ano0, ano1 : analog output asck : asynchronous serial clock astb : address strobe av dd : analog power supply av ref0 , av ref1 : analog reference voltage av ss : analog ground busy : busy buz : buzzer clock ic : internally connected intp0 to intp6 : interrupt from peripherals p00 to p07 : port 0 p10 to p17 : port 1 p20 to p27 : port 2 p30 to p37 : port 3 p40 to p47 : port 4 p50 to p57 : port 5 p60 to p67 : port 6 p70 to p72 : port 7 p80 to p87 : port 8 p90 to p96 : port 9 p100 to p103 : port 10 p120 to p127 : port 12 p130, p131 : port 13 pcl : programmable clock rd : read strobe reset : reset rtp0 to rtp7 : real-time output port rxd : receive data sb0, sb1 : serial bus sck0 to sck2 : serial clock si0 to si2 : serial input so0 to so2 : serial output stb : strobe ti00, ti01 : timer input ti1, ti2, ti5, ti6 : timer input to0 to to2, to5, to6 : timer output txd : transmit data v dd : power supply v pp : programming power supply v ss : ground wait : wait wr : write strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) 40 chapter 1 outline ( m pd78078 subseries) (2) prom programming mode 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) m pd78p078gc-7ea 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) m pd78p078gc-8eu note note under development cautions 1. (l) : connect independently to v ss via a pull-down resistor. 2. v ss : connect to the ground. 3. reset : set to the low level. 4. open : leave open. 1 76 (l) v dd v ss v dd pgm 77 78 79 80 82 83 84 85 86 88 89 91 92 93 94 95 96 98 100 81 87 90 97 99 (l) (l) (l) a9 reset (l) open v dd (l) open v pp (l) 50 49 48 47 46 44 43 42 41 40 38 37 35 34 33 32 31 30 28 26 45 39 36 29 27 a7 a8 a16 a10 a11 a12 a13 v ss a14 a15 oe (l) a2 a3 a4 a5 a6 a0 a1 (l) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 v ss v ss (l) (l) (l) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (l) d7 d6 d5 d4 d3 d2 d1 d0 ce (l) 41 chapter 1 outline ( m pd78078 subseries) 100-pin plastic qfp (14 x 20 mm) m pd78p078gf-3ba 100-pin ceramic wqfn m pd78p078kl-t cautions 1. (l) : connect independently to v ss via a pull-down resistor. 2. v ss : connect to the ground. 3. reset : set to the low level. 4. open : leave open. a0 to a16 : address bus reset : reset ce : chip enable v dd : power supply d0 to d7 : data bus v pp : programming power supply oe : output enable v ss : ground pgm : program 1 49 48 47 45 43 42 40 39 38 37 35 33 31 44 41 34 32 (l) 2 3 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 4 5 17 26 27 28 29 30 (l) ce oe a15 a14 v ss a13 a12 a11 a10 a16 a8 a6 a5 a4 a3 a2 a1 a0 a7 80 79 78 75 74 73 72 71 70 69 68 67 66 65 63 62 61 60 59 58 57 56 77 76 64 55 54 53 52 51 50 36 46 82 83 84 86 88 89 91 92 93 94 96 98 100 87 90 97 99 81 95 85 v pp open (l) v dd open (l) reset (l) v dd 23 v ss 24 pgm v ss d7 d6 d5 d4 d3 d2 d1 d0 (l) (l) (l) (l) (l) v dd v ss (l) (l) (l) (l) (l) a9 42 chapter 1 outline ( m pd78078 subseries) 1.6 78k/0 series expansion the products in the 78k/0 series are listed below. the names in boxes are subseries names. note planned pd78098 80-pin added iebus controller to pd78054 pd78044f 80-pin basic subseries for driving fips, 34 display outputs pd78002 pd78083 pd78002y pd780208 pd780228 pd78044h pd780308 pd78064b pd78064 pd780308y pd78064y pd78098b 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42-/44-pin 100-pin 100-pin 80-pin 100-pin 100-pin 100-pin 80-pin iebus tm supported lcd driving fip tm driving 78k/0 series mass-produced products products under development the subseries whose name ends with y support the i 2 c bus specifications. reduced emi noise version of pd78078 rom-less version of pd78078 reduced emi noise version of pd78054 80-pin enhanced serial i/o of pd78054, reduced emi noise version added uart and d/a to pd78014 and enhanced i/os enhanced a/d of pd780024 enhanced serial i/o of pd78018f reduced emi noise version of pd78018f pd78018f pd78014 pd780001 pd78018fy pd78014y 64-pin 64-pin 64-pin low-voltage (1.8 v) version of pd78014 and enhanced rom/ram size options added a/d and 16-bit timer to pd78002 added a/d to pd78002 basic subseries for control applications equipped with uart and operates at low-voltage (1.8 v) enhanced i/o and fip c/d of pd78044f, 53 display outputs enhanced i/o and fip c/d of pd78044h, 48 display outputs pd780964 pd780924 64-pin 64-pin pd780988 64-pin inverter control enhanced a/d of pd780924 equipped with inverter control circuit and uart, reduced emi noise version enhanced inverter control, timer, and sio of pd780964, expanded rom and ram added n-ch open-drain i/o to pd78044f, 34 display outputs enhanced sio of pd78064, expanded rom and ram reduced emi noise version of pd78064 basic subseries for driving lcds, equipped with uart reduced emi noise version of pd78098 equipped with controller/driver for driving automobile meters pd780973 80-pin meter control 100-pin enhanced serial i/o of pd78078y and functions are defined. 100-pin added timers to pd78054 and enhanced external interface pd78058f pd78054 pd780034 pd780024 pd78014h pd78058fy pd78054y pd780034y pd780024y pd780058 pd780058y note control pd780018ay pd78070a pd78070ay pd78078 pd78078y pd78075b 43 chapter 1 outline ( m pd78078 subseries) the following shows the major differences between subseries products. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd externa l subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a min. value expansion control m pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch e 2 ch 3 ch (uart: 1 ch) 88 1.8 v ? m pd78078 48 k to 60 k m pd78070a e 61 2.7 v m pd780058 24 k to 60 k 2 ch 3 ch (time division 68 1.8 v uart: 1 ch) m pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780034 8 k to 32 k e 8 ch e 3 ch (uart: 1 ch, time 51 1.8 v m pd780024 8 ch e division 3-wire: 1 ch) m pd78014h 2 ch 53 m pd78018f 8 k to 60 k m pd78014 8 k to 32 k 2.7 v m pd780001 8 k e e 1 ch 39 e m pd78002 8 k to 16 k 1 ch e 53 ? m pd78083 e 8 ch 1 ch (uart: 1 ch) 33 1.8 v e inverter m pd780988 32 k to 60 k 3 ch note 1 C 1 ch C 8 ch C 3 ch (uart: 2 ch) 47 4.0 v ? control m pd780964 8 k to 32 k note 2 2 ch (uart: 2 ch) 2.7 v m pd780924 8 ch e fip m pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch e e 2 ch 74 2.7 v e driving m pd780228 48 k to 60 k 3 ch e e 1 ch 72 4.5 v m pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 68 2.7 v m pd78044f 16 k to 40 k 2 ch lcd m pd780308 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch e e 3 ch (time division 57 2.0 v e driving uart: 1 ch) m pd78064b 32 k 2 ch (uart: 1 ch) m pd78064 16 k to 32 k iebus m pd78098b 40 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch e 2 ch 3 ch (uart: 1 ch) 69 2.7 v ? supported m pd78098 32 k to 60 k meter m pd780973 24 k to 32 k 3 ch 1 ch 1 ch 1 ch 5 ch e e 2 ch (uart: 1 ch) 56 4.5 v e control notes 1. 16-bit timer: 2 channels 10-bit timer: 1 channel 2. 10-bit timer: 1 channel 44 chapter 1 outline ( m pd78078 subseries) 1.7 block diagram remarks 1. the internal rom and ram capacities depend on the product. 2. pin connection in parentheses is for the m pd78p078. to0/p30 ti00/intp0/p00 ti01/intp1/p01 interrupt control serial interface 1 a/d converter serial interface 0 watchdog timer 8-bit timer/ event counter 1 16-bit timer/ event counter port 0 external access p01 to p06 8-bit timer/ event counter 2 port 1 p10 to p17 port 2 p20 to p27 port 3 p30 to p37 port 4 p40 to p47 port 5 p50 to p57 port 6 p60 to p67 port 7 p70 to p72 port 8 p80 to p87 port 9 p90 to p96 port 10 p100 to p103 port 12 p120 to p127 port 13 p130, p131 real-time output port rtp0/p120 to rtp7/p127 system control ad0/p40 to ad7/p47 a0/p80 to a7/p87 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p07 xt2 v dd v ss ic (v pp ) ram 78k/0 cpu core rom 8-bit timer/ event counter 5 8-bit timer/ event counter 6 watch timer serial interface 2 d/a converter buzzer output clock output control to1/p31 ti1/p33 to2/p32 ti2/p34 ti5/to5/p100 ti6/to6/p101 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 si2/rxd/p70 so2/txd/p71 sck2/asck/p72 av dd av ss av ref0 ani0/p10 to ani7/p17 av ss av ref1 ano0/p130, ano1/p131 intp0/p00 to intp6/p06 buz/p36 pcl/p35 p00 p07 45 chapter 1 outline ( m pd78078 subseries) 1.8 outline of function internal rom mask rom prom memory 48 kbytes 60 kbytes 60 kbytes note 1 high-speed ram 1024 bytes buffer ram 32 bytes expansion ram 1024 bytes 1024 bytes note 2 memory space 64 kbytes general register 8 bits x 8 x 4 banks with main system clock selected 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@ 5.0-mhz operation) with subsystem clock selected 122 m s (@ 32.768-khz operation) instruction set 16-bit operation multiply/divide (8-bit x 8-bit, 16-bit/8-bit) bit manipulate (set, reset, test, and boolean operation) bcd adjust, etc. i/o port total : 88 cmos input : 2 cmos input/output : 78 n-ch open drain i/o : 8 a/d converter 8-bit resolution x 8 channels d/a converter 8-bit resolution x 2 channels serial interface 3-wire serial i/o/sbi/2-wire serial i/o mode selection possible : 1 channel 3-wire serial i/o mode (maximum 32-byte on-chip automatic transmit/receive function) : 1 channel 3-wire serial i/o/uart mode selection possible : 1 channel timer 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 4 channels watch timer : 1 channel watchdog timer : 1 channel timer output 5 outputs: (14-bit pwm output enable: 1, 8-bit pwm output enable: 2) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (@ 5.0-mhz operation with main system clock) 32.768 khz (@ 32.768-khz operation with subsystem clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (@ 5.0-mhz operation with main system clock) notes 1. the capacity of the internal prom can be changed using the internal memory size switching register (ims). 2. the capacity of the internal expansion ram can be changed using the internal expansion ram size switching register (ixs). item minimum instruction execution time m pd78076 m pd78078 m pd78p078 part number 46 chapter 1 outline ( m pd78078 subseries) item m pd78076 m pd78078 m pd78p078 part number vectored maskable internal: 15 interrupt external: 7 source non-maskable internal: 1 software internal: 1 test input internal: 1 external: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = e40 to +85 c package 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) 100-pin plastic lqfp note (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) ? 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) ? 100-pin ceramic wqfn (14 x 20 mm) ( m pd78p078 only) note under development 47 chapter 1 outline ( m pd78078 subseries) 1.9 mask options the mask rom versions ( m pd78076, 78078) provide pull-up register mask options which allow users to specify whether to connect a pull-up register to a specific port pin when the user places an order for the device production. using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the m pd78078 subseries are shown in table 1-1. table 1-1. mask options of mask rom versions pin names mask options p60 to p63, p90 to p93 pull-up resistor connection can be specified in 1-bit units. 1.10 differences with m pd78054 subseries the m pd78078 subseries is upward-compatible with the m pd78054 subseries. the differences between the two subseries are shown in the table below. the functions and specifications other than those shown in this table are common to these two series. table 1-2. differences between m pd78078 subseries and m pd78054 subseries subseries m pd78054 subseries m pd78078 subseries item no. of i/o ports 69 88 8-bit timer/event counter 2 channnels 4 channels external device address bus separate function address bus separate function expansion function is not provided. is provided. (p80/a0 to p87/a7) power supply voltage v dd = 2.0 to 6.0 v v dd = 1.8 to 5.5 v package 80-pin plastic tqfp (12 x 12 mm) 100-pin plastic tqfp (14 x 14 mm) 80-pin plastic qfp (14 x 14 mm) 100-pin plastic lqfp (14 x 14 mm) 80-pin plastic wqfp (14 x 14 mm) * 100-pin plastic qfp (14 x 20 mm) 100-pin plastic wqfp (14 x 20 mm) * * : only for prom version * : only for prom version 48 [memo] 49 data memory part number type program memory (rom) m pd78076y m pd78078y m pd78p078y chapter 2 outline ( m pd78078y subseries) 2.1 features internal high-capacity rom and ram notes 1. the capacity of internal prom can be changed using the internal memory size switching register (ims). 2. the capacity of internal high-speed ram can be changed using the internal expansion ram size switching register (ixs). external memory expansion space: 64 kbytes minimum instruction execution time changeable from high speed (0.4 m s: @ 5.0-mhz operation with main system clock) to ultra-low speed (122 m s: @ 32.768-khz operation with subsystem clock) instruction set suited to system control bit manipulation possible in all address spaces multiply and divide instructions incorporated 88 i/o port pins: (including eight n-ch open-drain port pins) 8-bit resolution a/d converter: 8 channels 8-bit resolution d/a converter: 2 channels serial interface: three channels 3-wire serial i/o/2-wire serial i/o/i 2 c bus mode: 1 channel 3-wire serial i/o mode (automatic transmit/receive function): 1 channel 3-wire serial i/o/uart mode: 1 channel timer: seven channels 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 4 channels watch timer : 1 channel watchdog timer : 1 channel 24 vectored interrupt sources two test inputs two types of on-chip clock oscillation circuits (main system clock and subsystem clock) power supply voltage: 1.8 to 5.5 v 1024 bytes 1024 bytes note 2 48 kbytes 60 kbytes 60 kbytes note 1 internal high-speed ram internal buffer ram internal expansion ram 1024 bytes 32 bytes 50 chapter 2 outline ( m pd78078y subseries) 2.2 application fields cellular phones, cordless telephones, printers, av equipment, air conditioners, cameras, ppcs, fuzzy home appliances, vending machines, etc. 2.3 ordering information part number package internal rom m pd78076ygc-xxx-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) mask rom m pd78076ygf-xxx-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) mask rom m pd78078ygc-xxx-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) mask rom m pd78078ygf-xxx-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) mask rom m pd78p078ygc-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) one-time prom m pd78p078ygf-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) one-time prom m pd78p078ykl-t 100-pin ceramic wqfn (14 x 20 mm) eprom note under development remark xxx indicates rom code suffix. 51 chapter 2 outline ( m pd78078y subseries) 2.4 quality grade part number package quality grades m pd78076ygc-xxx-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) standard m pd78076ygf-xxx-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) standard m pd78078ygc-xxx-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) standard m pd78078ygf-xxx-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) standard m pd78p078ygc-8eu note 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) standard m pd78p078ygf-3ba 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) standard m pd78p078ykl-t 100-pin ceramic wqfn (14 x 20 mm) not assured (for function evaluation only) note under development caution of the above members, the following device with the suffix kl-t should be used only for experiment or function evaluation, because it is not intended for use in equipment that will be mass-produced and require high reliability. ? m pd78p078ykl-t remark xxx indicates rom code suffix. please refer to quality grades on nec semiconductor devices(c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. 52 chapter 2 outline ( m pd78078y subseries) 2.5 pin configuration (top view) (1) normal operating mode 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) m pd78076ygc-xxx-8eu note , 78078ygc-xxx-8eu note m pd78p078ygc-8eu note note under development 53 chapter 2 outline ( m pd78078y subseries) 100 p13/ani3 p122/rtp2 p121/rtp1 p120/rtp0 p96 p95 p94 p93 p92 p91 p90 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103 p102 p101/ti6/to6 p100/ti5/to5 p67/astb p66/wait p65/wr 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck v ss p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p80/a0 p81/a1 p82/a2 p83/a3 p84/a4 99 98 97 96 95 94 93 92 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 91 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 reset xt1/p07 xt2 v dd x1 x2 ic (v pp ) p127/rtp7 p126/rtp6 p125/rtp5 p124/rtp4 p123/rtp3 26 27 28 29 30 31 32 33 34 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 35 p85/a5 p86/a6 p87/a7 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p46/ad6 p47/ad7 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd cautions 1. connect ic (internally connected) pin to v ss directly. 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . remark pin connection in parentheses is for the m pd78p078y. 54 chapter 2 outline ( m pd78078y subseries) 1 49 48 47 45 43 42 40 39 38 37 35 33 31 44 41 34 32 p16/ani6 2 3 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 4 5 17 26 27 28 29 30 p66/wait p65/wr p64/rd p61 p60 p57/a15 p56/a14 v ss p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p87/a7 p63 p62 p47/ad7 p86/a6 p85/a5 p84/a4 p83/a3 p82/a2 80 79 78 75 74 73 72 71 70 69 68 67 66 65 63 62 61 60 59 58 57 56 77 76 64 55 54 53 52 51 50 36 46 82 83 84 86 88 89 91 92 93 94 96 98 100 87 90 97 99 81 95 85 p120/rtp0 p121/rtp1 p122/rtp2 p125/rtp5 p126/rtp6 p127/rtp7 ic (v pp ) x2 x1 v dd xt2 xt1/p07 reset p00/intp0/ti00 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 av dd av ref0 p10/ani0 p123/rtp3 p124/rtp4 p01/intp1/ti01 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck v ss p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0/sda0 p26/so0/sb1/sda1 p27/sck0/scl p80/a0 p81/a1 p96 p95 p94 p93 p92 p91 p90 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103 p102 p101/ti6/to6 p100/ti5/to5 p67/astb 100-pin plastic qfp (14 x 20 mm) m pd78076ygf-xxx-3ba m pd78078ygf-xxx-3ba, 78p078ygf-3ba 100-pin ceramic wqfn (14 x 20 mm) m pd78p078ykl-t cautions 1. connect ic (internally connected) pin to v ss directly. 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . remark pin connection in parentheses is for the m pd78p078y. 55 chapter 2 outline ( m pd78078y subseries) pin identifications a0 to a15 : address bus ad0 to ad7 : address/data bus ani0 to ani7 : analog input ano0, ano1 : analog output asck : asynchronous serial clock astb : address strobe av dd : analog power supply av ref0 , av ref1 : analog reference voltage av ss : analog ground busy : busy buz : buzzer clock ic : internally connected intp0 to intp6 : interrupt from peripherals p00 to p07 : port 0 p10 to p17 : port 1 p20 to p27 : port 2 p30 to p37 : port 3 p40 to p47 : port 4 p50 to p57 : port 5 p60 to p67 : port 6 p70 to p72 : port 7 p80 to p87 : port 8 p90 to p96 : port 9 p100 to p103 : port 10 p120 to p127 : port 12 p130, p131 : port 13 pcl : programmable clock rd : read strobe reset : reset rtp0 to rtp7 : real-time output port rxd : receive data sb0, sb1 : serial bus sck0 to sck2 : serial clock scl : serial clock sda0, sda1 : serial data si0 to si2 : serial input so0 to so2 : serial output stb : strobe ti00, ti01 : timer input ti1, ti2, ti5, ti6 : timer input to0 to to2, to5, to6 : timer output txd : transmit data v dd : power supply v pp : programming power supply v ss : ground wait : wait wr : write strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) 56 chapter 2 outline ( m pd78078y subseries) (2) prom programming mode 100-pin plastic qfp (fine pitch) (14 x 14 mm, resin thickness 1.45 mm) m pd78p078ygc-7ea 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) m pd78p078ygc-8eu note note under development cautions 1. (l) : connect independently to v ss via a pull-down resistor. 2. v ss : connect to the ground. 3. reset : set to the low level. 4. open : leave open. 1 76 (l) v dd v ss v dd pgm 77 78 79 80 82 83 84 85 86 88 89 91 92 93 94 95 96 98 100 81 87 90 97 99 (l) (l) (l) a9 reset (l) open v dd (l) open v pp (l) 50 49 48 47 46 44 43 42 41 40 38 37 35 34 33 32 31 30 28 26 45 39 36 29 27 a7 a8 a16 a10 a11 a12 a13 v ss a14 a15 oe (l) a2 a3 a4 a5 a6 a0 a1 (l) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 v ss v ss (l) (l) (l) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 (l) d7 d6 d5 d4 d3 d2 d1 d0 ce (l) 57 chapter 2 outline ( m pd78078y subseries) 100-pin plastic qfp (14 x 20 mm) m pd78p078ygf-3ba 100-pin ceramic wqfn m pd78p078ykl-t cautions 1. (l) : connect independently to v ss via a pull-down resistor. 2. v ss : connect to the ground. 3. reset : set to the low level. 4. open : leave open. a0 to a16 : address bus reset : reset ce : chip enable v dd : power supply d0 to d7 : data bus v pp : programming power supply oe : output enable v ss : ground pgm : program 1 49 48 47 45 43 42 40 39 38 37 35 33 31 44 41 34 32 (l) 2 3 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 4 5 17 26 27 28 29 30 (l) ce oe a15 a14 v ss a13 a12 a11 a10 a16 a8 a6 a5 a4 a3 a2 a1 a0 a7 80 79 78 75 74 73 72 71 70 69 68 67 66 65 63 62 61 60 59 58 57 56 77 76 64 55 54 53 52 51 50 36 46 82 83 84 86 88 89 91 92 93 94 96 98 100 87 90 97 99 81 95 85 v pp open (l) v dd open (l) reset (l) v dd v ss pgm v ss d7 d6 d5 d4 d3 d2 d1 d0 (l) (l) (l) (l) (l) v dd v ss (l) (l) (l) (l) (l) a9 58 chapter 2 outline ( m pd78078y subseries) 2.6 78k/0 series expansion the products in the 78k/0 series are listed below. the names in boxes are subseries names. note planned pd78098 80-pin added iebus controller to pd78054 pd78044f 80-pin basic subseries for driving fips, 34 display outputs pd78002 pd78083 pd78002y pd780208 pd780228 pd78044h pd780308 pd78064b pd78064 pd780308y pd78064y pd78098b 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 42-/44-pin 100-pin 100-pin 80-pin 100-pin 100-pin 100-pin 80-pin iebus supported lcd driving fip driving 78k/0 series mass-produced products products under development the subseries whose name ends with y support the i 2 c bus specifications. reduced emi noise version of pd78078 rom-less version of pd78078 reduced emi noise version of pd78054 80-pin enhanced serial i/o of pd78054, reduced emi noise version added uart and d/a to pd78014 and enhanced i/os enhanced a/d of pd780024 enhanced serial i/o of pd78018f reduced emi noise version of pd78018f pd78018f pd78014 pd780001 pd78018fy pd78014y 64-pin 64-pin 64-pin low-voltage (1.8 v) version of pd78014 and enhanced rom/ram size options added a/d and 16-bit timer to pd78002 added a/d to pd78002 basic subseries for control applications equipped with uart and operates at low-voltage (1.8 v) enhanced i/o and fip c/d of pd78044f, 53 display outputs enhanced i/o and fip c/d of pd78044h, 48 display outputs pd780964 pd780924 64-pin 64-pin pd780988 64-pin inverter control enhanced a/d of pd780924 enhanced inverter control, timer, and sio of pd780964, expanded rom and ram equipped with inverter control circuit and uart, reduced emi noise version added n-ch open-drain i/o to pd78044f, 34 display outputs enhanced sio of pd78064, expanded rom and ram reduced emi noise version of pd78064 basic subseries for driving lcds, equipped with uart reduced emi noise version of pd78098 equipped with controller/driver for driving automobile meters pd780973 80-pin meter control 100-pin enhanced serial i/o of pd78078y and functions are defined. 100-pin added timers to pd78054 and enhanced external interface pd78058f pd78054 pd780034 pd780024 pd78014h pd78058fy pd78054y pd780034y pd780024y pd780058 pd780058y note control pd780018ay pd78070a pd78070ay pd78078 pd78078y pd78075b 59 chapter 2 outline ( m pd78078y subseries) major differences among y subseries are tabulated below. function rom configuration of serial interface i /o v dd subseries capacity min. control m pd78078y 48k to 60k 3-wire/2-wire/i 2 c : 1 ch 88 1.8 v 3-wire with automatic transmit/receive function : 1 ch m pd78070ay ? 3-wire/uart : 1 ch 61 2.7 v m pd780018ay 48k to 60k 3-wire with automatic transmit/receive function : 1 ch 88 time division 3-wire : 1 ch i 2 c bus (supports multi-master) : 1 ch m pd780058y 24k to 60k 3-wire/2-wire/i 2 c : 1 ch 68 1.8 v 3-wire with automatic transmit/receive function : 1 ch 3-wire/time division uart : 1 ch m pd78058fy 48k to 60k 3-wire/2-wire/i 2 c : 1 ch 69 2.7 v m pd78054y 16k to 60k 3-wire with automatic transmit/receive function : 1 ch 2.0 v 3-wire/uart : 1 ch m pd780034y 8k to 32k uart : 1 ch 51 1.8 v 3-wire : 1 ch m pd780024y i 2 c bus (supports multi-master) : 1 ch m pd78018fy 8k to 60k 3-wire/2-wire/i 2 c : 1 ch 53 3-wire with automatic transmit/receive function : 1 ch m pd78014y 8k to 32k 3-wire/2-wire/i 2 c : 1 ch 2.7 v 3-wire with automatic transmit/receive function : 1 ch m pd78002y 8k to 16k 3-wire/2-wire/sbi/i 2 c : 1 ch lcd m pd780308y 48k to 60k 3-wire/2-wire/i 2 c : 1 ch 57 2.0 v drive 3-wire/time division uart : 1 ch 3-wire : 1 ch m pd78064y 16k to 32k 3-wire/2-wire/i 2 c : 1 ch 3-wire/uart : 1 ch remark the functions except serial interface are common with subseries without y. 60 chapter 2 outline ( m pd78078y subseries) 2.7 block diagram remarks 1. the internal rom and ram capacities depend on the product. 2. pin connection in parentheses is for the m pd78p078y. to0/p30 ti00/intp0/p00 ti01/intp1/p01 interrupt control serial interface 1 a/d converter serial interface 0 watchdog timer 8-bit timer/ event counter 1 16-bit timer/ event counter port 0 external access p01 to p06 8-bit timer/ event counter 2 port 1 p10 to p17 port 2 p20 to p27 port 3 p30 to p37 port 4 p40 to p47 port 5 p50 to p57 port 6 p60 to p67 port 7 p70 to p72 port 8 p80 to p87 port 9 p90 to p96 port 10 p100 to p103 port 12 p120 to p127 port 13 p130, p131 real-time output port rtp0/p120 to rtp7/p127 system control ad0/p40 to ad7/p47 a0/p80 to a7/p87 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 reset x1 x2 xt1/p07 xt2 v dd v ss ic (v pp ) ram 78k/0 cpu core rom 8-bit timer/ event counter 5 8-bit timer/ event counter 6 watch timer serial interface 2 d/a converter buzzer output clock output control to1/p31 ti1/p33 to2/p32 ti2/p34 p100/ti5/to5 p101/ti6/to6 si0/sb0/sda0/p25 so0/sb1/sda1/p26 sck0/scl/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 si2/rxd/p70 so2/txd/p71 sck2/asck/p72 av dd av ss av ref0 ani0/p10 to ani7/p17 av ss av ref1 ano0/p130, ano1/p131 intp0/p00 to intp6/p06 buz/p36 pcl/p35 p00 p07 61 chapter 2 outline ( m pd78078y subseries) part number 2.8 outline of function mask rom prom 48 kbytes 60 kbytes 60 kbytes note 1 high-speed ram 1024 bytes buffer ram 32 bytes expansion ram 1024 bytes 1024 bytes memory space 64 kbytes general register 8 bits x 8 x 4 banks with main system clock selected 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@ 5.0-mhz operation) with subsystem clock selected 122 m s (@ 32.768-khz operation) instruction set 16-bit operation multiply/divide (8-bit x 8-bit, 16-bit/8-bit) bit manipulate (set, reset, test, and boolean operation) bcd adjust, etc. i/o port total : 88 cmos input : 2 cmos input/output : 78 n-ch open drain i/o : 8 a/d converter 8-bit resolution x 8 channels d/a converter 8-bit resolution x 2 channels serial interface 3-wire serial i/o/2-wire serial i/o/i 2 c bus mode selection : 1 channel possible 3-wire serial i/o mode (maximum 32-byte on-chip automatic transmit/receive function) : 1 channel 3-wire serial i/o/uart mode selection possible : 1 channel timer 16-bit timer/event counter : 1 channel 8-bit timer/event counter : 4 channels watch timer : 1 channel watchdog timer : 1 channel timer output 5 outputs: (14-bit pwm output enable: 1, 8-bit pwm output enable: 2) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (@ 5.0-mhz operation with main system clock) 32.768 khz (@ 32.768-khz operation with subsystem clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (@ 5.0-mhz operation with main system clock) notes 1. the capacity of the internal prom can be changed using the internal memory size switching register (ims). 2. the capacity of the internal expansion ram can be changed using the internal expansion ram size switching register (ixs). rom internal memory minimum instruction execution time m pd78076y m pd78078y m pd78p078y item 62 chapter 2 outline ( m pd78078y subseries) item part number m pd78076y m pd78078y m pd78p078y vectored maskable internal: 15 interrupt external: 7 source non-maskable internal: 1 software internal: 1 test input internal: 1 external: 1 power supply voltage v dd = 1.8 to 5.5 v operating ambient temperature t a = e40 to +85 c package 100-pin plastic lqfp note (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) ? 100-pin plastic qfp (14 x 20 mm, resin thickness 2.7 mm) ? 100-pin ceramic wqfn (14 x 20 mm) ( m pd78p078y only) note under development 63 chapter 2 outline ( m pd78078y subseries) 2.9 mask options the mask rom versions ( m pd78076y, 78078y) provide pull-up register mask options which allow users to specify whether to connect a pull-up register to a specific port pin when the user places an order for the device production. using this mask option when pull-up resistors are required reduces the number of components to add to the device, resulting in board space saving. the mask options provided in the m pd78078y subseries are shown in table 2-1. table 2-1. mask options of mask rom versions pin names mask options p60 to p63, p90 to p93 pull-up resistor connection can be specified in 1-bit units. 2.10 differences with m pd78054y subseries the m pd78078y subseries is upward-compatible with the m pd78054y subseries. the differences between the two subseries are shown in the table below. the functions and specifications other than those shown in this table are common to these two series. table 2-2. differences between m pd78078y subseries and m pd78054y subseries subseries m pd78054y subseries m pd78078y subseries item no. of i/o ports 69 88 8-bit timer/event counter 2 channnels 4 channels external device address bus separate function address bus separate function expansion function is not provided. is provided. (p80/a0 to p87/a7) power supply voltage v dd = 2.0 to 6.0 v v dd = 1.8 to 5.5 v package 80-pin plastic qfp (14 x 14 mm) 100-pin plastic qfp (14 x 20 mm) 80-pin plastic wqfp (14 x 14 mm) * 100-pin plastic lqfp (14 x 14 mm) * : only for prom version 100-pin plastic wqfp (14 x 20 mm) * * : only for prom version 64 [memo] 65 input/ output chapter 3 pin function ( m pd78078 subseries) 3.1 pin function list 3.1.1 normal operating mode pins (1) port pins (1/3) input input pin name input/output function after reset alternate function p00 input input only input intp0/ti00 p01 input/output mode can be specified intp1/ti01 p02 bit-wise. intp2 p03 input/ port 0. if used as an input port, an on-chip intp3 p04 output 8-bit input/output port. pull-up resistor can be connected intp4 p05 by software. intp5 p06 intp6 p07 note 1 input input only input xt1 p10 to p17 port 1. 8-bit input/output port. input/output mode can be specified bit-wise. input ani0 to ani7 if used as input port, an on-chip pull-up resistor can be connected by software note 2 . p20 si1 p21 so1 p22 port 2. sck1 p23 input/ 8-bit input/output port. stb p24 output input/output mode can be specified bit-wise. busy p25 if used as an input port, an on-chip pull-up resistor can be connected by si0/sb0 p26 software. so0/sb1 p27 sck0 notes 1. when the p07/xt1 pin is used as an input port, set the bit 6 (frc) of the processor clock control register (pcc) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator). 2. when pins p10/ani0 to p17/ani7 are used as an analog input of the a/d converter, set port 1 in the input mode. the on-chip pull-up resistor becomes automatically disabled. 66 chapter 3 pin function ( m pd78078 subseries) (1) port pins (2/3) pin name input/output function after reset alternate function p30 to0 p31 to1 p32 port 3. to2 p33 input/ 8-bit input/output port. ti1 p34 output input/output mode can be specified bit-wise. ti2 p35 if used as an input port, an on-chip pull-up resistor can be connected by pcl p36 software. buz p37 port 4. 8-bit input/output port. input/ input/output mode can be specified in 8-bit units. output if used as an input port, an on-chip pull-up resistor can be conne cted by software. test input flag (krif) is set to 1 by falling edge detection. port 5. 8-bit input/output port. p50 to p57 leds can be driven directly. input a8 to a15 input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p61 p62 port 6. p63 input/ 8-bit input/output port. p64 output input/output mode can be if used as an input port, an on-chip input rd p65 specified bit-wise. pull-up resistor can be connected wr p66 by software. wait p67 astb port 7. input/ 3-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 8. input/ 8-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. input p40 to p47 input ad0 to ad7 n-ch open drain input/output port. on-chip pull-up resistor can be specified by mask option. (mask rom version only). leds can be driven directly. input/ output p70 si2/rxd p71 input so2/txd p72 sck2/asck p80 to p87 input a0 to a7 67 chapter 3 pin function ( m pd78078 subseries) input/ output n-ch open-drain input/output port. on-chip pull-up resistor can be specified by mask option. (mask rom version only). leds can be driven directly. (1) port pins (3/3) pin name input/output function after reset alternate function p90 p91 port 9. p92 7-bit input/output port. p93 input/output mode can be input p94 specified bit-wise. if used as an input port, an on-chip p95 pull-up resistor can be connected p96 by software. port 10. input/ 4-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 12. input/ 8-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 13. input/ 2-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p100 ti5/to5 p101 input ti6/to6 p102, p103 p120 to p127 input rtp0 to rtp7 p130, p131 input ano0, ano1 68 chapter 3 pin function ( m pd78078 subseries) input/ output serial interface serial data input/output input (2) non-port pins (1/2) pin name input/output function after reset alternate function intp0 p00/ti00 intp1 p01/ti01 intp2 external interrupt request inputs with specifiable valid edges (rising edge, p02 intp3 input falling edge, both rising and falling edges). input p03 intp4 p04 intp5 p05 intp6 p06 si0 p25/sb0 si1 input serial interface serial data input input p20 si2 p70/rxd so0 p26/sb1 so1 output serial interface serial data output input p21 so2 p71/txd sb0 input/ p25/si0 sb1 output p26/so0 sck0 p27 sck1 serial interface serial clock input/output input p22 sck2 p72/asck stb output serial interface automatic transmit/receive strobe output input p23 busy input serial interface automatic transmit/receive busy input input p24 rxd input asynchronous serial interface serial data input input p70/si2 txd output asynchronous serial interface serial data output input p71/so2 asck input asynchronous serial interface serial clock input input p72/sck2 ti00 external count clock input to 16-bit timer (tm0) p00/intp0 ti01 capture trigger signal input to capture register (cr00) p01/intp1 ti1 external count clock input to 8-bit timer (tm1) p33 ti2 external count clock input to 8-bit timer (tm2) p34 ti5 external count clock input to 8-bit timer (tm5) p100/to5 ti6 external count clock input to 8-bit timer (tm6) p101/to6 to0 16-bit timer (tm0) output (also used for 14-bit pwm output) p30 to1 8-bit timer (tm1) output p31 to2 output 8-bit timer (tm2) output input p32 to5 8-bit timer (tm5) output (also used for 8-bit pwm output) p100/ti5 to6 8-bit timer (tm6) output (also used for 8-bit pwm output) p101/ti6 pcl output clock output (for main system clock and subsystem clock trimming) input p35 buz output buzzer output input p36 rtp0 to rtp7 output real-time output port outputting data in synchronization with trigger input p120 to p127 input input 69 chapter 3 pin function ( m pd78078 subseries) (2) non-port pins (2/2) pin name input/output function after reset alternate function ad0 to ad7 input/output low-order address/data bus when expanding external memory input p40 to p47 a0 to a7 output low-order address bus when expanding external memory input p80 to p87 a8 to a15 output high-order address bus when expanding external memory input p50 to p57 rd strobe signal output for read operation from external memory p64 wr strobe signal output for write operation to external memory p65 wait input wait insertion when accessing external memory input p66 strobe output externally latching address information output to ports 4, 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 ano0, ano1 output d/a converter analog output input p130, p131 av ref0 input a/d converter reference voltage input av ref1 input d/a converter reference voltage input av dd a/d converter analog power supply. connect to v dd . av ss a/d converter, d/a converter ground potential. connect to v ss . reset input system reset input x1 input x2 xt1 input input p07 xt2 v dd positive power supply high-voltage application for program write/verify. connect directly to v ss in normal operating mode. v ss ground potential ic internally connected. connect directly to v ss. 3.1.2 prom programming mode pins ( m pd78p078 only) pin name input/output function prom programming mode setting. reset input when +5 v or +12.5 v is applied to the v pp pin or a low level voltage is applied to the reset pin, the prom programming mode is set. v pp input high-voltage application for prom programming mode setting and program write/verify. a0 to a16 input address bus d0 to d7 input/output data bus ce input prom enable input/program pulse input oe input read strobe input to prom pgm input program/program inhibit input in prom programming mode v dd positive power supply v ss ground potential output input astb output input p67 v pp crystal connection for main system clock oscillation crystal connection for subsystem clock oscillation 70 chapter 3 pin function ( m pd78078 subseries) 3.2 description of pin functions 3.2.1 p00 to p07 (port 0) these are 8-bit input/output ports. besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. the following operating modes can be specified bit-wise. (1) port mode p00 and p07 function as input-only ports and p01 to p06 function as input/output ports. p01 to p06 can be specified for input or output ports bit-wise with a port mode register 0 (pm0). when they are used as input ports, on-chip pull-up resistors can be connected to them by defining the pull-up resistor option register l (puol). (2) control mode in this mode, these ports function as an external interrupt request input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) intp0 to intp6 intp0 to intp6 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). intp0 or intp1 becomes a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. (b) ti00 pin for external count clock input to 16-bit timer/event counter (c) ti01 pin for capture trigger signal to capture register (cr00) of 16-bit timer/event counter (d) xt1 crystal connect pin for subsystem clock oscillation 3.2.2 p10 to p17 (port 1) these are 8-bit input/output ports. besides serving as input/output ports, they function as an a/d converter analog input. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with a port mode register 1 (pm1). if used as input ports, on-chip pull-up resistors can be connected to them by defining the pull-up resistor option register l (puol). (2) control mode these ports function as a/d converter analog input pins (ani0 to ani7). the pull-up resistor is automatically disabled when the pins are specified for analog input. 71 chapter 3 pin function ( m pd78078 subseries) 3.2.3 p20 to p27 (port 2) these are 8-bit input/output ports. besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 2 (pm2). when they are used as input ports, on-chip pull-up resistors can be connected to them by defining the pull-up resistor option register l (puol). (2) control mode these ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output functions. (a) si0, si1, so0, so1 serial interface serial data input/output pins (b) sck0 and sck1 serial interface serial clock input/output pins (c) sb0 and sb1 nec standard serial bus interface input/output pins (d) busy serial interface automatic transmit/receive busy input pins (e) stb serial interface automatic transmit/receive strobe output pins caution when this port is used as a serial interface, the i/o and output latches must be set according to the function the user requires. for the setting, refer to figure 17-4. serial operation mode register 0 format and figure 19-3. serial operation mode register 1 format. 72 chapter 3 pin function ( m pd78078 subseries) 3.2.4 p30 to p37 (port 3) these are 8-bit input/output ports. beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 3 (pm3). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register l (puol). (2) control mode these ports function as timer input/output, clock output, and buzzer output. (a) ti1 and ti2 pin for external count clock input to the 8-bit timer/event counter. (b) to0 to to2 timer output pins. (c) pcl clock output pin. (d) buz buzzer output pin. 3.2.5 p40 to p47 (port 4) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address/data bus. the test input flag (krif) can be set to 1 by detecting a falling edge. the following operating mode can be specified in 8-bit units. (1) port mode these ports function as 8-bit input/output ports. they can be specified in 8-bit units for input or output ports by using the memory expansion mode register (mm). when they are used as input ports, on-chip pull-up resistors can be connected to them by defining the pull-up resistor option register l (puol). (2) control mode these ports function as low-order address/data bus pins (ad0 to ad7) in external memory expansion mode. when pins are used as an address/data bus, the on-chip pull-up resistor is automatically disabled. 73 chapter 3 pin function ( m pd78078 subseries) 3.2.6 p50 to p57 (port 5) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address bus. port 5 can drive leds directly. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 5 (pm5). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register l (puol). (2) control mode these ports function as high-order address bus pins (a8 to a15) in external memory expansion mode. when pins are used as an address bus, the on-chip pull-up resistor is automatically disabled. 3.2.7 p60 to p67 (port 6) these are 8-bit input/output ports. besides serving as input/output ports, they are used for control in external memory expansion mode. p60 to p63 can drive leds directly. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 6 (pm6). p60 to p63 are n-ch open-drain outputs. mask rom version can contain pull-up resistors with the mask option. when p64 to p67 are used as input ports, on-chip pull-up resistors can be connected by defining the pull- up resistor option register l (puol). (2) control mode these ports function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. when a pin is used as a control signal output, the on-chip pull-up resistor is automatically disabled. caution when external wait is not used in external memory expansion mode, p66 can be used as an input/output port. 74 chapter 3 pin function ( m pd78078 subseries) 3.2.8 p70 to p72 (port 7) this is a 3-bit input/output port. in addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. the following operating modes can be specified bit-wise. (1) port mode port 7 functions as a 3-bit input/output port. bit-wise specification as an input port or output port is possible by means of port mode register 7 (pm7). when used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register l (puol). (2) control mode port 7 functions as serial interface data input/output and clock input/output. (a) si2, so2 serial interface serial data input/output pins (b) sck2 serial interface serial clock input/output pin. (c) rxd, txd asynchronous serial interface serial data input/output pins. (d) asck asynchronous serial interface serial clock input/output pin. caution when this port is used as a serial interface, the i/o and output latches must be set according to the function the user requires. for the setting, refer to the operation mode setting list in table 20-2. serial interface channel 2. 3.2.9 p80 to p87 (port 8) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address bus. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 8 (pm8). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). (2) control mode these ports function as lower address bus pins (a0 to a7) in external memory expansion mode. when a pin is used as an address bus, the on-chip pull-up resistor is automatically not used. 75 chapter 3 pin function ( m pd78078 subseries) 3.2.10 p90 to p96 (port 9) these are 7-bit input/output ports. p90 to p93 can drive leds directly. they can be specified bit-wise as input or output ports with port mode register 9 (pm9). p90 to p93 are n-ch open-drain pins. mask rom version product can contain pull-up resistors with the mask option. when p94 to p96 are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). 3.2.11 p100 to p103 (port 10) these are 4-bit input/output ports. besides serving as input/output ports, they function as a timer input/output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 4-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 10 (pm10). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). (2) control mode these ports function as timer input/output. (a) ti5 and ti6 pins for external count clock input to 8-bit timer/event counter. (b) to5 to to6 pins for timer output. 3.2.12 p120 to p127 (port 12) these are 8-bit input/output ports. besides serving as input/output ports, they function as a real-time output port. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 12 (pm12). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). (2) control mode these ports function as real-time output ports (rtp0 to rtp7) outputting data in synchronization with a trigger. 76 chapter 3 pin function ( m pd78078 subseries) 3.2.13 p130 and p131 (port 13) these are 2-bit input/output ports. besides serving as input/output ports, they are used for d/a converter analog output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 2-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 13 (pm13). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). (2) control mode these ports allow d/a converter analog output (ano0 and ano1). caution when only either one of the d/a converter channels is used with av ref1 < v dd , the other pins that are not used as analog outputs must be set as follows: ? set pm13x bit of the port mode register 13 (pm13) to 1 (input mode) and connect the pin to v ss . ? set pm13x bit of the port mode register 13 (pm13) to 0 (output mode) and the output latch to 0, to output low level from the pin. 3.2.14 av ref0 a/d converter reference voltage input pin. when a/d converter is not used, connect this pin to v ss . 3.2.15 av ref1 d/a converter reference voltage input pin. when d/a converter is not used, connect this pin to v dd . 3.2.16 av dd analog power supply pin of a/d converter. always use the same voltage as that of the v dd pin even when a/d converter is not used. 3.2.17 av ss this is a ground voltage pin of a/d converter and d/a converter. always use the same voltage as that of the v ss pin even when a/d converter or d/a converter is not used. 3.2.18 reset this is a low-level active system reset input pin. 3.2.19 x1 and x2 crystal resonator connect pins for main system clock oscillation. for external clock supply, input it to x1 and its inverted signal to x2. 3.2.20 xt1 and xt2 crystal resonator connect pins for subsystem clock oscillation. for external clock supply, input it to xt1 and its inverted signal to xt2. 77 chapter 3 pin function ( m pd78078 subseries) 3.2.21 v dd positive power supply pin 3.2.22 v ss ground potential pin 3.2.23 v pp ( m pd78p078 only) high-voltage apply pin for prom programming mode setting and program write/verify. connect directly to v ss in normal operating mode. 3.2.24 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the m pd78078 at delivery. connect it directly to the v ss with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the user?s program may not run normally. ? connect ic pins to v ss pins directly . v ss ic as short as possible 78 chapter 3 pin function ( m pd78078 subseries) 3.3 input/output circuits and recommended connection of unused pins table 2-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. refer to figure 3-1 for the configuration of the input/output circuit of each type. table 3-1. pin input/output circuit types (1/2) pin name input/output input/output recommended connection of unused pins circuit type p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-a input/output connect independently via a resistor p02/intp2 to v ss. p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11 input/output connect independently via a p20/si1 8-a resistor to v dd or v ss . p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0 10-a p26/so0/sb1 p27/sck0 p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40/ad0 to p47/ad7 5-e input/output connect independently via a resistor to v dd . 79 chapter 3 pin function ( m pd78078 subseries) table 3-1. pin input/output circuit types (2/2) pin name input/output input/output recommended connection of unused pins circuit type p50/a8 to p57/a15 5-a input/output connect independently via a resistor to v dd or v ss . p60 to p63 (mask rom version) 13-b input/output connect independently via a resistor p60 to p63 ( m pd78p078) 13-d to v dd . p64/rd 5-a input/output connect independently via a resistor p65/wr to v dd or v ss . p66/wait p67/astb p70/si2/rxd 8-a p71/so2/txd 5-a p72/sck2/asck 8-a p80/a0 to p87/a7 5-a p90 to p93 (mask rom version) 13-b input/output connect independently via a resistor p90 to p93 ( m pd78p078) 13-d to v dd . p94 to p96 5-a input/output connect independently via a resistor p100/ti5/to5 8-a to v dd or v ss . p101/ti6/to6 p102, p103 5-a p120/rtp0 to p127/rtp7 5-a p130/ano0, p131/ano1 12-a input/output connect independently via a resistor to v ss . reset 2 input ? xt2 16 ? open av ref0 ? connect to v ss . av ref1 connect to v dd . av dd av ss connect to v ss . ic (mask rom version) connect directly to v ss . v pp ( m pd78p078) 80 chapter 3 pin function ( m pd78078 subseries) figure 3-1. list of pin input/output circuits (1/2) in pullup enable v dd p-ch in/out input enable output disable data v dd p-ch n-ch type 2 type 5-a schmitt-triggered input with hysteresis characteristics type 5-e type 11 type 10-a type 8-a pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch pullup enable v dd p-ch in/out open drain output disable data v dd p-ch n-ch pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch p-ch comparator n-ch input enable v ref (threshold voltage) + C 81 chapter 3 pin function ( m pd78078 subseries) figure 3-1. list of pin input/output circuits (2/2) type 12-a type 13-b type 13-d output disable v dd n-ch in/out rd medium breakdown input buffer data p-ch xt2 xt1 feedback cut-off p-ch type 16 output disable v dd v dd n-ch mask option in/out rd medium breakdown input buffer data p-ch pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch input enable p-ch n-ch analog output voltage 82 [memo] 83 input/ output chapter 4 pin function ( m pd78078y subseries) 4.1 pin function list 4.1.1 normal operating mode pins (1) port pins (1/3) input input pin name input/output function after reset alternate function p00 input input only input intp0/ti00 p01 input/output mode can be specified intp1/ti01 p02 bit-wise. intp2 p03 input/ port 0. if used as an input port, an on-chip intp3 p04 output 8-bit input/output port. pull-up resistor can be connected intp4 p05 by software. intp5 p06 intp6 p07 note 1 input input only input xt1 p10 to p17 port 1. 8-bit input/output port. input/output mode can be specified bit-wise. input ani0 to ani7 if used as input port, an on-chip pull-up resistor can be connected by software note 2 . p20 si1 p21 so1 p22 port 2. sck1 p23 input/ 8-bit input/output port. stb p24 output input/output mode can be specified bit-wise. busy p25 if used as an input port, an on-chip pull-up resistor can be connected by si0/sb0/sda0 p26 software. so0/sb1/sda1 p27 sck0/scl notes 1. when the p07/xt1 pin is used as an input port, set the bit 6 (frc) of the processor clock control register (pcc) to 1 (do not use the feedback resistor internal to the subsystem clock oscillator). 2. when pins p10/ani0 to p17/ani7 are used as an analog input of the a/d converter, set port 1 in the input mode. the on-chip pull-up resistor becomes automatically disabled. 84 chapter 4 pin function ( m pd78078y subseries) input p40 to p47 input ad0 to ad7 (1) port pins (2/3) pin name input/output function after reset alternate function p30 to0 p31 to1 p32 port 3. to2 p33 input/ 8-bit input/output port. ti1 p34 output input/output mode can be specified bit-wise. ti2 p35 if used as an input port, an on-chip pull-up resistor can be connected by pcl p36 software. buz p37 port 4. 8-bit input/output port. input/ input/output mode can be specified in 8-bit units. output if used as an input port, an on-chip pull-up resistor can be connected by software. test input flag (krif) is set to 1 by falling edge detection. port 5. 8-bit input/output port. p50 to p57 leds can be driven directly. input a8 to a15 input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p61 p62 port 6. p63 input/ 8-bit input/output port. p64 output input/output mode can be if used as an input port, an on-chip input rd p65 specified bit-wise. pull-up resistor can be connected wr p66 by software. wait p67 astb port 7. input/ 3-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 8. input/ 8-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. n-ch open drain input/output port. on-chip pull-up resistor can be specified by mask option. (mask rom version only). leds can be driven directly. input/ output p70 si2/rxd p71 input so2/txd p72 sck2/asck p80 to p87 input a0 to a7 85 chapter 4 pin function ( m pd78078y subseries) input/ output n-ch open-drain input/output port. on-chip pull-up resistor can be specified by mask option. (mask rom version only). leds can be driven directly. (1) port pins (3/3) pin name input/output function after reset alternate function p90 p91 port 9. p92 7-bit input/output port. p93 input/output mode can be input p94 specified bit-wise. if used as an input port, an on-chip p95 pull-up resistor can be connected p96 by software. port 10. input/ 4-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 12. input/ 8-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 13. input/ 2-bit input/output port. output input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p120 to p127 input rtp0 to rtp7 p130 to p131 input ano0 to ano1 p100 ti5/to5 p101 input ti6/to6 p102, p103 86 chapter 4 pin function ( m pd78078y subseries) (2) non-port pins (1/2) pin name input/output function after reset alternate function intp0 p00/ti00 intp1 p01/ti01 intp2 external interrupt request inputs with specifiable valid edges (rising edge, p02 intp3 input falling edge, both rising and falling edges). input p03 intp4 p04 intp5 p05 intp6 p06 si0 p25/sb0/sda0 si1 input serial interface serial data input input p20 si2 p70/rxd so0 p26/sb1/sda1 so1 output serial interface serial data output input p21 so2 p71/txd sb0 p25/si0/sda0 sb1 input/ p26/so0/sda1 sda0 output p25/si0/sb0 sda1 p26/so0/sb1 sck0 p27/scl sck1 p22 sck2 p72/asck scl p27/sck0 stb output serial interface automatic transmit/receive strobe output input p23 busy input serial interface automatic transmit/receive busy input input p24 rxd input asynchronous serial interface serial data input input p70/si2 txd output asynchronous serial interface serial data output input p71/so2 asck input asynchronous serial interface serial clock input input p72/sck2 ti00 external count clock input to 16-bit timer (tm0) p00/intp0 ti01 capture trigger signal input to capture register (cr00) p01/intp1 ti1 external count clock input to 8-bit timer (tm1) p33 ti2 external count clock input to 8-bit timer (tm2) p34 ti5 external count clock input to 8-bit timer (tm5) p100/to5 ti6 external count clock input to 8-bit timer (tm6) p101/to6 to0 16-bit timer (tm0) output (also used for 14-bit pwm output) p30 to1 8-bit timer (tm1) output p31 to2 output 8-bit timer (tm2) output input p32 to5 8-bit timer (tm5) output (also used for 8-bit pwm output) p100/ti5 to6 8-bit timer (tm6) output (also used for 8-bit pwm output) p101/ti6 pcl output clock output (for main system clock and subsystem clock trimming) input p35 buz output buzzer output input p36 rtp0 to rtp7 output real-time output port outputting data in synchronization with trigger input p120 to p127 input input input/ output serial interface serial data input/output input serial interface serial clock input/output input 87 chapter 4 pin function ( m pd78078y subseries) v pp (2) non-port pins (2/2) pin name input/output function after reset alternate function ad0 to ad7 input/output low-order address/data bus when expanding external memory input p40 to p47 a0 to a7 output low-order address bus when expanding external memory input p80 to p87 a8 to a15 output high-order address bus when expanding external memory input p50 to p57 rd strobe signal output for read operation from external memory p64 wr strobe signal output for write operation to external memory p65 wait input wait insertion when accessing external memory input p66 strobe output externally latching address information output to ports 4, 5 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 ano0, ano1 output d/a converter analog output input p130, p131 av ref0 input a/d converter reference voltage input av ref1 input d/a converter reference voltage input av dd a/d converter analog power supply. connect to v dd . av ss a/d converter, d/a converter ground potential. connect to v ss . reset input system reset input x1 input x2 xt1 input input p07 xt2 v dd positive power supply high-voltage application for program write/verify. connect directly to v ss in normal operating mode. v ss ground potential ic internally connected. connect directly to v ss. 4.1.2 prom programming mode pins ( m pd78p078y only) pin name input/output function prom programming mode setting. reset input when +5 v or +12.5 v is applied to the v pp pin or a low level voltage is applied to the reset pin, the prom programming mode is set. v pp input high-voltage application for prom programming mode setting and program write/verify. a0 to a16 input address bus d0 to d7 input/output data bus ce input prom enable input/program pulse input oe input read strobe input to prom pgm input program/program inhibit input in prom programming mode v dd positive power supply v ss ground potential output input astb output input p67 crystal connection for main system clock oscillation crystal connection for subsystem clock oscillation 88 chapter 4 pin function ( m pd78078y subseries) 4.2 description of pin functions 4.2.1 p00 to p07 (port 0) these are 8-bit input/output ports. besides serving as input/output ports, they function as an external interrupt request input, an external count clock input to the timer, a capture trigger signal input, and crystal connection for subsystem oscillation. the following operating modes can be specified bit-wise. (1) port mode p00 and p07 function as input-only ports and p01 to p06 function as input/output ports. p01 to p06 can be specified for input or output ports bit-wise with a port mode register 0 (pm0). when they are used as input ports, on-chip pull-up resistors can be connected to them by defining the pull-up resistor option register l (puol). (2) control mode in this mode, these ports function as an external interrupt request input, an external count clock input to the timer, and crystal connection for subsystem clock oscillation. (a) intp0 to intp6 intp0 to intp6 are external interrupt request input pins which can specify valid edges (rising edge, falling edge, and both rising and falling edges). intp0 or intp1 becomes a 16-bit timer/event counter capture trigger signal input pin with a valid edge input. (b) ti00 pin for external count clock input to 16-bit timer/event counter (c) ti01 pin for capture trigger signal to capture register (cr00) of 16-bit timer/event counter (d) xt1 crystal connect pin for subsystem clock oscillation 4.2.2 p10 to p17 (port 1) these are 8-bit input/output ports. besides serving as input/output ports, they function as an a/d converter analog input. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with a port mode register 1 (pm1). if used as input ports, on-chip pull-up resistors can be connected to these ports by defining the pull-up resistor option register l (puol). (2) control mode these ports function as a/d converter analog input pins (ani0 to ani7). the on-chip pull-up resistor is automatically disabled when the pins specified for analog input. 89 chapter 4 pin function ( m pd78078y subseries) 4.2.3 p20 to p27 (port 2) these are 8-bit input/output ports. besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output functions. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 2 (pm2). when they are used as input ports, on-chp pull-up resistors can be connected to them by defining the pull-up resistor option register l (puol). (2) control mode these ports function as serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output functions. (a) si0, si1, so0, so1, sb0, sb1, sda0, sda1 serial interface serial data input/output pins (b) sck0, sck1, scl serial interface serial clock input/output pins (c) busy serial interface automatic transmit/receive busy input pins (d) stb serial interface automatic transmit/receive strobe output pins caution when this port is used as a serial interface, the i/o and output latches must be set according to the function the user requires. for the setting, refer to figure 18-4. serial operation mode register 0 format and figure 19-3. serial operation mode register 1 format. 90 chapter 4 pin function ( m pd78078y subseries) 4.2.4 p30 to p37 (port 3) these are 8-bit input/output ports. beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 3 (pm3). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register l (puol). (2) control mode these ports function as timer input/output, clock output, and buzzer output. (a) ti1 and ti2 pin for external count clock input to the 8-bit timer/event counter. (b) to0 to to2 timer output pins. (c) pcl clock output pin. (d) buz buzzer output pin. 4.2.5 p40 to p47 (port 4) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address/data bus. the test input flag (krif) can be set to 1 by detecting a falling edge. the following operating mode can be specified in 8-bit units. (1) port mode these ports function as 8-bit input/output ports. they can be specified in 8-bit units for input or output ports by using the memory expansion mode register (mm). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register l (puol). (2) control mode these ports function as low-order address/data bus pins (ad0 to ad7) in external memory expansion mode. when pins are used as an address/data bus, the on-chip pull-up resistor is automatically disabled. 91 chapter 4 pin function ( m pd78078y subseries) 4.2.6 p50 to p57 (port 5) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address bus. port 5 can drive leds directly. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input/output ports with port mode register 5 (pm5). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register l (puol). (2) control mode these ports function as high-order address bus pins (a8 to a15) in external memory expansion mode. when pins are used as an address bus, the on-chip pull-up resistor is automatically disabled. 4.2.7 p60 to p67 (port 6) these are 8-bit input/output ports. besides serving as input/output ports, they are used for control in external memory expansion mode. p60 to p63 can drive leds directly. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 6 (pm6). p60 to p63 are n-ch open-drain outputs. mask rom version can contain pull-up resistors with the mask option. when p64 to p67 are used as input ports, on-chip pull-up resistors can be connected by defining the pull- up resistor option register l (puol). (2) control mode these ports function as control signal output pins (rd, wr, wait, astb) in external memory expansion mode. when a pin is used as a control signal output, the on-chip pull-up resistor is automatically disabled. caution when external wait is not used in external memory expansion mode, p66 can be used as an input/output port. 92 chapter 4 pin function ( m pd78078y subseries) 4.2.8 p70 to p72 (port 7) this is a 3-bit input/output port. in addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions. the following operating modes can be specified bit-wise. (1) port mode port 7 functions as a 3-bit input/output port. bit-wise specification as an input port or output port is possible by means of port mode register 7 (pm7). when used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register l (puol). (2) control mode port 7 functions as serial interface data input/output and clock input/output. (a) si2, so2 serial interface serial data input/output pins (b) sck2 serial interface serial clock input/output pin. (c) rxd, txd asynchronous serial interface serial data input/output pins. (d) asck asynchronous serial interface serial clock input/output pin. caution when this port is used as a serial interface, the i/o and output latches must be set according to the function the user requires. for the setting, refer to the operation mode setting list in table 20-2. serial interface channel 2. 4.2.9 p80 to p87 (port 8) these are 8-bit input/output ports. besides serving as input/output ports, they function as an address bus. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 8 (pm8). when they are used as input ports,on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). (2) control mode these ports function as lower address bus pins (a0 to a7) in external memory expansion mode. when a pin is used as an address bus, the on-chip pull-up resistor is automatically not used. 93 chapter 4 pin function ( m pd78078y subseries) 4.2.10 p90 to p96 (port 9) these are 7-bit input/output ports. p90 to p93 can drive leds directly. they can be specified bit-wise as input or output ports with port mode register 9 (pm9). p90 to p93 are n-ch open-drain pins. mask rom version product can contain pull-up resistors with the mask option. when p94 to p96 are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). 4.2.11 p100 to p103 (port 10) these are 4-bit input/output ports. besides serving as input/output ports, they function as a timer input/output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 4-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 10 (pm10). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). (2) control mode these ports function as timer input/output. (a) ti5 and ti6 pins for external clock input to 8-bit timer/event counter. (b) to5 to to6 pins for timer output. 4.2.12 p120 to p127 (port 12) these are 8-bit input/output ports. besides serving as input/output ports, they function as a real-time output port. the following operating modes can be specified bit-wise. (1) port mode these ports function as 8-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 12 (pm12). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). (2) control mode these ports function as real-time output ports (rtp0 to rtp7) outputting data in synchronization with a trigger. 94 chapter 4 pin function ( m pd78078y subseries) 4.2.13 p130 and p131 (port 13) these are 2-bit input/output ports. besides serving as input/output ports, they are used for d/a converter analog output. the following operating modes can be specified bit-wise. (1) port mode these ports function as 2-bit input/output ports. they can be specified bit-wise as input or output ports with port mode register 13 (pm13). when they are used as input ports, on-chip pull-up resistors can be connected by defining the pull-up resistor option register h (puoh). (2) control mode these ports allow d/a converter analog output (ano0 and ano1). caution when only either one of the d/a converter channels is used with av ref1 < v dd , the other pins that are not used as analog outputs must be set as follows: ? set pm13x bit of the port mode register 13 (pm13) to 1 (input mode) and connect the pin to v ss . ? set pm13x bit of the port mode register 13 (pm13) to 0 (output mode) and the output latch to 0, to output low level from the pin. 4.2.14 av ref0 a/d converter reference voltage input pin. when a/d converter is not used, connect this pin to v ss . 4.2.15 av ref1 d/a converter reference voltage input pin. when d/a converter is not used, connect this pin to v dd . 4.2.16 av dd analog power supply pin of a/d converter. always use the same voltage as that of the v dd pin even when a/d converter is not used. 4.2.17 av ss this is a ground voltage pin of a/d converter and d/a converter. always use the same voltage as that of the v ss pin even when a/d converter or d/a converter is not used. 4.2.18 reset this is a low-level active system reset input pin. 4.2.19 x1 and x2 crystal resonator connect pins for main system clock oscillation. for external clock supply, input it to x1 and its inverted signal to x2. 4.2.20 xt1 and xt2 crystal resonator connect pins for subsystem clock oscillation. for external clock supply, input it to xt1 and its inverted signal to xt2. 95 chapter 4 pin function ( m pd78078y subseries) 4.2.21 v dd positive power supply pin 4.2.22 v ss ground potential pin 4.2.23 v pp ( m pd78p078y only) high-voltage apply pin for prom programming mode setting and program write/verify. connect directly to v ss in normal operating mode. 4.2.24 ic (mask rom version only) the ic (internally connected) pin is provided to set the test mode to check the m pd78078y at delivery. connect it directly to the v ss with the shortest possible wire in the normal operating mode. when a voltage difference is produced between the ic pin and v ss pin because the wiring between those two pins is too long or an external noise is input to the ic pin, the user?s program may not run normally. ? connect ic pins to v ss pins directly . v ss ic as short as possible 96 chapter 4 pin function ( m pd78078y subseries) 4.3 input/output circuits and recommended connection of unused pins table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. refer to figure 4-1 for the configuration of the input/output circuit of each type. table 4-1. pin input/output circuit types (1/2) pin name input/output input/output recommended connection of unused pins circuit type p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-a input/output connect independently via a resistor p02/intp2 to v ss. p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11 input/output connect independently via a p20/si1 8-a resistor to v dd or v ss . p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0/sda0 10-a p26/so0/sb1/sda1 p27/sck0/scl p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40/ad0 to p47/ad7 5-e input/output connect independently via a resistor to v dd . 97 chapter 4 pin function ( m pd78078y subseries) table 4-1. pin input/output circuit types (2/2) pin name input/output input/output recommended connection of unused pins circuit type p50/a8 to p57/a15 5-a input/output connect independently via a resistor to v dd or v ss . p60 to p63 (mask rom version) 13-b input/output connect independently via a resistor p60 to p63 ( m pd78p078y) 13-d to v dd . p64/rd 5-a input/output connect independently via a resistor p65/wr to v dd or v ss . p66/wait p67/astb p70/si2/rxd 8-a p71/so2/txd 5-a p72/sck2/asck 8-a p80/a0 to p87/a7 5-a p90 to p93 (mask rom version) 13-b input/output connect independently via a resistor p90 to p93 ( m pd78p078y) 13-d to v dd . p94 to p96 5-a input/output connect independently via a resistor p100/ti5/to5 8-a to v dd or v ss . p101/ti6/to6 p102, p103 5-a p120/rtp0 to p127/rtp7 5-a p130/ano0, p131/ano1 12-a input/output connect independently via a resistor to v ss . reset 2 input ? xt2 16 ? open av ref0 ? connect to v ss . av ref1 connect to v dd . av dd av ss connect to v ss . ic (mask rom version) connect directly to v ss . v pp ( m pd78p078y) 98 chapter 4 pin function ( m pd78078y subseries) figure 4-1. list of pin input/output circuits (1/2) in pullup enable v dd p-ch in/out input enable output disable data v dd p-ch n-ch type 2 type 5-a schmitt-triggered input with hysteresis characteristics type 5-e type 11 type 10-a type 8-a pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch pullup enable v dd p-ch in/out open drain output disable data v dd p-ch n-ch pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch p-ch comparator n-ch input enable v ref (threshold voltage) + C 99 chapter 4 pin function ( m pd78078y subseries) figure 4-1. list of pin input/output circuits (2/2) type 12-a type 13-b type 13-d output disable v dd n-ch in/out rd medium breakdown input buffer data p-ch xt2 xt1 feedback cut-off p-ch type 16 output disable v dd v dd n-ch mask option in/out rd medium breakdown input buffer data p-ch pullup enable v dd p-ch in/out output disable data v dd p-ch n-ch input enable p-ch n-ch analog output voltage 100 [memo] 101 0000h data memory space general registers 32 x 8 bits internal rom 49152 x 8 bits bfffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal buffer ram 32 x 8 bits external memory 13312 x 8 bits reserved program memory space c000h bfffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 x 8 bits special function registers (sfrs) 256 x 8 bits internal expansion ram 1024 x 8 bits f400h f3ffh reserved fb00h faffh chapter 5 cpu architecture 5.1 memory spaces the m pd78078 and 78078y subseries allow access to a memory space of 64 kbytes. figures 5-1 to 5-3 shows memory maps. figure 5-1. memory map ( m pd78076, 78076y) 102 chapter 5 cpu architecture 0000h data memory space general registers 32 x 8 bits internal rom 61440 x 8 bits efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal buffer ram 32 x 8 bits reserved note program memory space f000h efffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 x 8 bits special function registers (sfrs) 256 x 8 bits internal expansion ram 1024 x 8 bits f400h f3ffh reserved fb00h faffh reserved figure 5-2. memory map ( m pd78078, 78078y) note when internal rom size is 60 kbytes, the area f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the internal rom size to less than 56 kbytes by the internal memory size switching register. 103 chapter 5 cpu architecture 0000h data memory space general registers 32 x 8 bits internal prom 61440 x 8 bits efffh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h callf entry area callt table area vector table area program area program area internal buffer ram 32 x 8 bits reserved program memory space f000h efffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 x 8 bits special function registers (sfrs) 256 x 8 bits internal expansion ram 1024 x 8 bits f400h f3ffh reserved fb00h faffh reserved note figure 5-3. memory map ( m pd78p078, m pd78p078y) note when internal prom size is 60 kbytes, the area f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the internal rom size to less than 56 kbytes by the internal memory size switching register. 104 chapter 5 cpu architecture 5.1.1 internal program memory space the internal program memory space stores programs and table data. this is generally accessed by the program counter (pc). the m pd78078 and 78078y subseries have various size of internal roms or prom as shown below. table 5-1. internal rom capacities part number internal rom type capacity m pd78076, 78076y mask rom 49152 x 8 bits m pd78078, 78078y 61440 x 8 bits m pd78p078, 78p078y prom the internal program memory is divided into three areas: vector table area, callt instruction table area, and callf instruction table area. these areas are described on the next page. 105 chapter 5 cpu architecture (1) vector table area the 64-byte area 0000h to 003fh is reserved as a vector table area. the reset input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. of the 16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses. table 5-2. vector table vector table address interrupt request 0000h reset input 0004h intwdt 0006h intp0 0008h intp1 000ah intp2 000ch intp3 000eh intp4 0010h intp5 0012h intp6 0014h intcsi0 0016h intcsi1 0018h intser 001ah intsr/intcsi2 001ch intst 001eh inttm3 0020h inttm00 0022h inttm01 0024h inttm1 0026h inttm2 0028h intad 002ah inttm5 002ch inttm6 003eh brk (2) callt instruction table area the 64-byte area 0040h to 007fh can store the subroutine entry address of a 1-byte call instruction (callt). (3) callf instruction entry area the area 0800h to 0fffh can perform a direct subroutine call with a 2-byte call instruction (callf). 106 chapter 5 cpu architecture 5.1.2 internal data memory space the m pd78078 and 78078y subseries units incorporate the following rams. (1) internal high-speed ram this is a 1024 x 8-bit configuration in the area fb00h to feffh 4 banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area fee0h to feffh. the internal high-speed ram can also be used as a stack memory. (2) internal buffer ram internal buffer ram is allocated to the 32-byte area from fac0h to fadfh. internal buffer ram is used for storing transmit/receive data of serial interface channel 1 (3-wire serial i/o mode with automatic transmit/ receive function). when not used in the 3-wire serial i/o mode with automatic transmit/receive function, internal buffer ram can also be used as normal ram. (3) internal expansion ram internal expansion ram is allocated to the 1024-byte area from f400h to f7ffh. 5.1.3 special function register (sfr) area an on-chip peripheral hardware special function register (sfr) is allocated in the area ff00h to ffffh. (refer to table 5-3. special function register list of 5.2.3 special function register (sfr) ). caution do not access addresses where the sfr is not assigned. 5.1.4 external memory space the external memory space is accessible by setting the memory expansion mode register (mm). external memory space can store program, table data, etc. and allocate peripheral devices. 107 chapter 5 cpu architecture 0000h general registers 32 x 8 bits internal rom 49152 x 8 bits internal buffer ram 32 x 8 bits external memory 13312 x 8 bits reserved c000h bfffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 x 8 bits reserved fb00h faffh f400h f3ffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 x 8 bits internal expansion ram 1024 x 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing 5.1.5 data memory addressing addressing is a method to specify the instruction address to be executed next and the register and memory address to be manipulated when instructions are executed. the instruction address to be executed next is addressed by the program counter (pc) (for details, refer to 5.3 instruction address addressing ). for the addressing of the memory to be manipulated when instructions are executed, the m pd78078 and 78078y subseries are provided with various addressing modes for optimum addressing. special addressing methods are possible to meet the functions of the special function registers (sfrs) and general registers. the data memory space is the entire 64-kbyte space (0000h to ffffh). figures 5-4 to 5-6 show the data memory addressing modes. for details of addressing, refer to 5.4 operand address addressing . figure 5-4. data memory addressing ( m pd78076, 78076y) 108 chapter 5 cpu architecture 0000h general registers 32 x 8 bits internal rom 61440 x 8 bits internal buffer ram 32 x 8 bits reserved f000h efffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 x 8 bits reserved fb00h faffh f400h f3ffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 x 8 bits internal expansion ram 1024 x 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing reserved note figure 5-5. data memory addressing ( m pd78078, 78078y) note when internal rom size is 60 kbytes, the area f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the internal rom size to less than 56 kbytes by the internal memory size switching register (ims). 109 chapter 5 cpu architecture 0000h general registers 32 x 8 bits internal rom 61440 x 8 bits internal buffer ram 32 x 8 bits reserved f000h efffh f800h f7ffh fac0h fabfh fae0h fadfh fee0h fedfh ff00h feffh ffffh internal high-speed ram 1024 x 8 bits reserved fb00h faffh f400h f3ffh ff20h ff1fh fe20h fe1fh special function registers (sfrs) 256 x 8 bits internal expansion ram 1024 x 8 bits sfr addressing register addressing short direct addressing direct addressing register indirect addressing based addressing based indexed addressing reserved note figure 5-6. data memory addressing ( m pd78p078, 78p078y) note when internal prom size is 60 kbytes, the area f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the internal rom size to less than 56 kbytes by the internal memory size switching register (ims). 110 chapter 5 cpu architecture 70 ie psw z rbs1 ac rbs0 0 isp cy pc 15 0 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 5.2 processor registers the m pd78078 and 78078y subseries units incorporate the following processor registers. 5.2.1 control registers the control registers control the program sequence, statuses, and stack memory. the control registers consist of a program counter (pc), a program status word (psw), and a stack pointer (sp). (1) program counter (pc) the program counter is a 16-bit register which holds the address information of the next program to be executed. in normal operation, the pc is automatically incremented according to the number of bytes of the instruction to be fetched. when a branch instruction is executed, immediate data and register contents are set. reset input sets the reset vector table values at addresses 0000h and 0001h to the program counter. figure 5-7. program counter configuration (2) program status word (psw) the program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. program status word contents are automatically stacked upon interrupt request generation or push psw instruction execution and are automatically reset upon execution of the retb, reti and pop psw instructions. reset input sets the psw to 02h. figure 5-8. program status word configuration 111 chapter 5 cpu architecture (a) interrupt enable flag (ie) this flag controls the interrupt request acknowledge operations of the cpu. when ie = 0, the ie is set to interrupt disabled (di) status. all interrupts except non-maskable interrupt are disabled. when ie = 1, the ie is set to interrupt enabled (ei) status and interrupt request acknowledge is controlled with an in-service priority flag (isp), an interrupt mask flag for various interrupt sources, and a priority specification flag. the ie is reset to (0) upon di instruction execution or interrupt request acknowledgement and is set to (1) upon ei instruction execution. (b) zero flag (z) when the operation result is zero, this flag is set (1). it is reset (0) in all other cases. (c) register bank select flags (rbs0 and rbs1) these are 2-bit flags to select one of the four register banks. in these flags, the 2-bit information which indicates the register bank selected by sel rbn instruction execution is stored. (d) auxiliary carry flag (ac) if the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). it is reset (0) in all other cases. (e) in-service priority flag (isp) this flag manages the priority of acknowledgeable maskable vectored interrupts. when isp = 0, acknowledgment of the vectored interrupt request specified to low-order priority with the priority specify flag registers (pr0l, pr0h, and pr1l) (refer to 22.3 (3) priority specify flag registers (pr0l, pr0h, and pr1l) ) is disabled. whether an actual interrupt request is acknowledged or not is controlled with the interrupt enable flag (ie). (f) carry flag (cy) this flag stores overflow and underflow upon add/subtract instruction execution. it stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. 112 chapter 5 cpu architecture sp 15 0 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 (3) stack pointer (sp) this is a 16-bit register to hold the start address of the memory stack area. only the internal high-speed ram area can be set as the stack area. figure 5-9. stack pointer configuration the sp is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory. each stack operation saves/resets data as shown in figures 5-10 and 5-11. caution since reset input makes sp contents indeterminate, be sure to initialize the sp before instruction execution. figure 5-10. data to be saved to stack memory figure 5-11. data to be reset from stack memory interrupt and brk instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp _ 2 sp _ 2 register pair upper call, callf, and callt instruction push rp instruction sp _ 1 sp sp sp _ 2 sp _ 2 sp _ 1 sp pc7 to pc0 sp _ 3 sp _ 2 sp _ 1 sp sp sp _ 3 reti and retb instruction psw pc15 to pc8 pc15 to pc8 pc7 to pc0 register pair lower sp sp + 2 sp register pair upper ret instruction pop rp instruction sp + 1 pc7 to pc0 sp sp + 2 sp sp + 1 sp + 2 sp sp + 1 sp sp + 3 113 chapter 5 cpu architecture 5.2.2 general registers a general register is mapped at particular addresses (fee0h to feffh) of the data memory. it consists of 4 banks, each bank consisting of eight 8-bit registers (x, a, c, b, e, d, l, and h). each register can also be used as an 8-bit register. two 8-bit registers can be used in pairs as a 16-bit register (ax, bc, de, and hl). they can be described in terms of function names (x, a, c, b, e, d, l, h, ax, bc, de, and hl) and absolute names (r0 to r7 and rp0 to rp3). register banks to be used for instruction execution are set with the cpu control instruction (sel rbn). because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption for each bank. figure 5-12. general register configuration (a) absolute name (b) function name bank0 bank1 bank2 bank3 feffh fef8h fee0h rp3 rp2 rp1 rp0 r7 15 0 7 0 r6 r5 r4 r3 r2 r1 r0 16-bit processing 8-bit processing fee0h fee8h bank0 bank1 bank2 bank3 feffh fef8h fee0h hl de bc ax h 15 0 7 0 l d e b c a x 16-bit processing 8-bit processing fef0h fee8h 114 chapter 5 cpu architecture 5.2.3 special function register (sfr) unlike a general register, each special function register has special functions. it is allocated in the ff00h to ffffh area. the special function registers can be manipulated in a similar way as the general registers, by using operation, transfer, or bit-manipulate instructions. the special function regsters are read from and written to in specified manipulation bit units (1, 8, and/or 16) depending on the register type. each manipulation bit unit can be specified as follows. ? 1-bit manipulation describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit). this manipulation can also be specified with an address. ? 8-bit manipulation describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr). this manipulation can also be specified with an address. ? 16-bit manipulation describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp). when addressing an address, describe an even address. table 5-3 gives a list of special function registers. the meaning of items in the table is as follows. ? symbol this column shows the addresses of the special function registers. they have been defined as reserved words in the ra78k/0 and as the header file, sfrbit.h, in the cc78k/0. they can be described as instruction operands when the ra78k/0, id78k0-ns, id78k0, and sm78k/0 are used. ? r/w this column shows whether the corresponding special function register can be read or written. r/w : both reading and writing are enabled. r : the value in the register can read out. a write to this register is ignored. w : a value can be written to the register. reading values from the register is impossible. ? manipulation the register can be manipulated in bit units marked with a check ( ? ) mark. the register cannot be manipulated in bit units marked with ?. ? after reset the register is set to the value immediately after the reset signal is input. 115 chapter 5 cpu architecture address special function register (sfr) name symbol r/w after reset ff00h port0 p0 r/w ?? ? 00h ff01h port1 p1 ?? ? ff02h port2 p2 ?? ? ff03h port3 p3 ?? ? ff04h port4 p4 ?? ? undefined ff05h port5 p5 ?? ? ff06h port6 p6 ?? ? ff07h port7 p7 ?? ? 00h ff08h port8 p8 ?? ? ff09h port9 p9 ?? ? ff0ah port10 p10 ?? ? ff0ch port12 p12 ?? ? ff0dh port13 p13 ?? ? ff10h capture/compare register 00 cr00 ? ? ? undefined ff11h ff12h capture/compare register 01 cr01 ? ? ? ff13h ff14h 16-bit timer register tm0 r ? ? ? 0000h ff15h ff16h compare register 10 cr10 r/w ? ? ? undefined ff17h compare register 20 cr20 ? ? ? ff18h 8-bit timer register 1 tms tm1 r ? ?? 00h ff19h 8-bit timer register 2 tm2 ? ? ff1ah serial i/o shift register 0 sio0 r/w ? ? ? undefined ff1bh serial i/o shift register 1 sio1 ? ? ? ff1fh a/d conversion result register adcr r ? ? ? ff20h port mode register 0 pm0 r/w ?? ? ffh ff21h port mode register 1 pm1 ?? ? ff22h port mode register 2 pm2 ?? ? ff23h port mode register 3 pm3 ?? ? ff25h port mode register 5 pm5 ?? ? ff26h port mode register 6 pm6 ?? ? ff27h port mode register 7 pm7 ?? ? ff28h port mode register 8 pm8 ?? ? ff29h port mode register 9 pm9 ?? ? ff2ah port mode register 10 pm10 ?? ? ff2ch port mode register 12 pm12 ?? ? ff2dh port mode register 13 pm13 ?? ? table 5-3. special function register list (1/3) manipulation 8 bits 1 bit 16 bits 116 chapter 5 cpu architecture table 5-3. special function register list (2/3) 8 bits 1 bit 16 bits address special function register (sfr) name symbol r/w after reset ff30h real-time output buffer register l rtbl r/w ? ? 00h ff31h real-time output buffer register h rtbh ? ? ? ff34h real-time output port mode register rtpm ?? ? ff36h real-time output port control register rtpc ?? ? ff38h correction address register 0 corad0 ? ? ? ff39h ff3ah correction address register 1 corad1 ? ? ? ff3bh ff3fh external bus type selection register ebts ? ? ? ff40h timer clock select register 0 tcl0 ?? ? ff41h timer clock select register 1 tcl1 ? ? ? ff42h timer clock select register 2 tcl2 ? ? ? ff43h timer clock select register 3 tcl3 ? ? ? 88h ff47h sampling clock select register scs ? ? ? 00h ff48h 16-bit timer mode control register tmc0 ?? ? ff49h 8-bit timer mode control register 1 tmc1 ?? ? ff4ah watch timer mode control register tmc2 ?? ? ff4ch capture/compare control register 0 crc0 ?? ? 04h ff4eh 16-bit timer output control register toc0 ?? ? 00h ff4fh 8-bit timer output control register toc1 ?? ? ff50h compare register 50 cr50 ? ? ? ff51h 8-bit timer register 5 tm5 r ? ? ? ff52h timer clock selection register 5 tcl5 r/w ? ? ? ff53h 8-bit timer mode control register 5 tmc5 ?? ? ff54h compare register 60 cr60 ? ? ? ff55h 8-bit timer register 6 tm6 r ? ? ? ff56h timer clock selection register 6 tcl6 r/w ? ? ? ff57h 8-bit timer mode control register 6 tmc6 ?? ? ff60h serial operating mode register 0 csim0 ?? ? ff61h serial bus interface control register sbic ?? ? ff62h slave address register sva ? ? ? undefined ff63h interrupt timing specify register sint ?? ? 00h ff68h serial operating mode register 1 csim1 ?? ? ff69h automatic data transmit/receive control register adtc ?? ? ff6ah automatic data transmit/receive address pointer adtp ? ? ? ff6bh automatic data transmit/receive interval specify register adti ?? ? ff70h asynchronous serial interface mode register asim ?? ? ff71h asynchronous serial interface status register asis r ? ? ? ff72h serial operating mode register 2 csim2 r/w ?? ? ff73h baud rate generator control register brgc ? ? ? manipulation 117 chapter 5 cpu architecture address special function register (sfr) name symbol r/w after reset ff74h transmit shift register txs sio2 w ? ? ffh receive buffer register rxb r ff80h a/d converter mode register adm r/w ?? ? 01h ff84h a/d converter input select register adis ? ? ? 00h ff8ah correction control register corcn ?? ? ff90h d/a conversion value set register 0 dacs0 ? ? ? ff91h d/a conversion value set register 1 dacs1 ? ? ? ff98h d/a converter mode registe dam ?? ? ffd0h to external access area note 1 ?? ? undefined ffdfh ffe0h interrupt request flag register 0l if0 if0l ??? 00h ffe1h interrupt request flag register 0h if0h ?? ffe2h interrupt request flag register 1l if1l ?? ? ffe4h interrupt mask flag register 0l mk0 mk0l ??? ffh ffe5h interrupt mask flag register 0h mk0h ?? ffe6h interrupt mask flag register 1l mk1l ?? ? ffe8h priority order specify flag register 0l pr0 pr0l ??? ffe9h priority order specify flag register 0h pr0h ?? ffeah priority order specify flag register 1l pr1l ?? ? ffech external interrupt mode register 0 intm0 ? ? ? 00h ffedh external interrupt mode register 1 intm1 ? ? ? fff0h internal memory size switching register ims ? ? ? note 2 fff2h oscillation mode selection register osms w ? ? 00h fff3h pull-up resistor option register h puoh r/w ?? ? fff4h internal expansion ram size ixs w ? ? ? 0ah note 3 switching register fff6h key return mode register krm r/w ?? ? 02h fff7h pull-up resistor option register l puol ?? ? 00h fff8h memory expansion mode register mm ?? ? 10h fff9h watchdog timer mode register wdtm ?? ? 00h fffah oscillation stabilization time select register osts ? ? ? 04h fffbh processor clock control register pcc ?? ? table 5-3. special function register list (3/3) 8 bits 1 bit 16 bits notes 1. the external access area cannot be accessed in sfr addressing. access the area through direct addressing. 2. the value after reset depends on products. m pd78076,78076y: cch, m pd78078, 78078y: cfh, m pd78p078, 78p078y: cfh when a mask rom version is used, do not set to ims any value other than that determined at reset, unless external device expansion function is used with the m pd78078 or 78078y. 3. when a mask rom version is used, do not set to ixs any value other than that determined at reset. manipulation 118 chapter 5 cpu architecture 15 0 pc + 15 0 876 s 15 0 pc a jdisp8 when s = 0, all bits of a are 0. when s = 1, all bits of a are 1. pc indicates the start address of the instruction after the br instruction. ... 5.3 instruction address addressing an instruction address is determined by program counter (pc) contents. the pc contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. however, when a branch instruction is executed, the branch destination information is set to the pc and branched by the following addressing. (for details of instructions, refer to 78k/0 users manual instructions (u12326e) . 5.3.1 relative addressing [function] the value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (pc) and branched. the displacement value is treated as signed twos complement data (C128 to +127) and bit 7 becomes a sign bit. in other words, the range of branch in relative addressing is between C128 and +127 of the start address of the following instruction. this function is carried out when the br $addr16 instruction or a conditional branch instruction is executed. [illustration] 119 chapter 5 cpu architecture 5.3.2 immediate addressing [function] immediate data in the instruction word is transferred to the program counter (pc) and branched. this function is carried out when the call !addr16 or br !addr16 or callf !addr11 instruction is executed. call !addr16 and br !addr16 instructions can branch to all the memory space. callf !addr11 instruction branches to the area from 0800h to 0fffh. [illustration] in the case of call !addr16 and br !addr16 instructions in the case of callf !addr11 instruction 15 0 pc 87 70 call or br low addr. high addr. 15 0 pc 87 70 fa 10? 11 10 00001 643 callf fa 7? 120 chapter 5 cpu architecture 5.3.3 table indirect addressing [function] table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (pc) and branched. table indirect addressing is carried out when the callt [addr5] instruction is executed. this instruction can refer to the address stored in the memory table 40h to 7fh and branch to all the memory space. [illustration] 15 1 15 0 pc 70 low addr. high addr. memory (table) effective address+1 effective address 01 00000000 87 87 65 0 0 1 11 765 10 ta 4? operation code 121 chapter 5 cpu architecture 5.3.4 register addressing [function] register pair (ax) contents to be specified with an instruction word are transferred to the program counter (pc) and branched. this function is carried out when the br ax instruction is executed. [illustration] 70 rp 07 ax 15 0 pc 87 122 chapter 5 cpu architecture 5.4 operand address addressing the following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 implied addressing [function] the register which functions as an accumulator (a and ax) in the general register is automatically (implicitly) addressed. of the m pd78078 and 78078y subseries instruction words, the following instructions employ implied addressing. instruction register to be specified by implied addressing mulu a register for multiplicand and ax register for product storage divuw ax register for dividend and quotient storage adjba/adjbs a register for storage of numeric values which become decimal correction targets ror4/rol4 a register for storage of digit data which undergoes digit rotation [operand format] because implied addressing can be automatically employed with an instruction, no particular operand format is necessary. [description example] in the case of mulu x with an 8-bit x 8-bit multiply instruction, the product of a register and x register is stored in ax. in this example, the a and ax registers are specified by implied addressing. 123 chapter 5 cpu architecture 01100010 register specify code operation code 5.4.2 register addressing [function] the general register is accessed as an operand. the general register to be accessed is specified with register bank select flags (rbs0 and rbs1) and register specify code (rn, rpn) in the instruction code. register addressing is carried out when an instruction with the following operand format is executed. when an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code. [operand format] identifier description r x, a, c, b, e, d, l, h rp ax, bc, de, hl r and rp can be described with function names (x, a, c, b, e, d, l, h, ax, bc, de and hl) as well as absolute names (r0 to r7 and rp0 to rp3). [description example] mov a, c; when selecting c register as r incw de; when selecting de register pair as rp 10000100 register specify code operation code 124 chapter 5 cpu architecture 5.4.3 direct addressing [function] the memory indicated by immediate data in an instruction word is directly addressed. [operand format] identifier description addr16 label or 16-bit immediate data [description example] mov a, !0fe00h; when setting !addr16 to fe00h operation code 10001110 op code 00000000 00h 11111110 feh [illustration] 70 op code addr16 (higher) memory addr16 (lower) 125 chapter 5 cpu architecture 5.4.4 short direct addressing [function] the memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. the fixed space to which this addressing is applied to is the 256-byte space, from fe20h to ff1fh. an internal high-speed ram and a special function register (sfr) are mapped at fe20h to feffh and ff00h to ff1fh, respectively. the sfr area where short direct addressing is applied (ff00h to ff1fh) is a part of the sfr area. in this area, ports which are frequently accessed in a program, a compare register of the timer/event counter, and a capture register of the timer/event counter are mapped and these sfrs can be manipulated with a small number of bytes and clocks. when 8-bit immediate data is at 20h to ffh, bit 8 of an effective address is set to 0. when it is at 00h to 1fh, bit 8 is set to 1. refer to [illustration] below. [operand format] identifier description saddr label of fe20h to ff1fh immediate data saddrp label of fe20h to ff1fh immediate data (even address only) [description example] mov 0fe30h, #50h; when setting saddr to fe30h and immediate data to 50h operation code 00010001 op code 00110000 30h (saddr-offset) 01010000 50h (immediate data) [illustration] when 8-bit immediate data is 20h to ffh, a = 0 when 8-bit immediate data is 00h to 1fh, a = 1 15 0 short direct memory effective address 1 111111 87 0 7 op code saddr-offset a 126 chapter 5 cpu architecture 15 0 sfr effective address 1 111111 87 0 7 op code sfr-offset 1 5.4.5 special function register (sfr) addressing [function] the memory-mapped special function register (sfr) is addressed with 8-bit immediate data in an instruction word. this addressing is applied to the 240-byte spaces ff00h to ffcfh and ffe0h to ffffh. however, the sfr mapped at ff00h to ff1fh can be accessed with short direct addressing. [operand format] identifier description sfr special function register name sfrp 16-bit manipulatable special function register name (even address only) [description example] mov pm0, a; when selecting pm0 (ff20h) as sfr operation code 11110110 op code 00100000 20h (sfr-offset) [illustration] 127 chapter 5 cpu architecture 5.4.6 register indirect addressing [function] the memory is addressed with the contents of the register pair specified as an operand. the register pair to be accessed is specified with the register bank select flag (rbs0 and rbs1) and the register pair specify code in the instruction code. this addressing can be carried out for all the memory spaces. [operand format] identifier description [de], [hl] [description example] mov a, [de]; when selecting [de] as register pair operation code 10000101 [illustration] 16 0 8 d 7 e memory the contents of addressed memory are transferred memory address specified by register pair de 0 7 7 0 a de 128 chapter 5 cpu architecture 5.4.7 based addressing [function] 8-bit immediate data is added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. the hl register pair to be accessed is in the register bank specified with the register bank select flags (rbs0 and rbs1). addition is performed by expanding the offset data as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + byte] [description example] mov a, [hl + 10h]; when setting byte to 10h operation code 10101110 00010000 129 chapter 5 cpu architecture 5.4.8 based indexed addressing [function] the b or c register contents specified in an instruction are added to the contents of the base register, that is, the hl register pair, and the sum is used to address the memory. the hl, b, and c registers to be accessed are registers in the register bank specified with the register bank select flag (rbs0 and rbs1). addition is performed by expanding the contents of the b or c register as a positive number to 16 bits. a carry from the 16th bit is ignored. this addressing can be carried out for all the memory spaces. [operand format] identifier description [hl + b], [hl + c] [description example] in the case of mov a, [hl + b] operation code 10101011 5.4.9 stack addressing [function] the stack area is indirectly addressed with the stack pointer (sp) contents. this addressing method is automatically employed when the push, pop, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. stack addressing enables to address the internal high-speed ram area only. [description example] in the case of push de operation code 10110101 130 [memo] 131 chapter 6 port functions 6.1 port functions the m pd78078 and 78078y subseries units incorporate two input ports and eighty-six input/output ports. figure 6-1 shows the port configuration. every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. besides port functions, the ports can also serve as on-chip hardware input/output pins. figure 6-1. port types port 6 port 0 port 8 port 9 port 7 8 port 1 port 2 p00 p60 p67 p70 p72 p80 p103 p10 p07 p17 p20 p27 port 13 port 3 port 4 port 5 p87 p90 p96 p100 p120 p127 p130 port 10 port 12 p131 p30 p37 p40 to p47 p50 p57 132 chapter 6 port functions pin name function alternate function p00 input only intp0/ti00 p01 intp1/ti01 p02 input/output mode can be specified bit- intp2 p03 port 0. wise. intp3 p04 8-bit input/output port. if used as an input port, an on-chip pull- intp4 p05 up resistor can be connected by software. intp5 p06 intp6 p07 input only xt1 port 1. 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p20 si1 p21 so1 p22 port 2. sck1 p23 8-bit input/output port. stb p24 input/output mode can be specified bit-wise. busy p25 if used as an input port, an on-chip pull-up resistor can be connected by software. si0/sb0 p26 so0/sb1 p27 sck0 p30 to0 p31 to1 p32 port 3. to2 p33 8-bit input/output port. ti1 p34 input/output mode can be specified bit-wise. ti2 p35 if used as an input port, an on-chip pull-up resistor can be connected by software. pcl p36 buz p37 port 4. 8-bit input/output port. p40 to p47 input/output mode can be specified bit-wise. ad0 to ad7 if used as an input port, an on-chip pull-up resistor can be connected by software. test input flag (krif) is set to 1 by falling edge detection. port 5. 8-bit input/output port. p50 to p57 leds can be driven directly. a8 to a15 input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p10 to p17 ani0 to ani7 table 6-1. port functions ( m pd78078 subseries) (1/2) 133 chapter 6 port functions p120 to p127 rtp0 to rtp7 p130, p131 ano0, ano1 p100 ti5/to5 p101 ti6/to6 p102, 103 p70 si2/rxd p71 so2/txd p72 sck2/asck table 6-1. port functions ( m pd78078 subseries) (2/2) pin name function alternate function p60 n-ch open drain input/output port. p61 on-chip pull-up resistor can be specified by p62 port 6. mask option. (mask rom version only). p63 8-bit input/output port. leds can be driven directly. p64 input/output mode can be specified if used as an input port, an on-chip pull- rd p65 bit-wise. up resistor can be connected by software. wr p66 wait p67 astb port 7. 3-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 8. 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p90 n-ch open-drain input/output port. p91 on-chip pull-up resistor can be specified by p92 port 9. mask option. (mask rom version only). p93 7-bit input/output port. leds can be driven directly. p94 input/output mode can be specified bit-wise. if used as an input port, an on-chip pull- p95 up resistor can be connected by software. p96 port 10. 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 12. 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 13. 2-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p80 to p87 a0 to a7 134 chapter 6 port functions table 6-2. port functions ( m pd78078y subseries) (1/2) pin name function alternate function p00 input only intp0/ti00 p01 intp1/ti01 p02 input/output mode can be specified bit- intp2 p03 port 0. wise. intp3 p04 8-bit input/output port. if used as an input port, an on-chip pull- intp4 p05 up resistor can be connected by software. intp5 p06 intp6 p07 input only xt1 port 1. p10 to p17 8-bit input/output port. ani0 to ani7 input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p20 si1 p21 so1 p22 port 2. sck1 p23 8-bit input/output port. stb p24 input/output mode can be specified bit-wise. busy p25 if used as an input port, an on-chip pull-up resistor can be connected by software. si0/sb0/sda0 p26 so0/sb1/sda1 p27 sck0/scl p30 to0 p31 to1 p32 port 3. to2 p33 8-bit input/output port. ti1 p34 input/output mode can be specified bit-wise. ti2 p35 if used as an input port, an on-chip pull-up resistor can be connected by software. pcl p36 buz p37 port 4. 8-bit input/output port. p40 to p47 input/output mode can be specified 8-bit-wise. ad0 to ad7 if used as an input port, an on-chip pull-up resistor can be connected by software. test input flag (krif) is set to 1 by falling edge detection. port 5. 8-bit input/output port. p50 to p57 leds can be driven directly. a8 to a15 input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. 135 chapter 6 port functions table 6-2. port functions ( m pd78078y subseries) (2/2) pin name function alternate function p60 n-ch open drain input/output port. p61 on-chip pull-up resistor can be specified by p62 port 6. mask option. (mask rom version only). p63 8-bit input/output port. leds can be driven directly. p64 input/output mode can be specified if used as an input port, an on-chip pull- rd p65 bit-wise. up resistor can be connected by software. wr p66 wait p67 astb port 7. 3-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 8. 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p90 n-ch open drain input/output port. p91 on-chip pull-up resistor can be specified by p92 port 9. mask option. (mask rom version only). p93 7-bit input/output port. leds can be driven directly. p94 input/output mode can be specified bit-wise. if used as an input port, an on-chip pull- p95 up resistor can be connected by software. p96 port 10. 4-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 12. 8-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. port 13. 2-bit input/output port. input/output mode can be specified bit-wise. if used as an input port, an on-chip pull-up resistor can be connected by software. p100 ti5/to5 p101 ti6/to6 p102, 103 p120 to p127 rtp0 to rtp7 p130, p131 ano0, ano1 p70 si2/rxd p71 so2/txd p72 sck2/asck p80 to p87 a0 to a7 136 chapter 6 port functions 6.2 port configuration a port consists of the following hardware: table 6-3. port configuration item configuration control register port mode register (pmm: m = 0 to 3, 5 to 10, 12, 13) pull-up resistor option register (puoh, puol) memory expansion mode register (mm) note key return mode register (krm) port total: 88 ports (2 inputs, 86 inputs/outputs) pull-up resistor ? mask rom versions..... total: 86 pins (software-specifiable for 78 pins and mask option for 8 pins) ? m pd78p078 (or 78p078y) ..... total: 78 pins note mm specifies port 4 input/output. 6.2.1 port 0 port 0 is an 8-bit input/output port with output latch. p01 to p06 pins can specify the input mode/output mode in 1-bit units with the port mode register 0 (pm0). p00 and p07 pins are input-only ports. when p01 to p06 pins are used as input ports, an on-chip pull-up resistor can be used in 6-bit units with a pull-up resistor option register l (puol). dual-functions include external interrupt request input, external count clock input to the timer and crystal connection for subsystem clock oscillation. reset input sets port 0 to input mode. figures 6-2 and 6-3 show block diagrams of port 0. caution because port 0 also serves for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. thus, when the output mode is used, set the interrupt mask flag to 1. 137 chapter 6 port functions figure 6-2. block diagram of p00 and p07 figure 6-3. block diagram of p01 to p06 puo : pull-up resistor option register pm : port mode register rd : port 0 read signal wr : port 0 write signal p00/intp0/ti00, p07/xt1 rd internal bus p-ch wr pm wr port rd wr puo v dd p01/intp1/ti01, p02/intp2 to p06/intp6 selector puo0 output latch (p01 to p06) pm01 to pm06 internal bus 138 chapter 6 port functions 6.2.2 port 1 port 1 is an 8-bit input/output port with output latch. it can specify the input mode/output mode in 1-bit units with a port mode register 1 (pm1). when p10 to p17 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register l (puol). dual-functions include an a/d converter analog input. reset input sets port 1 to input mode. figure 6-4 shows a block diagram of port 1. caution an on-chip pull-up resistor cannot be used for pins used as a/d converter analog input. figure 6-4. block diagram of p10 to p17 puo : pull-up resistor option register pm : port mode register rd : port 1 read signal wr : port 1 write signal p-ch wr pm wr port rd wr puo v dd p10/ani0 to p17/ani7 selector puo1 output latch (p10 to p17) pm10 to pm17 internal bus 139 chapter 6 port functions p-ch wr pm wr port rd wr puo v dd selector puo2 output latch (p20, p21, p23 to p26) pm20, pm21 pm23 to pm26 internal bus dual function p20/si1, p21/so1, p23/stb, p24/busy, p25/si0/sb0, p26/so0/sb1 6.2.3 port 2 ( m pd78078 subseries) port 2 is an 8-bit input/output port with output latch. p20 to p27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (pm2). when p20 to p27 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register l (puol). dual-functions include serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. reset input sets port 2 to input mode. figures 6-5 and 6-6 show a block diagram of port 2. cautions 1. when used as a serial interface, set the input/output and output latch according to its functions. for the setting method, refer to figure 17-4. serial operating mode register 0 format and figure 19-3. serial operating mode register 1 format. 2. when reading the pin state in sbi mode, set pm2n bit of pm2 to 1 (n = 5, 6) (refer to the description of (11) sbi mode precautions (e) in 17.4.3 sbi mode operation). figure 6-5. block diagram of p20, p21, p23 to p26 puo : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal 140 chapter 6 port functions p-ch wr pm wr port rd wr puo v dd selector puo2 output latch (p20, p21, p23 to p26) pm20, pm21 pm23 to pm26 internal bus dual function p20/si1, p21/so1, p23/stb, p24/busy, p25/si0/sb0/sda0, p26/so0/sb1/sda1 figure 6-6. block diagram of p22 and p27 puo : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal 141 chapter 6 port functions p20/si1, p21/so1, p23/stb, p24/busy, p25/si0/sb0/sda0, p26/so0/sb1/sda1 p-ch wr pm wr port rd wr puo v dd selector puo2 output latch (p20, p21, p23 to p26) pm20, pm21 pm23 to pm26 internal bus dual function 6.2.4 port 2 ( m pd78078y subseries) port 2 is an 8-bit input/output port with output latch. p20 to p27 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (pm2). when p20 to p27 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register l (puol). dual-functions include serial interface data input/output, clock input/output, automatic transmit/receive busy input, and strobe output. reset input sets port 2 to input mode. figures 6-7 and 6-8 show a block diagram of port 2. caution when used as a serial interface, set the input/output and output latch according to its functions. for the setting method, refer to figure 18-4. serial operating mode register 0 format and figure 19-3. serial operating mode register 1 format. figure 6-7. block diagram of p20, p21, p23 to p26 puo : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal 142 chapter 6 port functions p-ch wr pm wr port rd wr puo v dd selector puo2 output latch (p22, p27) pm22, pm27 internal bus dual function p22/sck1, p27/sck0/scl figure 6-8. block diagram of p22 and p27 puo : pull-up resistor option register pm : port mode register rd : port 2 read signal wr : port 2 write signal 143 chapter 6 port functions p-ch wr pm wr port rd wr puo v dd selector puo3 output latch (p30 to p37) pm30 to pm37 internal bus dual function p30/to0 to p32/to2, p33/ti1, p34/ti2, p35/pcl, p36/buz, p37 6.2.5 port 3 port 3 is an 8-bit input/output port with output latch. p30 to p37 pins can specify the input mode/output mode in 1-bit units with the port mode register 3 (pm3). when p30 to p37 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register l (puol). dual-functions include timer input/output, clock output and buzzer output. reset input sets port 3 to input mode. figure 6-9 shows a block diagram of port 3. figure 6-9. block diagram of p30 to p37 puo : pull-up resistor option register pm : port mode register rd : port 3 read signal wr : port 3 write signal 144 chapter 6 port functions 6.2.6 port 4 port 4 is an 8-bit input/output port with output latch. p40 to p47 pins can specify the input mode/output mode in 8-bit units with the memory expansion mode register (mm). when p40 to p47 pins are used as input ports, an on- chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register l (puol). the test input flag (krif) can be set to 1 by detecting falling edges. dual-functions include address/data bus function in external memory expansion mode. reset input sets port 4 to input mode. figures 6-10 and 6-11 show a block diagram of port 4 and block diagram of falling edge detection circuit, respectively. figure 6-10. block diagram of p40 to p47 puo : pull-up resistor option register mm : memory expansion mode register rd : port 4 read signal wr : port 4 write signal figure 6-11. block diagram of falling edge detection circuit p40 p41 p42 p43 p44 p45 p46 p47 falling edge detection circuit krmk krif set signal standby release signal p-ch wr mm wr port rd wr puo v dd selector puo4 output latch (p40 to p47) mm internal bus p40/ad0 to p47/ad7 145 chapter 6 port functions 6.2.7 port 5 port 5 is an 8-bit input/output port with output latch. p50 to p57 pins can specify the input mode/output mode in 1-bit units with the port mode register 5 (pm5). when p50 to p57 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register l (puol). port 5 can drive leds directly. dual-functions include address bus function in external memory expansion mode. reset input sets port 5 to input mode. figure 6-12 shows a block diagram of port 5. figure 6-12. block diagram of p50 to p57 puo : pull-up resistor option register pm : port mode register rd : port 5 read signal wr : port 5 write signal p-ch wr pm wr port rd wr puo v dd selector puo5 output latch (p50 to p57) pm50 to pm57 internal bus p50/a8 to p57/a15 146 chapter 6 port functions 6.2.8 port 6 port 6 is an 8-bit input/output port with output latch. p60 to p67 pins can specify the input mode/output mode in 1-bit units with the port mode register 6 (pm6). this port has pull-up resistor options as shown below. however, the option specification method differs depending on the port pin and the device version. table 6-4. pull-up resistor options for port 6 higher 4 bits (p64 to p67) lower 4 bits (p60 to p63) mask rom version internal pull-up resistors can be specified internal mask-option pull-up resistors can be by setting puo6 in 4-bit units. specified bitwise. prom version no pull-up resistor options puo6 : bit 6 of the pull-up resistor option register l (puol) pins p60 to p63 can drive leds directly. dual-functions include the control signal output function in external memory expansion mode. reset input sets port 6 to input mode. figures 6-13 and 6-14 show block diagrams of port 6. cautions 1. when external wait is not used in external memory expansion mode, p66 can be used as an input/output port. 2. when the low level is input to the p60 to p63 pins, the leakage current that flows through each of these pins depends on the following conditions: [mask rom version] ? when a pull-up resistor is connected, C3 m a (max.) ? when a pull-up resistor is not connected, C200 m a (max.) ........ for 1.5 clock cycles during which a read instruction is executed to port 6 (p6) or port mode register 6 (pm6) (it is assumed that no wait cycles are inserted.) C3 m a (max.) ............ during periods other than the above [prom version] ? when a pull-up resistor is not connected, C200 m a (max.) ........ for 1.5 clock cycles during which a read instruction is executed to port 6 (p6) or port mode register 6 (pm6) (it is assumed that no wait cycles are inserted.) C3 m a (max.) ............ during periods other than the above 147 chapter 6 port functions figure 6-13. block diagram of p60 to p63 pm : port mode register rd : port 6 read signal wr : port 6 write signal figure 6-14. block diagram of p64 to p67 puo : pull-up resistor option register pm : port mode register rd : port 6 read signal wr : port 6 write signal wr pm wr port rd v dd selector output latch (p60 to p63) pm60 to pm63 internal bus p60 to p63 mask option resistor mask rom versions only. pd78p078 and 78p078y have no pull-up resistor. p-ch wr pm wr port rd wr puo v dd selector puo6 output latch (p64 to p67) pm64 to pm67 internal bus p64/rd, p65/wr, p66/wait, p67/astb 148 chapter 6 port functions 6.2.9 port 7 this is a 3-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with a port mode register 7 (pm7). when pins p70 to p72 are used as input port pins, an on-chip pull-up resistor can be connected in 3-bit units with a pull-up resistor option register l (puol). dual-functions include serial interface channel 2 data input/output and clock input/output. reset input sets the input mode. port 7 block diagrams are shown in figures 6-15 and 6-16. caution when used as a serial interface, set the input/output and output latch according to its functions. for the setting method, refer to table 20-2. serial interface channel 2 operating mode setting. figure 6-15. block diagram of p70 puo : pull-up resistor option register pm : port mode register rd : port 7 read signal wr : port 7 write signal p-ch wr pm wr port rd wr puo v dd selector puo7 output latch (p70) pm70 internal bus p70/si2/rxd 149 chapter 6 port functions p-ch wr pm wr port rd wr puo v dd selector puo7 output latch (p71, p72) pm71, pm72 internal bus dual function p71/so2/txd, p72/sck2/asck figure 6-16. block diagram of p71 and p72 puo : pull-up resistor option register pm : port mode register rd : port 7 read signal wr : port 7 write signal 150 chapter 6 port functions 6.2.10 port 8 port 8 is an 8-bit input/output port with output latch. p80 to p87 pins can specify the input mode/output mode in 1-bit units with the port mode register 8 (pm8). when pins p80 to p87 are used as input ports, an on-chip pull-up resistor can be connected to them in 8-bit units with a pull-up resistor option register h (puoh). dual-functions include the address bus function in external memory expansion mode. reset input sets port 8 to input mode. figure 6-17 shows block diagram of port 8. figure 6-17. block diagram of p80 to p87 puo : pull-up resistor option register pm : port mode register rd : port 8 read signal wr : port 8 write signal p-ch wr pm wr port rd wr puo v dd selector puo8 output latch (p80 to p87) pm80 to pm87 internal bus p80/a0 to p87/a7 151 chapter 6 port functions 6.2.11 port 9 port 9 is an 7-bit input/output port with output latch. p90 to p96 pins can specify the input mode/output mode in 1-bit units with the port mode register 9 (pm9). this port has pull-up resistor options as shown below. however, the option specification method differs depending on the port pin and the device version. table 6-5. pull-up resistor options for port 9 higher 3 bits (p94 to p97) lower 4 bits (p90 to p93) mask rom version internal pull-up resistors can be specified internal mask-option pull-up resistors can be by setting puo6 in 3-bit units. specified bitwise. prom version no pull-up resistor options puo9 : bit 1 of the pull-up resistor option register h (puoh) pins p90 to p93 can drive leds directly. dual-functions include the control signal output function in external memory expansion mode. reset input sets port 6 to input mode. figures 6-18 and 6-19 show block diagrams of port 9. caution when the low level is input to the p90 to p93 pins, the leakage current that flows through each of these pins depends on the following conditions: [mask rom version] ? when a pull-up resistor is connected, C3 m a (max.) ? when a pull-up resistor is not connected, C200 m a (max.) ........ for 1.5 clock cycles during which a read instruction is executed to port 9 (p9) or port mode register 9 (pm9) (it is assumed that no wait cycles are inserted.) C3 m a (max.) ............ during periods other than the above [prom version] ? when a pull-up resistor is not connected, C200 m a (max.) ........ for 1.5 clock cycles during which a read instruction is executed to port 9 (p9) or port mode register 9 (pm9) (it is assumed that no wait cycles are inserted.) C3 m a (max.) ............ during periods other than the above 152 chapter 6 port functions figure 6-18. block diagram of p90 to p93 pm : port mode register rd : port 9 read signal wr : port 9 write signal figure 6-19. block diagram of p94 to p96 puo : pull-up resistor option register pm : port mode register rd : port 9 read signal wr : port 9 write signal mask option resistor wr pm wr port rd v dd selector output latch (p90 to p93) pm90 to pm93 internal bus p90 to p93 mask rom versions only. pd78p078 and 78p078y have no pull-up resistor. p-ch wr pm wr port rd wr puo v dd selector puo9 output latch (p94 to p96) pm94 to pm96 internal bus p94 to p96 153 chapter 6 port functions p-ch wr pm wr port rd wr puo v dd selector puo10 output latch (p100, p101) pm100, pm101 internal bus dual-functions p100/ti5/to5, p101/ti6/to6 6.2.12 port 10 port 10 is a 4-bit input/output port with output latch. p100 to p103 pins can specify the input mode/output mode in 1-bit units with the port mode register 10 (pm10). when pins p100 to p103 are used as input ports, an on-chip pull-up resistor can be connected to them in 4-bit units with a pull-up resistor option register h (puoh). dual-functions include the timer input/output. reset input sets port 10 to input mode. figures 6-20 and 6-21 show block diagrams of port 10. figure 6-20. block diagram of p100 and p101 puo : pull-up resistor option register pm : port mode register rd : port 10 read signal wr : port 10 write signal 154 chapter 6 port functions figure 6-21. block diagram of p102 and p103 puo : pull-up resistor option register pm : port mode register rd : port 6 read signal wr : port 6 write signal p-ch wr pm wr port rd wr puo v dd selector puo10 output latch (p102, p103) pm102, pm103 internal bus p102, p103 155 chapter 6 port functions 6.2.13 port 12 this is an 8-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with the port mode register 12 (pm12). when pins p120 to p127 are used as input port pins, an on-chip pull-up resistor can be connected in 8-bit units with a pull-up resistor option register h (puoh). these pins are dual function pin and serve as real-time outputs. reset input sets the input mode. the port 12 block diagram is shown in figure 6-22. figure 6-22. block diagram of p120 to p127 puo : pull-up resistor option register pm : port mode register rd : port 12 read signal wr : port 12 write signal p-ch wr pm wr port rd wr puo v dd selector puo12 output latch (p120 to p127) pm120 to pm127 internal bus p120/rtp0 to p127/rtp7 156 chapter 6 port functions 6.2.14 port 13 this is a 2-bit input/output port with output latches. input mode/output mode can be specified in 1-bit units with the port mode register 13 (pm13). when pins p130 and p131 are used as input port pins, an on-chip pull-up resistor can be connected in 2-bit units with a pull-up resistor option register h (puoh). these pins are dual function pin and serve as d/a converter analog outputs. reset input sets the input mode. the port 13 block diagram is shown in figure 6-23. caution when only either one of the d/a converter channels is used with av ref1 < v dd , the other pins that are not used as analog outputs must be set as follows: ? set pm13x bit of the port mode register 13 (pm13) to 1 (input mode) and connect the pin to v ss . ? set pm13x bit of the port mode register 13 (pm13) to 0 (output mode) and the output latch to 0, to output low level from the pin. figure 6-23. block diagram of p130 and p131 puo : pull-up resistor option register pm : port mode register rd : port 13 read signal wr : port 13 write signal p-ch wr pm wr port rd wr puo v dd selector puo13 output latch (p130, p131) pm130, pm131 internal bus p130/ano0, p131/ano1 157 chapter 6 port functions 6.3 port function control registers the following four types of registers control the ports. ? port mode registers (pm0 to pm3, pm5 to pm10, pm12, pm13) ? pull-up resistor option register (puoh, puol) ? memory expansion mode register (mm) ? key return mode register (krm) (1) port mode registers (pm0 to pm3, pm5 to pm10, pm12, pm13) these registers are used to set port input/output in 1-bit units. pm0 to pm3, pm5 to pm10, pm12, and pm13 are independently set with a 1-bit or 8-bit memory manipulation instruction reset input sets registers to ffh. when port pins are used as alternate-function pins, set the port mode register and output latch according to table 6-6. cautions 1. pins p00 and p07 are input-only pins. 2. as port 0 has an alternate function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. when the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand. 3. the memory expansion mode register specifies p40 to p47 as input/output pins. 158 chapter 6 port functions p00 intp0 input 1 (fixed) none p50 to p57 a8 to a15 output x note 2 ti00 input 1 (fixed) none p64 rd output x note 2 p01 intp1 input 1 x p65 wr output x note 2 ti01 input 1 x p66 wait input x note 2 p02 to p06 intp2 to intp6 input 1 x p67 astb output x note 2 p07 note 1 xt1 input 1 (fixed) none p80 to p87 a0 to a7 output x note 3 p10 to p17 note 1 ani0 to ani7 input 1 x p100 ti5 input 1 x p30 to p32 to0 to to2 output 0 0 to5 output 0 0 p33, p34 ti1, ti2 input 1 x p101 ti6 input 1 x p35 pcl output 0 0 to6 output 0 0 p36 buz output 0 0 p120 to p127 rtp0 to rtp7 output 0 desired value p40 to p47 ad0 to ad7 input/output x note 2 p130,p131 note 1 ano0, ano1 output 1 x table 6-6. port mode register and output latch settings when using alternate function alternate function input/output pin name name alternate function pxx pmxx input/output pin name name notes 1. if these ports are read out when these pins are used in the alternative function mode, undefined values are read. 2. when the p40 to p47 pins p50 to p57 pins, and p64 to p67 pins are used for alternate functions, set the function with the memory extension mode register (mm). 3. when the p80 to p87 pins are used for alternate functions, set the function with the external bus type selection register (ebts). cautions 1. when not using external wait in the external memory extension mode, the p66 pin can be used as an i/o port. 2. when port 2 and port 7 are used for serial interface, the i/o latch or output latch must be set according to its function. for the setting methods, see figure 17-4. serial operation mode register 0 format, figure 18-4. serial operation mode register 0 format, figure 19-3. serial operation mode register 1 format, and table 20-2. operating mode setting for serial interface channel 2. remarks x : dont care pmxx : port mode register pxx : port output latch pxx pmxx 159 chapter 6 port functions figure 6-24. port mode register format pm0 pm1 pm2 1 pm06 pm03 pm02 pm01 1 76543210 symbol pm3 pm5 ff20h ff21h ff22h ff23h ff25h ffh ffh ffh ffh ffh r/w r/w r/w r/w r/w address after reset r/w pm17 pm16 pm15 pm14 pm13 pm12 pm11 pm10 pm27 pm26 pm25 pm24 pm23 pm22 pm21 pm20 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 pm57 pm56 pm55 pm54 pm53 pm52 pm51 pm50 pm6 pm7 pm8 ff26h ff27h ff28h ffh ffh ffh r/w r/w r/w pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 1 1 1 1 1 pm72 pm71 pm70 pm87 pm86 pm85 pm84 pm83 pm82 pm81 pm80 pm05 pm04 pm9 ff29h ffh r/w 1 pm96 pm95 pm94 pm93 pm92 pm91 pm90 pm10 pm12 pm13 pmmn pmn pin input/output mode selection (m = 0 to 3, 5 to 10, 12, 13 : n = 0 to 7) 0 1 output mode (output buffer on) input mode (output buffer off) ff2ah ff2ch ff2dh ffh ffh ffh r/w r/w r/w 1111 pm103 pm102 pm101 pm100 pm122 pm121 pm120 111111 pm131 pm130 pm125 pm124 pm123 pm127 pm126 160 chapter 6 port functions (2) pull-up resistor option register (puoh, puol) this register is used to set whether to use an internal pull-up resistor at each port or not. a pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with puoh, puol. no on-chip pull-up resistors can be used to the bits set to the output mode or to the bits used as an analog input pin, irrespective of puoh or puol setting. puoh and puol are set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. cautions 1. p00 and p07 pins do not incorporate a pull-up resistor. 2. when ports 1, 4, 5, and p64 to p67 pins, or port 8 pins are used as dual-function pins, an on-chip pull-up resistor cannot be used even if 1 is set in puom bit of puoh and puol (m = 1, 4 to 6, or 8). 3. pins p60 to p63 and p90 to p93 can be incorporated with pull-up resistor by mask option only for mask rom version. figure 6-25. pull-up resistor option register format caution bits 3, 6, and 7 of puoh should be set to 0. puo7 puo6 puo5 puo4 puo2 puo1 puo0 puol puom pm internal pull-up resistor selection (m = 0 to 10, 12, 13) 0 1 internal pull-up resistor not used internal pull-up resistor used fff7h 00h r/w puo3 00 puo13 puo12 puo10 puo9 puo8 puoh fff3h 00h r/w 7 6 <5> <4> symbol address after reset r/w 0 6 3 <2> <0> <1> <7> 6 <5> <4> <6> <3> <2> <0> <1> 161 chapter 6 port functions (3) memory expansion mode register (mm) this register is used to set input/output of port 4. mm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 10h. figure 6-26. memory expansion mode register format notes 1. these pins can be used only in the separate bus mode. they enter the port mode when the device is switched to the multiplexed bus mode. 2. the full address mode allows external expansion for all areas of the 64-kbyte address space, except the internal rom, ram, sfr, and use-prohibited areas. remarks 1. p60 to p63 pins enter the port mode in both the single-chip and memory expansion mode. 2. besides setting port 4 input/output, mm also sets the wait count and external expansion area. 00pw1 0 mm fff8h 10h r/w 76 5432 symbol address after reset r/w 1 pw0 mm2 mm1 mm0 0 mm2 mm1 mm0 000 001 011 100 101 111 other than above setting prohibited single-chip/memory expansion mode selection single-chip mode 256-byte mode 4-kbyte mode 16-kbyte mode full note 2 address mode memory expansion mode ad0 to ad7 input out- put port mode p40 to p47 p80 to p87 p56, p57 p64 to p67 port mode port mode port mode port mode a14, a15 a12, a13 p64 = rd p65 = wr p66 = wait p67 = astb pw1 pw0 0 0 0 1 1 1 0 1 wait control no wait wait (one wait state insertion) setting prohibited wait control by external wait pin p50 to p53 p54, p55 a0 to a7 note 1 a8 to a11 p40 to p47, p50 to p57, p64 to p67, p80 to p87 pin state 162 chapter 6 port functions (4) key return mode register (krm) this register sets enabling/disabling of standby function release by a key return signal (falling edge detection of port 4). krm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets krm to 02h. figure 6-27. key return mode register format caution when falling edge detection of port4 is used, krif should be cleared to 0 (not cleared to 0 automatically). krif key return signal detection flag 0 1 not detected detected (falling edge detection of port 4) 000 0 krm fff6h 76 5432 symbol <1> 0 krmk krif <0> 0 krmk standby mode control by key return signal 0 1 standby mode release enabled standby mode release disabled address after reset r/w 02h r/w 163 chapter 6 port functions 6.4 port function operations port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 writing to input/output port (1) output mode a value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode a value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. once data is written to the output latch, it is retained until data is written to the output latch again. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit. 6.4.2 reading from input/output port (1) output mode the output latch contents are read by a transfer instruction. the output latch contents do not change. (2) input mode the pin status is read by a transfer instruction. the output latch contents do not change. 6.4.3 operations on input/output port (1) output mode an operation is performed on the output latch contents, and the result is written to the output latch. the output latch contents are output from the pins. once data is written to the output latch, it is retained until data is written to the output latch again. (2) input mode the output latch contents are undefined, but since the output buffer is off, the pin status does not change. caution in the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 164 chapter 6 port functions 6.5 selection of mask option the following mask option is provided in mask rom version. the m pd78p078 and 78p078y have no mask option. table 6-7. comparison between mask rom version and the m pd78p078 and 78p078y pin name mask rom version m pd78p078 and 78p078y mask option for pins p60 to p63 and bitwise-selectable on-chip pull-up no on-chip pull-up resistor p90 to p93 resistors 165 chapter 7 clock generator 7.1 clock generator functions the clock generator generates the clock to be supplied to the cpu and peripheral hardware. the following two types of system clock oscillators are available. (1) main system clock oscillator this circuit oscillates at frequencies of 1 to 5.0 mhz. oscillation can be stopped by executing the stop instruction or setting the processor clock control register (pcc). (2) subsystem clock oscillator the circuit oscillates at a frequency of 32.768 khz. oscillation cannot be stopped. if the subsystem clock oscillator is not used, not using the internal feedback resistance can be set by the processor clock control register (pcc). this enables to decrease power consumption in the stop mode. 166 chapter 7 clock generator subsystem clock oscillator main system clock oscillator x2 x1 xt2 xt1/p07 frc stop mcc frc cls css pcc2 pcc1 internal bus standby control circuit to intp0 sampling clock 2 f xx 2 2 f xx 2 3 f xx 2 4 f xx prescaler clock to peripheral hardware prescaler oscillation mode selection register watch timer, clock output function f xx cpu clock (f cpu ) wait control circuit divider selector f x f xt 2 f x mcs processor clock control register 1/2 2 f xt pcc0 3 selector 7.2 clock generator configuration the clock generator consists of the following hardware. table 7-1. clock generator configuration item configuration control register processor clock control register (pcc) oscillation mode selection register (osms) oscillator main system clock oscillator subsystem clock oscillator figure 7-1. block diagram of clock generator 167 chapter 7 clock generator 7.3 clock generator control register the clock generator is controlled by the following two registers: ? processor clock control register (pcc) ? oscillation mode selection register (osms) (1) processor clock control register (pcc) the pcc selects a cpu clock and the division ratio, determines whether to make the main system clock oscillator operate or stop, and enables or desables the subsystem clock oscillator internal feedback resistor. the pcc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets the pcc to 04h. figure 7-2. subsystem clock feedback resistor frc p-ch feedback resistor xt1 xt2 168 chapter 7 clock generator mcc frc cls css pcc2 pcc1 pcc0 pcc cls 0 1 main system clock subsystem clock fffbh 04h <7> <6> <5> <4> symbol address after reset r/w r/w note 1 0 32 0 1 css 0 0f xx /2 pcc2 cpu ciock (f cpu ) selection pcc1 pcc0 cpu clock status 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 f xx /2 2 f xx /2 3 f xx /2 4 f xx setting prohibited other than above frc 0 1 internal feedback resistor used internal feedback resistor not used subsystem clock feedback resistor selection mcc 0 1 oscillation possible oscillation stopped main system clock oscillation control note 2 r/w r/w r/w r f x f x /2 f x /2 2 f xt /2 f x /2 3 f x /2 4 f x /2 2 f x /2 f x /2 3 f x /2 4 f x /2 5 mcs = 1 mcs = 0 0 1 figure 7-3. processor clock control register format notes 1. bit 5 is a read-only bit. 2. when the cpu is operating on the subsystem clock, mcc should be used to stop the main system clock oscillation. a stop instruction should not be used. caution bit 3 must be set to 0. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. mcs : bit 0 of oscillation mode selection register (osms) 169 chapter 7 clock generator the fastest instruction of the m pd78078 and 78078y subseries can be executed in two clocks of the cpu clock. the relationship between the cpu clock (f cpu ) and the minimum instruction execution time is shown in table 7-2. table 7-2. relationship between cpu clock and minimum instruction execution time cpu clock (f cpu ) minimum instruction execution time: 2/f cpu f x 0.4 m s f x /2 0.8 m s f x /2 2 1.6 m s f x /2 3 3.2 m s f x /2 4 6.4 m s f x /2 5 12.8 m s f xt /2 122 m s f x = 5.0 mhz, f xt = 32.768 khz f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency 170 chapter 7 clock generator (2) oscillation mode selection register (osms) this register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock. osms is set with 8-bit memory manipulation instruction. reset input sets osms to 00h. figure 7-4. oscillation mode selection register format cautions 1. as shown in figure 7-5 below, writing data (including same data as previous) to osms cause delay of main system clock cycle up to 2/f x during the write operation. therefore, if this register is written during the operation, in peripheral hardware which operates with the main system clock, a temporary error occurs in the count clock cycle of timer, etc. in addition, because the oscillation mode is changed by this register, the clocks for peripheral hardware as well as that for the cpu are switched. therefore, writing to osms should be performed only immediately after reset signal release and before peripheral hardware operation starts. 2. when writing 1 to mcs, v dd must be 2.7 v or higher before the write execution. figure 7-5. main system clock waveform due to writing to osms remarks fxx : main system clock frequency (fx or fx/2) fx : main system clock oscillation frequency mcs main system clock scaler control 0 1 scaler used scaler not used 000 0 osms fff2h 76 5432 symbol 1 0mcs 0 0 address after reset r/w 00h w 0 write to osms (mcs 0) f xx max. 2/f x operating at f xx = f x /2 (mcs = 0) operating at f xx = f x /2 (mcs = 0) 171 chapter 7 clock generator 7.4 system clock oscillator 7.4.1 main system clock oscillator the main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 mhz) connected to the x1 and x2 pins. external clocks can be input to the main system clock oscillator. in this case, input a clock signal to the x1 pin and an antiphase clock signal to the x2 pin. figure 7-6 shows an external circuit of the main system clock oscillator. figure 7-6. external circuit of main system clock oscillator (a) crystal and ceramic oscillation (b) external clock caution do not execute the stop instruction nor set mcc (bit 7 of the processor clock control register (pcc)) to 1 while an external clock is input. this is because the operation of main system clock is stopped and x2 pin is pulled-up to v dd when a stop instruction is executed and mcc is set to 1. crystal or ceramic resonator ic x1 x2 x1 pd74hcu04 x2 external clock 172 chapter 7 clock generator 7.4.2 subsystem clock oscillator the subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 khz) connected to the xt1 and xt2 pins. external clocks can be input to the subsystem clock oscillator. in this case, input a clock signal to the xt1 pin and an antiphase clock signal to the xt2 pin. figure 7-7 shows an external circuit of the subsystem clock oscillator. figure 7-7. external circuit of subsystem clock oscillator (a) crystal oscillation (b) external clock cautions 1. when using a main system clock oscillator and a subsystem clock oscillator, carry out wiring in the broken-line area in figures 7-6 and 7-7 as follows to prevent any effects from wiring capacities. ? minimize the wiring length. ? do not allow wiring to intersect with other signal conductors. do not allow wiring to come near abruptly changing high current. ? set the potential of the grounding position of the oscillator capacitor to that of v ss . do not ground to any ground pattern where high current is present. ? do not fetch signals from the oscillator. take special note of the fact that the subsystem clock oscillator is a circuit with low-level amplification so that current consumption is maintained at low levels. figure 7-8 shows examples of oscillator having bad connection. figure 7-8. examples of oscillator with bad connection (1/2) (a) wiring of connection (b) a signal line crosses over circuits is too long oscillation circuit lines remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. further, insert resistors in series on the side of xt2. external clock xt2 xt1 pd74hcu04 xt2 xt1 32.768 khz ic ic x2 x1 x2 x1 portn (n = 0 to 10, 12, 13) ic 173 chapter 7 clock generator figure 7-8. examples of oscillator with bad connection (2/2) (c) changing high current is too near a (d) current flows through the grounding line signal conductor of the oscillator (potential at points a, b, and c fluctuate) (e) signals are fetched (f) signal conductors of the main and sub- system clock are parallel and near each other remark when using a subsystem clock, replace x1 and x2 with xt1 and xt2, respectively. also, insert resistors in series on the xt2 side. cautions 2. in figure 7-8 (f), xt2 and x1 are wired in parallel. thus, the cross-talk noise of x1 may increase with xt2, resulting in malfunctioning. to prevent that from occurring, it is recommended to wire xt2 and x1 so that they are not in parallel, and to connect the ic pin between xt1 and x1 directly to v ss . ic x2 x1 high current ic x2 ab c pnm v dd high current x1 ic x2 x1 ic x2 x1 xt1 xt2 xt1 and xt2 are wiring in parallel 174 chapter 7 clock generator 7.4.3 divider the divider generates various clocks by dividing the main system clock oscillator output (f xx ). 7.4.4 when no subsystem clocks are used if it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the xt1 and xt2 pins as follows. xt1 : connect to v dd xt2 : open in this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator when the main system clock stops. to minimize leakage current, set bit 6 (frc) of the processor clock control register (pcc) so that the above internal feedback resistor is not used. in this case also, connect the xt1 and xt2 pins as described above. 175 chapter 7 clock generator 7.5 clock generator operations the clock generator generates the following various types of clocks and controls the cpu operating mode including the standby mode. ? main system clock f xx ? subsystem clock f xt ? cpu clock f cpu ? clock to peripheral hardware the following clock generator functions and operations are determined with the processor clock control register (pcc) and the oscillation mode selection register (osms). (a) upon generation of reset signal, the lowest speed mode of the main system clock (12.8 m s when operated at 5.0 mhz) is selected (pcc = 04h, osms = 00h). main system clock oscillation stops while the low level is applied to reset pin. (b) with the main system clock selected, one of the five cpu clock stages (f xx , f xx /2, f xx /2 2 , f xx /2 3 or f xx /2 4 ) can be selected by setting the pcc and osms. (c) with the main system clock selected, two standby modes, the stop and halt modes, are available. in a system which is not using the subsystem clock, the current consumption in the stop mode can be reduced further by setting bit 6 (frc) of the pcc so as not to use the on-chip feedback resistor. (d) the pcc can be used to select the subsystem clock and to operate the system with low current consumption (122 m s when operated at 32.768 khz). (e) with the subsystem clock selected, main system clock oscillation can be stopped with the pcc. the halt mode can be used. however, the stop mode cannot be used. (subsystem clock oscillation cannot be stopped.) (f) the main system clock is divided and supplied to the peripheral hardware. the subsystem clock is supplied to 16-bit timer/event counter, the watch timer, and clock output functions only. thus, 16-bit timer/event counter (when selecting watch timer output for count clock operating with subsystem clock), the watch function, and the clock output function can also be continued in the standby state. however, since all other peripheral hardware operate with the main system clock, the peripheral hardware also stops if the main system clock is stopped. (except external input clock operation) 176 chapter 7 clock generator 7.5.1 main system clock operations when operated with the main system clock (with bit 5 (cls) of the processor clock control register (pcc) set to 0), the following operations are carried out by pcc setting. (a) because the operation guarantee instruction execution speed depends on the power supply voltage, the minimum instruction execution time can be changed by bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) if bit 7 (mcc) of the pcc is set to 1 when operated with the main system clock, the main system clock oscillation does not stop. when bit 4 (css) of the pcc is set to 1 and the operation is switched to subsystem clock operation (cls = 1) after that, the main system clock oscillation stops (see figure 7-9 ). figure 7-9. main system clock stop function (1/2) (a) operation when mcc is set after setting css with main system clock operation (b) operation when mcc is set in case of main system clock operation mcc css cls main system clock oscillation subsystem clock oscillation cpu clock mcc css cls main system clock oscillation subsystem clock oscillation cpu clock l l oscillation does not stop. 177 chapter 7 clock generator figure 7-9. main system clock stop function (2/2) (c) operation when css is set after setting mcc with main system clock operation 7.5.2 subsystem clock operations when operated with the subsystem clock (with bit 5 (cls) of the processor clock control register (pcc) set to 1), the following operations are carried out. (a) the minimum instruction execution time remains constant (122 m s when operated at 32.768 khz) irrespective of bits 0 to 2 (pcc0 to pcc2) of the pcc. (b) watchdog timer counting stops. caution do not execute the stop instruction while the subsystem clock is in operation. mcc css cls main system clock oscillation subsystem clock oscillation cpu clock 178 chapter 7 clock generator 7.6 changing system clock and cpu clock settings 7.6.1 time required for switchover between system clock and cpu clock the system clock and cpu clock can be switched over by means of bit 0 to bit 2 (pcc0 to pcc2) and bit 4 (css) of the processor clock control register (pcc). the actual switchover operation is not performed directly after writing to the pcc, but operation continues on the pre-switchover clock for several instructions (see table 7-3). determination as to whether the system is operating on the main system clock or the subsystem clock is performed by bit 5 (cls) of the pcc register. table 7-3. maximum time required for cpu clock switchover set values after switchover set values before switchover mcs css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 css pcc2 pcc1 pcc0 00000001001000110100 1xxx x 0 0 0 0 8 instructions 4 instructions 2 instructions 1 instruction 1 instruction 001 16 instructions 4 instructions 2 instructions 1 instruction 1 instruction 010 16 instructions 8 instructions 2 instructions 1 instruction 1 instruction 011 16 instructions 8 instructions 4 instructions 1 instruction 1 instruction 100 16 instructions 8 instructions 4 instructions 2 instructions 1 instruction 11 x x x f x /2f xt instruction f x /4f xt instruction f x /8f xt instruction f x /16f xt instruction f x /32f xt instruction (77 instructions) (39 instructions) (20 instructions) (10 instructions) (5 instructions) 0 f x /4f xt instruction f x /8f xt instruction f x /16f xt instruction f x /32f xt instruction f x /64f xt instruction (39 instructions) (20 instructions) (10 instructions) (5 instructions) (3 instructions) caution selection of the cpu clock cycle scaling factor (pcc0 to pcc2) and switchover from the main system clock to the subsystem clock (changing css from 0 to 1) should not be performed simultaneously. simultaneous setting is possible, however, for selection of the cpu clock cycle scaling factor (pcc0 to pcc2) and switchover from the subsystem clock to the main system clock (changing css from 1 to 0). remarks 1. one instruction is the minimum instruction execution time with the pre-switchover cpu clock. 2. figures in parentheses apply to operation with f x = 5.0 mhz and f xt = 32.768 khz. 179 chapter 7 clock generator 7.6.2 system clock and cpu clock switching procedure this section describes switching procedure between system clock and cpu clock. figure 7-10. system clock and cpu clock switching (1) the cpu is reset by setting the reset signal to low level after power-on. after that, when reset is released by setting the reset signal to high level, main system clock starts oscillation. at this time, oscillation stabilization time (2 17 /f x ) is secured automatically. after that, the cpu starts executing the instruction at the minimum speed of the main system clock (12.8 m s when operated at 5.0 mhz). (2) after the lapse of a sufficient time for the v dd voltage to increase to enable operation at maximum speeds, the processor clock control register (pcc) and oscillation mode selection register (osms) are rewritten and the maximum-speed operation is carried out. (3) upon detection of a decrease of the v dd voltage due to an interrupt request signal, the main system clock is switched to the subsystem clock (which must be in an oscillation stable state). (4) upon detection of v dd voltage reset due to an interrupt request signal, 0 is set to bit 7 (mcc) of pcc and oscillation of the main system clock is started. after the lapse of time required for stabilization of oscillation, the pcc and osms are rewritten and the maximum-speed operation is resumed. caution when subsystem clock is being operated while main system clock was stopped, if switching to the main system clock is made again, be sure to switch after securing oscillation stable time by software. v dd reset interrupt request signal system clock cpu clock wait (26.2 ms : 5.0 mhz) internal reset operation minimum speed operation maximum speed operation subsystem clock operation f xx f xx f xt f xx high-speed operation 180 [memo] 181 chapter 8 16-bit timer/event counter 8.1 outline of timers incorporated into m pd78078, 78078y subseries this chapter explains the 16-bit timer/event counter. first of all, the timers incorporated into the m pd78078, 78078y subseries and the related circuits are outlined below. (1) 16-bit timer/event counter (tm0) the tm0 can be used for an interval timer, pwm output, pulse widths measurement (infrared ray remote control receive function), external event counter, square wave output of any frequency or one-shot pulse output. (2) 8-bit timers/event counters 1 and 2 (tm1 and tm2) tm1 and tm2 can be used to serve as an interval timer and an external event counter and to output square waves with any selected frequency. two 8-bit timer/event counters can be used as one 16-bit timer/event counter (see chapter 9 8-bit timer/event counters 1 and 2 ). (3) 8-bit timer/event counters 5 and 6 (tm5 and tm6) tm5 and tm6 can be used to serve as an interval timer and external event counter and to output any frecuency square waves. these cannot be used as 16-bit timer/event counters (see chapter 10 8- bit timer/event counter 5 and 6 ). (4) watch timer (tm3) this timer can set a flag every 0.5 sec. and simultaneously generates interrupt requests at the preset time intervals (see chapter 11 watch timer ). (5) watchdog timer (wdtm) wdtm can perform the watchdog timer function or generate non-maskable interrupt requests, maskable interrupt requests and reset at the preset time intervals (see chapter 12 watchdog timer ). (6) clock output control circuit this circuit supplies other devices with the divided main system clock and the subsystem clock (see chapter 13 clock output control circuit ). (7) buzzer output control circuit this circuit outputs the buzzer frequency obtained by dividing the main system clock (see chapter 14 buzzer output control circuit ). 182 chapter 8 16-bit timer/event counter table 8-1. timer/event counter operations operation interval timer 2 channels note 3 2 channels 2 channels 1 channel note 1 1 channel note 2 mode external event counter ??? ?? function timer output ??? ?? pwm output ? ? ? ?? pulse width measurement ? ???? square-wave output ??? ?? one-shot pulse output ? ???? interrupt request ????? test input ? ? ? ? ? notes 1. the watch timer can perform both watch timer and interval timer functions at the same time. 2. the watchdog timer can perform either the watchdog timer function or the interval timer function. 3. when capture/compare registers (cr00, cr01) are specified as compare registers. 16-bit timer/ 8-bit timer/event 8-bit timer/event watch timer watchdog timer event counter counters 1 and 2 counters 5 and 6 183 chapter 8 16-bit timer/event counter 8.2 16-bit timer/event counter functions the 16-bit timer/event counter (tm0) has the following functions. ? interval timer ? pwm output ? pulse width measurement ? external event counter ? square-wave output ? one-shot pulse output tm0 can perform both pwm output and pulse width measurement at the same time. (1) interval timer tm0 generates interrupt requests at the preset time interval. table 8-2. 16-bit timer/event counter interval times minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 x ti00 input cycle 2 16 x ti00 input cycle ti00 input edge cycle 2 x 1/f x 2 16 x 1/f x 1/f x (400 ns) (13.1 ms) (200 ns) 2 x 1/f x 2 2 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 1/f x 2 x 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 2 2 x 1/f x 2 3 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 x 1/f x 2 2 x 1/f x (800 ns) (1.6 m s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 3 x 1/f x 2 4 x 1/f x 2 18 x 1/f x 2 19 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (1.6 m s) (3.2 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 x watch timer output cycle 2 16 x watch timer output cycle watch timer output edge cycle remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. (2) pwm output tm0 can generate 14-bit resolution pwm output. (3) pulse width measurement tm0 can measure the pulse width of an externally input signal. (4) external event counter tm0 can measure the number of pulses of an externally input signal. 184 chapter 8 16-bit timer/event counter (5) square-wave output tm0 can output a square wave with any selected frequency. table 8-3. 16-bit timer/event counter square-wave output ranges minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 x ti00 input cycle 2 16 x ti00 input cycle ti00 input edge cycle 2 x 1/f x 2 16 x 1/f x 1/f x (400 ns) (13.1 ms) (200 ns) 2 x 1/f x 2 2 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 1/f x 2 x 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 2 2 x 1/f x 2 3 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 x 1/f x 2 2 x 1/f x (800 ns) (1.6 m s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 3 x 1/f x 2 4 x 1/f x 2 18 x 1/f x 2 19 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (1.6 m s) (3.2 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 x watch timer output cycle 2 16 x watch timer output cycle watch timer output edge cycle remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses operation with f x = 5.0 mhz. (6) one-shot pulse output tm0 is able to output one-shot pulse which can set any width of output pulse. 185 chapter 8 16-bit timer/event counter 8.3 16-bit timer/event counter configuration the 16-bit timer/event counter consists of the following hardware. table 8-4. 16-bit timer/event counter configuration item configuration timer register 16 bits x 1 (tm0) register capture/compare register: 16 bits x 2 (cr00, cr01) timer output 1 (to0) timer clock select register 0 (tcl0) 16-bit timer mode control register (tmc0) capture/compare control register 0 (crc0) control register 16-bit timer output control register (toc0) port mode register 3 (pm3) external interrupt mode register 0 (intm0) sampling clock select register (scs) note note refer to figure 22-1 basic configuration of interrupt function . 186 chapter 8 16-bit timer/event counter figure 8-1. 16-bit timer/event counter block diagram notes 1. edge detection circuit 2. the configuration of the 16-bit timer/event counter output control circuit is shown in figure 8-2. internal bus capture/compare control register 0 crc02 crc01 crc00 selector ti01 / p01 / intp1 inttm3 2f xx f xx f xx /2 f xx /2 2 ti00 / p00 / intp0 selector 3 tcl06 tcl05 tcl04 timer clock selection register 0 crc02 16-bit capture/compare control register (cr01) internal bus 16-bit capture/compare control register (cr00) 16-bit timer register (tm0) clear match clear circuit tmc03 tmc02 tmc01 ovf0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 16-bit timer mode control register 16-bit timer output control register 2 pwm pulse output control 16-bit timer/event counter output control circuit note 2 tmc01 to tmc03 intp0 inttm01 to0/p30 intp1 inttm00 match tmc01 to tmc03 3 note 1 187 chapter 8 16-bit timer/event counter figure 8-2. 16-bit timer/event counter output control circuit block diagram remark the circuitry enclosed by the dotted line is the output control circuit. pwm pulse output control circuit edge detection circuit 2 es11 es10 ti00 / p00 / intp0 external interrupt mode register 0 ospt 16-bit timer output control register ospe toc04 lvs0 lvr0 toc01 toe0 16-bit timer mode control register tmc03 tmc02 tmc01 p30 output latch pm30 port mode register 3 to0/p30 selector inv s r q 3 level inversion crc02 inttm01 crc00 inttm00 one-shot pulse output control circuit internal bus selector 188 chapter 8 16-bit timer/event counter (1) capture/compare register 00 (cr00) cr00 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or as a compare register is set by bit 0 (crc00) of capture/compare control register 0 (crc0). when cr00 is used as a compare register, the value set in the cr00 is constantly compared with the 16- bit timer register (tm0) count value, and an interrupt request (inttm00) is generated if they match. cr00 is used as a register to hold the interval time when tm0 is set to interval timer operation, and it is used as a register to set the pulse width when tm0 is set to the pwm output operation. when cr00 is used as a capture register, it is possible to select the valid edge of the intp0/ti00 pin or the intp1/ti01 pin as the capture trigger. the intp0/ti00 or intp1/ti01 valid edge is set by means of external interrupt mode register 0 (intm0). if cr00 is specified as a capture register and capture trigger is specified to be the valid edge of the intp0/ ti00 pin, the situation is as shown in the following table. table 8-5. intp0/ti00 pin valid edge and cr00 capture trigger valid edge es11 es10 intp0/ti00 pin valid edge cr00 capture trigger valid edge 0 0 falling edge rising edge 0 1 rising edge falling edge 1 0 setting prohibited 1 1 both rising and falling edges no capture operation cr00 is set by a 16-bit memory manipulation instruction. after reset input, the value of cr00 is undefined. cautions 1. set the pwm data (14 bits) to the higher 14 bits of cr00 and set 00 to the lower 2 bits. 2. set values other than 0000h to cr00. therefore, when used as an event counter, 1-pulse count operation cannot be executed. 3. when the value after cr00 is changed is smaller than the 16-bit timer register (tm0) value, tm0 continues to count, overflows, and resumes counting from zero. therefore, when the value after cr00 is changed (m) is smaller than the value before cr00 is changed (n), it is necessary to restart the timer after changing cr00. (2) capture/compare register 01 (cr01) cr01 is a 16-bit register which has the functions of both a capture register and a compare register. whether it is used as a capture register or a compare register is set by bit 2 (crc02) of capture/compare control register 0. when cr01 is used as a compare register, the value set in the cr01 is constantly compared with the 16- bit timer register (tm0) count value, and an interrupt request (inttm01) is generated if they match. when cr01 is used as a capture register, it is possible to select the valid edge of the intp0/ti00 pin as the capture trigger. setting of the intp0/ti00 valid edge is set by means of external interrupt mode register 0 (intm0). cr01 is set with a 16-bit memory manipulation instruction. after reset input, the value of cr01 is undefined. caution if a valid edge of ti0/p00 pin is input while reading out cr01, cr01 does not carry out capture operation and retains the data. however, the interrupt request flag (pif0) is set by the detection of a valid edge. 189 chapter 8 16-bit timer/event counter (3) 16-bit timer register (tm0) tm0 is a 16-bit register which counts the count pulses. tm0 is read by a 16-bit memory manipulation instruction. when tm0 is read, capture/compare register (cr01) should first be set as a capture register. reset input sets tm0 to 0000h. caution as the value of tm0 is read via cr01, the previously set value of cr01 is lost. 190 chapter 8 16-bit timer/event counter 8.4 16-bit timer/event counter control registers the following seven types of registers are used to control the 16-bit timer/event counter. ? timer clock select register 0 (tcl0) ? 16-bit timer mode control register (tmc0) ? capture/compare control register 0 (crc0) ? 16-bit timer output control register (toc0) ? port mode register 3 (pm3) ? external interrupt mode register 0 (intm0) ? sampling clock select register (scs) (1) timer clock select register 0 (tcl0) this register is used to set the count clock of the 16-bit timer register. tcl0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tcl0 value to 00h. remark tcl0 has the function of setting the pcl output clock in addition to that of setting the count clock of the 16-bit timer register. 191 chapter 8 16-bit timer/event counter figure 8-3. timer clock selection register 0 format cautions 1. external interrupt mode register 0 (intm0) sets the ti00/intp0 pin valid edge, and the sampling clock selection register (scs) selects the sampling clock. 2. when enabling pcl output, set tcl00 to tcl03, then set 1 in cloe with a 1-bit memory manipulation instruction. 3. to read the count value when ti00 has been specified as the tm0 count clock, the value should be read from tm0, not from capture/compare register 01 (cr01). 4. when rewriting tcl0 to other data, stop the timer operation beforehand. cloe tcl06 tcl05 tcl04 tcl03 tcl02 tcl01 tcl00 <7>6543210 symbol tcl0 tcl03 tcl02 tcl01 tcl00 0000f xt (32.768 khz) 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 1 pcl output clock selection mcs = 0 ff40h 00h r/w address after reset r/w other than above setting prohibited tcl06 tcl05 tcl04 0 0 0 ti00 (valid edge specifiable) 0012f xx setting prohibited f x (5.0 mhz) 010f xx f x (5.0 mhz) f x /2 (2.5 mhz) 011f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 100f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1 1 1 watch timer output (inttm3) mcs = 1 16-bit timer register count clock selection mcs = 0 other than above setting prohibited cloe 1 output enabled pcl output control 0 output disabled 192 chapter 8 16-bit timer/event counter remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. ti00 : 16-bit timer/event counter input pin 5. tm0 : 16-bit timer register 6. mcs : bit 0 of oscillation mode selection register (osms) 7. figures in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. (2) 16-bit timer mode control register (tmc0) this register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. tmc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc0 value to 00h. caution the 16-bit timer register starts operation when a value other than 0, 0, 0 (operation stop mode) is set in tmc01 to tmc03, respectively. set 0, 0, 0 in tmc01 to tmc03 to stop the operation. figure 8-4. 16-bit timer mode control register format 0000 tmc03 tmc02 tmc01 ovf0 7654321<0> symbol tmc0 ff48h 00h r/w address after reset r/w ovf0 16-bit timer register overflow detection 0 overflow not detected 1 overflow detected tmc03 tmc02 tmc01 operating mode and clear mode to0 output timing interrupt generation 000 operation stop (tm0 cleared to 0) no change not generated 001 pwm mode (free running) pwm pulse output 010 011 100 101 110 111 free running mode tm0 and cr00 match, or tm0 and cr01 match. tm0 and cr00 match, tm0 and cr01 match, or on ti00 valid edge. tm0 and cr00 match, or tm0 and cr01 match. tm0 and cr00 match, tm0 and cr01 match, or on ti00 valid edge tm0 and cr00 match, or tm0 and cr01 match. tm0 and cr00 match, tm0 and cr01 match, or on ti00 valid edge clear & start on ti00 valid edge clear & start when tm0 and cr00 match generated when tm0 and cr00 match, or tm0 and cr01 match. 193 chapter 8 16-bit timer/event counter cautions 1. switch the clear mode and the t00 output timing after stopping the timer operation (by setting tmc01 to tmc03 to 0, 0, 0). 2. set the valid edge of the ti00/intp0 pin with an external interrupt mode register 0 (intm0) and select the sampling clock frequency with a sampling clock select register (scs). 3. when using the pwm mode, set the pwm and then set data to cr00. 4. if the mode is set so that the timer is cleared and starts when tm0 and cr00 match, the ovf0 flag is set to 1 when the tm0 value changes from 0ffffh to 0000h with cr00 set to ffffh. remark to0 : 16-bit timer/event counter output pin ti00 : 16-bit timer/event counter input pin tm0 : 16-bit timer register cr00 : compare register 00 cr01 : compare register 01 (3) capture/compare control register 0 (crc0) this register controls the operation of the capture/compare registers (cr00, cr01). crc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets crc0 value to 04h. figure 8-5. capture/compare control register 0 format cautions 1. timer operation must be stopped before setting crc0. 2. when clear & start mode on a match between tm0 and cr00 is selected with the 16-bit timer mode control register, cr00 should not be specified as a capture register. 0000 0 crc02 crc01 crc00 76543210 symbol crc0 ff4ch 04h r/w address after reset r/w crc00 cr00 operating mode selection 0 operates as compare register 1 operates as capture register crc01 cr00 capture trigger selection captures on valid edge of ti01 captures on valid edge of ti00 0 1 crc02 cr01 operating mode selection operates as compare register operates as capture register 0 1 194 chapter 8 16-bit timer/event counter (4) 16-bit timer output control register (toc0) this register controls the operation of the 16-bit timer/event counter output control circuit. it sets r-s type flip-flop (lv0) setting/resetting, the active level in pwm mode, inversion enabling/disabling in modes other than pwm mode, 16-bit timer/event counter timer output enabling/disabling, one-shot pulse output operation enabling/disabling, and output trigger for a one-shop pulse by software. toc0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets toc0 value to 00h. figure 8-6. 16-bit timer output control register format cautions 1. timer operation must be stopped before setting toc0 (except ospt). 2. if lvs0 and lvr0 are read after data is set, they will be 0. 3. ospt is cleared automatically after data setting, and will therefore be 0 if read. 0 ospt ospe toc04 lvs0 lvr0 toc01 toe0 7 <6> <5> 4 <3> <2> 1 <0> symbol toc0 ff4eh 00h r/w address after reset r/w toe0 16-bit timer/event counter output control 0 output disabled (port mode) 1 output enabled toc01 0 1 in pwm mode in other modes active level selection timer output f/f control by match of cr00 and tm0 active high active low inversion operation disabled inversion operation enabled lvs0 lvr0 16-bit timer/event counter timer output f/f status setting 0 0 no change 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toc04 timer output f/f control by match of cr01 and tm0 0 inversion operation disabled 1 inversion operation enabled ospe one-shot pulse output control 0 continuous pulse output 1 one-shot pulse output ospt control of one-shot pulse output trigger by software 0 no one-shot pulse trigger 1 one-shot pulse trigger used 195 chapter 8 16-bit timer/event counter (5) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p30/to0 pin for timer output, set pm30 and output latch of p30 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 value to ffh. figure 8-7. port mode register 3 format pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 76543210 symbol pm3 ff23h ffh r/w address after reset r/w pm3n p3n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 196 chapter 8 16-bit timer/event counter (6) external interrupt mode register 0 (intm0) this register is used to set intp0 to intp2 valid edges. intm0 is set with an 8-bit memory manipulation instruction. reset input sets intm0 value to 00h. figure 8-8. external interrupt mode register 0 format caution set 0, 0, 0 to bits 1 through 3 (tmc01 through tmc03) of the 16-bit timer mode control register (tmc0) and stop the timer operation before setting the valid edges of intp0/ti00/ p00 pins. es31 es30 es21 es20 es11 es10 0 0 76543210 symbol intm0 ffech 00h r/w address after reset r/w es11 intp0 valid edge selection es10 0 falling edge 0 0 rising edge 1 1 setting prohibited 0 1 both falling and rising edges 1 es21 intp1 valid edge selection es20 0 falling edge 0 0 rising edge 1 1 setting prohibited 0 1 both falling and rising edges 1 es31 intp2 valid edge selection es30 0 falling edge 0 0 rising edge 1 1 setting prohibited 0 1 both falling and rising edges 1 197 chapter 8 16-bit timer/event counter (7) sampling clock select registers (scs) this register sets clocks which undergo clock sampling of valid edges to be input to intp0. when remote controlled reception is carried out using intp0, digital noise is removed with sampling clock. scs is set with an 8-bit memory manipulation instruction. reset input sets scs value to 00h. figure 8-9. sampling clock select register format caution f xx /2 n is the clock supplied to the cpu, and f xx /2 5 , f xx /2 6 , and f xx /2 7 are clocks supplied to peripheral hardware. f xx /2 n is stopped in halt mode. remarks 1. n : value set in bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc) (n = 0 to 4) 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency 4. mcs : bit 0 of oscillation mode selection register (osms) 5. figures in parentheses apply to operation with f x = 5.0 mhz. 0 0 0 0 0 0 scs1 scs0 76543210 symbol scs ff47h 00h r/w address after reset r/w scs1 scs0 00 01 10 11 intp0 sampling clock selection mcs = 1 mcs = 0 f xx /2 n f x /2 7 (39.1 khz) f xx /2 7 f x /2 8 (19.5 khz) f x /2 5 (156.3 khz) f xx /2 5 f x /2 6 (78.1 khz) f x /2 6 (78.1 khz) f xx /2 6 f x /2 7 (39.1 khz) 198 chapter 8 16-bit timer/event counter 8.5 16-bit timer/event counter operations 8.5.1 interval timer operations setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-10 allows operation as an interval timer. interrupt requests are generated repeatedly using the count value set in 16-bit capture/compare register 00 (cr00) beforehand is used as the interval. when the count value of the 16-bit timer register (tm0) matches the value set to cr00, counting continues with the tm0 value cleared to 0 and the interrupt request signal (inttm00) is generated. count clock of the 16-bit timer/event counter can be selected with bits 4 to 6 (tcl04 to tcl06) of the timer clock select register 0 (tcl0). for the operation in the case the value of the compare register is changed during the timer count operation, refer to 8.6 16-bit timer/event counter precautions (3) . figure 8-10. control register settings for interval timer operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the interval timer. see the description of the respective control registers for details. 0000110/10 tmc03 tmc02 tmc01 ovf0 tmc0 clear & start on match tm0 and cr00 0 0 0 0 0 0/1 0/1 0 crc02 crc01 crc00 crc0 cr00 set as compare register 199 chapter 8 16-bit timer/event counter t count clock tm0 count value cr00 inttm00 to0 interval time interval time interval time 0000 0001 n 0000 0001 n 0000 0001 n count start clear clear nn nn interrupt request acknowledge interrupt request acknowledge figure 8-11. interval timer configuration diagram figure 8-12. interval timer operation timings remark interval time = (n + 1) x t : n = 0001h to ffffh. 16-bit capture/compare register 00 (cr00) 16-bit timer register (tm0) selector f xx /2 2 f xx /2 f xx 2f xx inttm3 ti00/p00/intp0 ovf0 clear circuit inttm00 200 chapter 8 16-bit timer/event counter table 8-6. 16-bit timer/event counter interval times minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0 0 0 2 x ti00 input cycle 2 16 x ti00 input cycle ti00 input edge cycle 0 0 1 setting 2 x 1/f x setting 2 16 x 1/f x setting 1/f x prohibited (400 ns) prohibited (13.1 ms) prohibited (200 ns) 0 1 0 2 x 1/f x 2 2 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 1/f x 2 x 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 0112 2 x 1/f x 2 3 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 x 1/f x 2 2 x 1/f x (800 ns) (1.6 m s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 1002 3 x 1/f x 2 4 x 1/f x 2 18 x 1/f x 2 19 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (1.6 m s) (3.2 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 1 1 1 2 x watch timer output cycle 2 16 x watch timer output cycle watch timer output edge cycle other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. tcl04 to tcl06 : bits 4 to 6 of timer clock select register 0 (tcl0) 4. figures in parentheses apply to operation with f x = 5.0 mhz. 8.5.2 pwm output operations setting the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16-bit timer output control register (toc0) as shown in figure 8-13 allows operation as pwm output. pulses with the duty rate determined by the value set in 16-bit capture/compare register 00 (cr00) beforehand are output from the to0/ p30 pin. set the active level width of the pwm pulse to the high-order 14 bits of cr00. select the active level with bit 1 (toc01) of the 16- bit timer output control register (toc0). this pwm pulse has a 14-bit resolution. the pulse can be converted to an analog voltage by integrating it with an external low-pass filter (lpf). the pwm pulse has a combination of the basic cycle determined by 2 8 / f and the sub-cycle determined by 2 14 / f so that the time constant of the external lpf can be shortened. count clock f can be selected with bits 4 to 6 (tcl04 to tcl06) of the timer clock select register (tcl0). pwm output enable/disable can be selected with bit 0 (toe0) of toc0. cautions 1. pwm operation mode should be selected before setting cr00. 2. write 0 to bits 0 and 1 of cr00. 3. do not select pwm operation mode for external clock input from the ti00/p00/intp0 pin. tcl06 tcl05 tcl4 201 chapter 8 16-bit timer/event counter figure 8-13. control register settings for pwm output operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) remark 0/1 : setting 0 or 1 allows another function to be used simultaneously with pwm output. see the description of the respective control registers for details. x : dont care tmc0 0 1 0 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 pwm mode crc00 crc01 crc02 crc0 0 0/1 0/1 0 0 0 0 0 cr00 set as compare register toe0 toc01 lvr0 lvs0 toc04 ospe ospt toc0 1 0/1 x x x x x 0 to0 output enabled specifies active level 202 chapter 8 16-bit timer/event counter by integrating 14-bit resolution pwm pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and d/a converter applications, etc. the analog output voltage (v an ) used for d/a conversion with the configuration shown in figure 8-14 is as follows. v an = v ref x 2 16 v ref : external switching circuit reference voltage figure 8-14. example of d/a converter configuration with pwm output capture/compare register 00 (cr00) value figure 8-15 shows an example in which pwm output is converted to an analog voltage and used in a voltage synthesizer type tv tuner. figure 8-15. tv tuner application circuit example switching circuit to0/p30 pwm signal v ref low-pass filter analog output (v an ) pd78078, 78078y to0/p30 v ss 8.2 k w 8.2 k w 100 pf 22 k w +110 v 2sc 2352 47 k w 47 k w 47 k w 0.22 f 0.22 f 0.22 f electronic tuner gnd pc574j pd78078, 78078y 203 chapter 8 16-bit timer/event counter 8.5.3 ppg output operations setting the 16-bit timer mode control register (tmc0) and capture/compare control register 0 (crc0) as shown in figure 8-16 allows operation as ppg (programmable pulse generator) output. in the ppg output operation, square waves are output from the to0/p30 pin with the pulse width and the cycle that correspond to the count values set beforehand in 16-bit capture/compare register 01 (cr01) and in 16-bit capture/ compare register 00 (cr00), respectively. figure 8-16. control register settings for ppg output operation (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) caution values in the following range should be set in cr00 and cr01. 0000h cr01 < cr00 ffffh remark x : dont care tmc0 0 0 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start on match of tm0 and cr00 crc0 0 x 0 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register cr01 set as compare register toc0 1 1 0/1 0/1 1 0 0 0 toe0 toc01 lvr0 lvs0 inversion of output on match of tm0 and cr00 toc04 ospe ospt to0 output enabled specified to0 output f/f initial value inversion of output on match of tm0 and cr01 one-shot pulse output disabled 204 chapter 8 16-bit timer/event counter 8.5.4 pulse width measurement operations it is possible to measure the pulse width of the signals input to the ti00/p00 pin and ti01/p01 pin using the bit timer register (tm0). there are two measurement methods: measuring with tm0 used in free-running mode, and measuring by restarting the timer in synchronization with the edge of the signal input to the ti00/p00 pin. (1) pulse width measurement with free-running counter and one capture register when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8- 17), and the edge specified by external interrupt mode register 0 (intm0) is input to the ti00/p00 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (intp0) is set. any of three edge specifications can be selected-rising, falling, or both edges-by means of bits 2 and 3 (ex10 and es11) of intm0. for valid edge detection, sampling is performed at the interval selected by means of the sampling clock selection register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 8-17. control register settings for pulse width measurement with free-running counter and one capture register (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. tmc0 0 0/1 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-running mode crc0 0 0/1 1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register cr01 set as capture register 205 chapter 8 16-bit timer/event counter figure 8-18. configuration diagram for pulse width measurement by free-running counter figure 8-19. timing of pulse width measurement operation by free-running counter and one capture register (with both edges specified) count clock tm0 count value ti00 pin input cr01 captured value intp0 ovf0 0000 0001 d0 d1 ffff 0000 d2 d3 d0 d1 d2 d3 (d1 ?d0) x t (10000h ?d1 + d2) x t (d3 ?d2) x t t selector f xx /2 2 f xx /2 f xx 2f xx inttm3 16-bit timer register (tm0) 16-bit capture/compare register 01 (cr01) ovf0 intp0 internal bus ti00/p00/intp00 206 chapter 8 16-bit timer/event counter (2) two pulse width measurements with free-running counter when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8- 20), it is possible to simultaneously measure the pulse widths of the two signals input to the ti00/p00 pin and the ti01/p01 pin. when the edge specified by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0) is input to the ti00/p00 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (intp0) is set. also, when the edge specified by bits 4 and 5 (es20 and es21) of intm0 is input to the ti01/p01 pin, the value of tm0 is taken into 16-bit capture/compare register 00 (cr00) and an external interrupt request signal (intp1) is set. any of three edge specifications can be selected-rising, falling, or both edges-as the valid edges for the ti00/ p00 pin and the ti01/p01 pin by means of bits 2 and 3 (es10 and es11) and bits 4 and 5 (es20 and es21) of intm0, respectively. for ti00/p00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling clock selection register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. figure 8-20. control register settings for two pulse width measurements with free-running counter (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. tmc0 0 0/1 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-running mode crc0 1 0 1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as capture register captured in cr00 on valid edge of ti01/p01 pin cr01 set as capture register 207 chapter 8 16-bit timer/event counter figure 8-21. timing of pulse width measurement operation with free-running counter (with both edges specified) count clock tm0 count value ti00 pin input cr01 captured value intp0 ti01 pin input t cr00 captured value intp1 ovf0 (d1 ?d0) x t (10000h ?d1 + d2) x t (10000h ?d1 + (d2 + 1)) x t (d3 ?d2) x t 0000 0001 d0 d1 0000 d3 d2 ffff d0 d1 d3 d2 d1 208 chapter 8 16-bit timer/event counter (3) pulse width measurement with free-running counter and two capture registers when the 16-bit timer register (tm0) is operated in free-running mode (see register settings in figure 8-22), it is possible to measure the pulse width of the signal input to the ti00/p00 pin. when the edge specified by bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0) is input to the ti00/p00 pin, the value of tm0 is taken into 16-bit capture/compare register 01 (cr01) and an external interrupt request signal (intp0) is set. also, on the inverse edge input of that of the capture operation into cr01, the value of tm0 is taken into 16-bit capture/compare register 00 (cr00). either of two edge specifications can be selectedrising or fallingas the valid edges for the ti00/p00 pin by means of bits 2 and 3 (es10 and es11) of intm0. for ti00/p00 pin valid edge detection, sampling is performed at the interval selected by means of the sampling clock selection register (scs), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short pulse width. caution if the valid edge of ti00/p00 is specified to be both rising and falling edge, capture/compare register 00 (cr00) cannot perform the capture operation. figure 8-22. control register settings for pulse width measurement with free-running counter and two capture registers (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. tmc0 0 0/1 1 0 0 0 0 0 ovf0 tmc01 tmc02 tmc03 free-running mode crc0 1 1 1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as capture register captured in cr00 on invalid edge of ti00/p00 pin cr01 set as capture register 209 chapter 8 16-bit timer/event counter figure 8-23. timing of pulse width measurement operation by free-running counter and two capture registers (with rising edge specified) count clock tm0 count value ti00 pin input cr01 captured value cr00 captured value intp0 ovf0 (d1 ?d0) x t (10000h ?d1 + d2) x t (d3 ?d2) x t d1 d3 d0 d2 d3 d2 0000 ffff d1 d0 0000 0001 t 210 chapter 8 16-bit timer/event counter (4) pulse width measurement by means of restart when input of a valid edge to the ti00/p00 pin is detected, the count value of the 16-bit timer register (tm0) is taken into 16-bit capture/compare register 01 (cr01), and then the pulse width of the signal input to the ti00/p00 pin is measured by clearing tm0 and restarting the count (see register settings in figure 8-24). the edge specification can be selected from two types, rising and falling edges, by bits 2 and 3 (es10 and es11) of the external interrupt mode register 0 (intm0). in a valid edge detection, the sampling is performed by a cycle selected by the sampling clock selection register (scs), and a capture operation is not performed before detecting valid levels twice allowing short pulse width noise to be eliminated. caution if the valid edge of ti00/p00 is specified to be both rising and falling edge, capture/compare register 00 (cr00) cannot perform the capture operation. figure 8-24. control register settings for pulse width measurement by means of restart (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with pulse width measurement. see the description of the respective control registers for details. figure 8-25. timing of pulse width measurement operation by means of restart (with rising edge specified) tmc0 0 0/1 0 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start with valid edge of ti00/p00 pin crc0 1 1 1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as capture register captured in cr00 on invalid edge of ti00/p00 pin cr01 set as capture register count clock tm0 count value ti00 pin input cr01 capture value cr00 capture value intp0 t 0000 0001 d0 0000 0001 d1 0001 0000 d2 d0 d2 d1 d1 x t d2 x t 211 chapter 8 16-bit timer/event counter 8.5.5 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti00/p00 pin with the 16-bit timer register (tm0). tm0 is incremented each time the valid edge specified with the external interrupt mode register 0 (intm0) is input. when the tm0 counted value matches the 16-bit capture/compare register 00 (cr00) value, tm0 is cleared to 0 and the interrupt request signal (inttm00) is generated. set a value other than 0000h to cr00 (1-pulse count operation cannot be performed). the rising edge, the falling edge or both edges can be selected with bits 2 and 3 (es10 and es11) of intm0. because operation is carried out only after the valid edge is detected twice by sampling at the cycle selected with the sampling clock select register (scs), noise with short pulse widths can be removed. figure 8-26. control register settings in external event counter mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) remark 0/1: setting 0 or 1 allows another function to be used simultaneously with the external event counter. see the description of the respective control registers for details. tmc0 0 0/1 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start with match of tm0 and cr00 crc0 0 0/1 0/1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register 212 chapter 8 16-bit timer/event counter figure 8-27. external event counter configuration diagram figure 8-28. external event counter operation timings (with rising edge specified) caution when reading the external event counter count value, tm0 should be read. 16-bit capture/compare register 00 (cr00) clear inttm00 intp0 16-bit timer register (tm0) 16-bit capture/compare register 01 (cr01) internal bus ti00 valid edge ovf0 ti00 pin input tm0 count value cr00 inttm0 n 0000 0001 0002 0003 0004 0005 n 1 n 0000 0001 0002 0003 213 chapter 8 16-bit timer/event counter 8.5.6 square-wave output operation 16-bit timer/event counter operates as a square wave output with any selected frequency at intervals of the count value preset to the 16-bit capture/compare register 00 (cr00). the to0/p30 pin output status is reversed at intervals of the count value preset to cr00 by setting bit 0 (toe0) and bit 1 (toc01) of the 16-bit timer output control register (toc0) to 1. this enables a square wave with any selected frequency to be output. figure 8-29. control register settings in square-wave output mode (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) tmc0 0 0/1 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start on match of tm0 and cr00 crc0 0 0/1 0/1 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register (c) 16-bit timer output control register (toc0) toc0 1 1 0/1 0/1 0 0 0 0 toe0 toc01 lvr0 ospt ospe toc04 lvs0 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value no inversion of output on match of tm0 and cr01 one-shot pulse output disabled remark 0/1: setting 0 or 1 allows another function to be used simultaneously with square-wave output. see the description of the respective control registers for details. 214 chapter 8 16-bit timer/event counter figure 8-30. square-wave output operation timing table 8-7. 16-bit timer/event count square-wave output ranges minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 x ti00 input cycle 2 16 x ti00 input cycle ti00 input edge cycle 2 x 1/f x 2 16 x 1/f x 1/f x (400 ns) (13.1 ms) (200 ns) 2 x 1/f x 2 2 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 1/f x 2 x 1/f x (400 ns) (800 ns) (13.1 ms) (26.2 ms) (200 ns) (400 ns) 2 2 x 1/f x 2 3 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 x 1/f x 2 2 x 1/f x (800 ns) (1.6 m s) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 3 x 1/f x 2 4 x 1/f x 2 18 x 1/f x 2 19 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (1.6 m s) (3.2 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 x watch timer output cycle 2 16 x watch timer output cycle watch timer output edge cycle remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. ti00 pin input tm0 count value cr00 inttm0 to0 pin output 0000 0001 0002 n 1 n 0000 0001 0002 n 1 n 0000 n 215 chapter 8 16-bit timer/event counter 8.5.7 one-shot pulse output operation it is possible to output one-shot pulses synchronized with a software trigger or an external trigger (ti00/p00 pin input). (1) one-shot pulse output using software trigger if the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16- bit timer output control register (toc0) are set as shown in figure 8-31, and 1 is set in bit 6 (ospt) of toc0 by software, a one-shot pulse is output from the to0/p30 pin. by setting 1 in ospt, the 16-bit timer/event counter is cleared and started, and output is activated by the count value set beforehand in 16-bit capture/compare register 01 (cr01). thereafter, output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (cr00). tm0 continues to operate after one-shot pulse is output. to stop tm0, 00h must be set to tmc0. caution when outputting one-shot pulse, do not set 1 in ospt. when outputting one-shot pulse again, execute after the inttm00, or interrupt match signal with cr00, is generated. figure 8-31. control register settings for one-shot pulse output operation using software trigger (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) caution values in the following range should be set in cr00 and cr01. 0000h cr01 < cr00 ffffh remark 0/1: setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. see the description of the respective control registers for details. tmc0 0 0 1 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start with match of tm0 and cr00 crc0 0 0/1 0 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register cr01 set as compare register toc0 1 1 0/1 0/1 1 1 0 0 toe0 toc01 lvr0 ospt ospe toc04 lvs0 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value inversion of output on match of tm0 and cr01 one-shot pulse output mode set 1 in case of output 216 chapter 8 16-bit timer/event counter figure 8-32. timing of one-shot pulse output operation using software trigger caution the 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to tmc01 to tmc03, respectively. count clock tm0 count value cr01 set value cr00 set value inttm01 ospt inttm00 to0 pin output 0000 0001 n n + 1 0000 n 1 n m 1 m 0000 0001 0002 n m n m n m n m set 0ch to tmc0 (tm0 count start) 217 chapter 8 16-bit timer/event counter (2) one-shot pulse output using external trigger if the 16-bit timer mode control register (tmc0), capture/compare control register 0 (crc0), and the 16- bit timer output control register (toc0) are set as shown in figure 8-33, a one-shot pulse is output from the to0/p30 pin with a ti00/p00 valid edge as an external trigger. any of three edge specifications can be selected-rising, falling, or both edges - as the valid edges for the ti00/p00 pin by means of bits 2 and 3 (es10 and es11) of external interrupt mode register 0 (intm0). when a valid edge is input to the ti00/p00 pin, the 16-bit timer/event counter is cleared and started, and output is activated by the count values set beforehand in 16-bit capture/compare register 01 (cr01). thereafter, output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (cr00). caution when outputting one-shot pulses, external trigger is ignored if generated again. figure 8-33. control register settings for one-shot pulse output operation using external trigger (a) 16-bit timer mode control register (tmc0) (b) capture/compare control register 0 (crc0) (c) 16-bit timer output control register (toc0) caution values in the following range should be set in cr00 and cr01. 0000h cr01 < cr00 ffffh remark 0/1: setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output. see the description of the respective control registers for details. tmc0 0 0 0 1 0 0 0 0 ovf0 tmc01 tmc02 tmc03 clear & start with valid edge of ti00/p00 pin crc0 0 0/1 0 0 0 0 0 0 crc00 crc01 crc02 cr00 set as compare register cr01 set as compare register toc0 1 1 0/1 0/1 1 1 0 0 toe0 toc01 lvr0 lvs0 ospt ospe toc04 to0 output enabled inversion of output on match of tm0 and cr00 specified to0 output f/f initial value inversion of output on match of tm0 and cr01 one-shot pulse output mode 218 chapter 8 16-bit timer/event counter figure 8-34. timing of one-shot pulse output operation using external trigger (with rising edge specified) caution the 16-bit timer register starts operation at the moment a value other than 0, 0, 0 (operation stop mode) is set to tmc01 to tmc03, respectively. count clock tm0 count value cr01 set value cr00 set value inttm01 ti00 pin input inttm00 to0 pin output 0000 0001 0000 n n + 1 n + 2 m 2 m 1 m m + 1 m + 2 m + 3 n m n m n m n m set 08h to tmc0 (tm0 count start) 219 chapter 8 16-bit timer/event counter 8.6 16-bit timer/event counter operating precautions (1) timer start errors an error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. this is because the 16-bit timer register (tm0) is started asynchronously with the count pulse. figure 8-35. 16-bit timer register start timing (2) 16-bit compare register setting set a value other than 0000h to the 16-bit capture/compare register 00 (cr00). thus, when using the 16-bit capture/compare register as event counter, one-pulse count operation cannot be carried out. (3) operation after compare register change during timer count operation if the value after the 16-bit capture/compare register (cr00) is changed is smaller than that of the 16-bit timer register (tm0), tm0 continues counting, overflows and then restarts counting from 0. thus, if the value (m) after cr00 change is smaller than that (n) before change, it is necessary to restart the timer after changing cr00. figure 8-36. timings after change of compare register during timer count operation remark n > x > m timer start count pulse tm0 count value 0000h 0001h 0002h 0003h 0004h count pulse cr00 captured value tm0 count value x 1 x ffffh 0000h 0001h 0002h m n 220 chapter 8 16-bit timer/event counter (4) capture register data retention timings if the valid edge of the ti00/p00 pin is input during 16-bit capture/compare register 01 (cr01) read, cr01 holds data without carrying out capture operation. however, the interrupt request flag (pif0) is set upon detection of the valid edge. figure 8-37. capture register data retention timing (5) valid edge setting set the valid edge of the ti00/p00/intp0 pin after setting bits 1 to 3 (tmc01 to tmc03) of the 16-bit timer mode control register (tmc0) to 0, 0 and 0, respectively, and then stopping timer operation. valid edge setting is carried out with bits 2 and 3 (es10 and es11) of the external interrupt mode register 0 (intm0). (6) re-trigger of one-shot pulse (a) one-shot pulse output using software when outputting one-shot pulse, do not set 1 in ospt. when outputting one-shot pulse again, execute it after the inttm00, which is the match interrupt request with cr00, is generated. (b) one-shot pulse output using external trigger when outputting one-shot pulses, external trigger is ignored if generated again. count pulse tm0 count value edge input interrupt request flag capture read signal cr01 captured value capture operation ignored xn + 1 n n + 1 n + 2 m m + 1 m + 2 221 chapter 8 16-bit timer/event counter (7) operation of ovf0 flag ofv0 flag is set to 1 in the following case. the clear & start mode on match between tm0 and cr00 is selected. cr00 is set to ffffh. when tm0 is counted up from ffffh to 0000h. figure 8-38. operation timing of ovf0 flag count pulse cr00 tm0 ovf0 inttm00 ffffh fffeh ffffh 0000h 0001h 222 [memo] 223 chapter 9 8-bit timer/event counters 1 and 2 9.1 8-bit timer/event counters 1 and 2 functions for the 8-bit timer/event counters 1 and 2, two modes are available. one is a mode for two-channel 8-bit timer/ event counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the 8-bit timer/ event counter to be used as 16-bit timer/event counter (the 16-bit timer/event counter mode). 9.1.1 8-bit timer/event counter mode the 8-bit timer/event counters 1 and 2 (tm1 and tm2) have the following functions. ? interval timer ? external event counter ? square-wave output 224 chapter 9 8-bit timer/event counters 1 and 2 (1) 8-bit interval timer interrupt requests are generated at the preset time intervals. table 9-1. 8-bit timer/event counters 1 and 2 interval times minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 x 1/f x 2 2 x 1/f x 2 9 x 1/f x 2 10 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 10 x 1/f x 2 11 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 11 x 1/f x 2 12 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 12 x 1/f x 2 13 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 13 x 1/f x 2 14 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 14 x 1/f x 2 15 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 15 x 1/f x 2 16 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. 225 chapter 9 8-bit timer/event counters 1 and 2 (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. table 9-2. 8-bit timer/event counters 1 and 2 square-wave output ranges minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 x 1/f x 2 2 x 1/f x 2 9 x 1/f x 2 10 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 10 x 1/f x 2 11 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 11 x 1/f x 2 12 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 12 x 1/f x 2 13 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 13 x 1/f x 2 14 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 14 x 1/f x 2 15 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 15 x 1/f x 2 16 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. 226 chapter 9 8-bit timer/event counters 1 and 2 9.1.2 16-bit timer/event counter mode (1) 16-bit interval timer interrupt requests can be generated at the preset time intervals. table 9-3. interval times when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counters minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 x 1/f x 2 2 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 18 x 1/f x 2 19 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (104.9 ms) (209.7 ms) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 20 x 1/f x 2 21 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (209.7 ms) (419.4 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 21 x 1/f x 2 22 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (419.4 ms) (838.9 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 22 x 1/f x 2 23 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (838.9 ms) (1.7 s) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 23 x 1/f x 2 24 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (1.7 s) (3.4 s) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 24 x 1/f x 2 25 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (3.4 s) (6.7 s) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 25 x 1/f x 2 26 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (6.7 s) (13.4 s) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 27 x 1/f x 2 28 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (26.8 s) (53.7 s) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. 227 chapter 9 8-bit timer/event counters 1 and 2 (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. table 9-4. square-wave output ranges when 8-bit timer/event counters 1 and 2 are used as 16-bit timer/event counters minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 x 1/f x 2 2 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 18 x 1/f x 2 19 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (104.9 ms) (209.7 ms) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 20 x 1/f x 2 21 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (209.7 ms) (419.4 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 21 x 1/f x 2 22 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (419.4 ms) (838.9 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 22 x 1/f x 2 23 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (838.9 ms) (1.7 s) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 23 x 1/f x 2 24 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (1.7 s) (3.4 s) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 24 x 1/f x 2 25 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (3.4 s) (6.7 s) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 25 x 1/f x 2 26 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (6.7 s) (13.4 s) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 27 x 1/f x 2 28 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (26.8 s) (53.7 s) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with at f x = 5.0 mhz. 228 chapter 9 8-bit timer/event counters 1 and 2 9.2 8-bit timer/event counters 1 and 2 configurations the 8-bit timer/event counters 1 and 2 consist of the following hardware. table 9-5. 8-bit timer/event counters 1 and 2 configurations item configuration timer register 8 bits x 2 (tm1, tm2) register compare register: 8 bits x 2 (cr10, cr20) timer output 2 (to1, to2) timer clock select register 1 (tcl1) 8-bit timer mode control register 1 (tmc1) 8-bit timer output control register (toc1) port mode register 3 (pm3) note note refer to figure 6-9 block diagram of p30 to p37 . figure 9-1. 8-bit timer/event counters 1 and 2 block diagram note refer to figures 9-2 and 9-3 for details of 8-bit timer/event counter output control circuits 1 and 2, respectively. control register internal bus 8-bit compare register (cr10) match 8-bit timer register 1 (tm1) selector clear selector selector ti1/p33 f xx /2 to f xx /2 9 f xx /2 to f xx /2 9 f xx /2 11 f xx /2 11 ti2/p34 4 4 8-bit timer mode control register tmc12 tce2 tce1 internal bus lvs2 lvr2 toc 15 toe2 lvs1 lvr1 toc 11 toe1 4 8-bit timer register 2 (tm2) 8-bit timer/ event counter output control circuit 8-bit timer output control register 8-bit timer/event counter output control selector clear match 8-bit compare register (cr20) note inttm1 to2/p32 inttm2 to1/p31 selector tcl 17 tcl 16 tcl 15 tcl 14 tcl 13 tcl 12 tcl 11 tcl 10 timer clock select register 1 note 229 chapter 9 8-bit timer/event counters 1 and 2 figure 9-2. block diagram of 8-bit timer/event counter output control circuit 1 remark the section in the broken line is an output control circuit. figure 9-3. block diagram of 8-bit timer/event counter output control circuit 2 remarks 1. the section in the broken line is an output control circuit. 2. f sck : serial clock frequency lvr1 lvs1 toc11 inttm1 r s inv q p31 output latch toe1 pm31 to1/p31 level f/f (lv1) lvr2 lvs2 toc15 inttm2 r s inv level f/f (lv2) f sck p32 output latch pm32 toe2 to2/p32 q 230 chapter 9 8-bit timer/event counters 1 and 2 (1) compare registers 10 and 20 (cr10, cr20) these are 8-bit registers to compare the value set to cr10 to the 8-bit timer register 1 (tm1) count value, and the value set to cr20 to the 8-bit timer register 2 (tm2) count value, and, if they match, generate an interrupt request (inttm1 and inttm2, respectively). cr10 and cr20 are set with an 8-bit memory manipulation instruction. they cannot be set with a 16-bit memory manipulation instruction. when the compare register is used as 8-bit timer/event counter, the 00h to ffh values can be set. when the compare register is used as 16-bit timer/event counter, the 0000h to ffffh values can be set. reset input makes cr10 and cr20 undefined. caution when using the compare register as 16-bit timer/event counter, be sure to set data after stopping timer operation. (2) 8-bit timer registers 1, 2 (tm1, tm2) these are 8-bit registers to count count pulses. when tm1 and tm2 are used in the 8-bit timer x 2-channel mode, they are read with an 8-bit memory manipulation instruction. when tm1 and tm2 are used as 16-bit timer x 1-channel mode, 16-bit timer register (tms) is read with a 16-bit memory manipulation instruction. reset input sets tm1 and tm2 to 00h. 231 chapter 9 8-bit timer/event counters 1 and 2 9.3 8-bit timer/event counters 1 and 2 control registers the following four types of registers are used to control the 8-bit timer/event counter. ? timer clock select register 1 (tcl1) ? 8-bit timer mode control register 1 (tmc1) ? 8-bit timer output control register (toc1) ? port mode register 3 (pm3) (1) timer clock select register 1 (tcl1) this register sets count clocks of 8-bit timer registers 1 and 2. tcl1 is set with an 8-bit memory manipulation instruction. reset input sets tcl1 to 00h. 232 chapter 9 8-bit timer/event counters 1 and 2 tcl13 tcl12 tcl11 tcl10 0 0 0 0 ti1 falling edge 0 0 0 1 ti1 rising edge 0110 0111 f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 1000 f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1001 f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1010 f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1011 f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1100 f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1101 f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 1110 f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 1111 f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) mcs = 1 8-bit timer register 1 count clock selection mcs = 0 other than above setting prohibited f xx /2 11 f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) tcl17 tcl16 tcl15 tcl14 tcl13 tcl12 tcl11 tcl10 76543210 symbol tcl1 ff41h 00h r/w address after reset r/w tcl17 tcl16 tcl15 tcl14 0 0 0 0 ti2 falling edge 0 0 0 1 ti2 rising edge 0110 0111 f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 1000 f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 1001 f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1010 f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1011 f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1100 f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1101 f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 1110 f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 1111 f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) mcs = 1 8-bit timer register 2 count clock selection mcs = 0 other than above setting prohibited f xx /2 11 f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) figure 9-4. timer clock select register 1 format caution stop the timer operation before rewriting tcl1 to other data. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. ti1 : 8-bit timer register 1 input pin 4. ti2 : 8-bit timer register 2 input pin 5. mcs : bit 0 of oscillation mode selection register (osms) 6. figures in parentheses apply to operation with f x = 5.0 mhz. 233 chapter 9 8-bit timer/event counters 1 and 2 (2) 8-bit timer mode control register 1 (tmc1) this register enables/stops operation of 8-bit timer registers 1 and 2 and sets the operating mode of 8-bit timer register 2. tmc1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc1 to 00h. figure 9-5. 8-bit timer mode control register 1 format cautions 1. stop the timer operation before switching the operating mode. 2. when used as 16-bit timer register, tce1 should be used for operation enable/stop. <0> <1> 2 3 4 5 6 7 symbol tce1 ff49h 00h r/w address after reset r/w tce2 tmc12 0 0 0 0 0 tmc1 tce1 8-bit timer register 1 operation control 0 operation stop (tm1 clear to 0) 1 operation enable tce2 8-bit timer register 2 operation control operation stop (tm2 clear to 0) operation enable 0 1 tmc12 operating mode selection 8-bit timer register x 2 channel mode (tm1, tm2) 16-bit timer register x 1 channel mode (tms) 0 1 234 chapter 9 8-bit timer/event counters 1 and 2 (3) 8-bit timer output control register (toc1) this register controls operation of 8-bit timer/event counter output control circuits 1 and 2. it sets/resets the r-s flip-flops (lv1 and lv2) and enables/disables inversion and 8-bit timer output of 8- bit timer registers 1 and 2. toc1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets toc1 to 00h. figure 9-6. 8-bit timer output control register format cautions 1. stop the timer operation before setting toc1. 2. after data setting, 0 can be read from lvs1, lvs2, lvr1, and lvr2. <0> 1 <2> <3> <4> 5 <6> <7> symbol toe1 toc11 lvr1 lvs1 toe2 toc15 lvr2 lvs2 toc1 ff4fh 00h r/w address after reset r/w toe1 8-bit timer/event counter 1 outptut control 0 output disable (port mode) 1 output enable toc11 8-bit timer/event counter 1 timer output f/f control 0 inverted operation disable 1 inverted operation enable lvs1 lvr1 8-bit timer/event counter 1 timer output f/f status set 0 0 unchanged 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited toe2 8-bit timer/event counter 2 output control 0 output disable (port mode) 1 output enable toc15 8-bit timer/event counter 2 timer output f/f control 0 inverted operation disable 1 inverted operation enable lvs2 lvr2 8-bit timer/event counter 2 timer output f/f status set 0 0 unchanged 0 1 timer output f/f reset (0) 1 0 timer output f/f set (1) 1 1 setting prohibited 235 chapter 9 8-bit timer/event counters 1 and 2 (4) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p31/to1 and p32/to2 pins for timer output, set pm31, pm32, and output latches of p31 and p32 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 9-7. port mode register 3 format 0 1 2 3 4 5 6 7 symbol pm30 ff23h ffh r/w address after reset r/w pm31 pm32 pm33 pm34 pm35 pm36 pm37 pm3 pm3n p3n pin input/output mode selection (n = 0 to 7) 0 output mode (output buffer on) 1 input mode (output buffer off) 236 chapter 9 8-bit timer/event counters 1 and 2 9.4 8-bit timer/event counters 1 and 2 operations 9.4.1 8-bit timer/event counter mode (1) interval timer operations the 8-bit timer/event counters 1 and 2 operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 10 and 20 (cr10 and cr20). when the count values of the 8-bit timer registers 1 and 2 (tm1 and tm2) match the values set to cr10 and cr20, counting continues with the tm1 and tm2 values cleared to 0 and the interrupt request signals (inttm1 and inttm2) are generated. count clock of the tm1 can be selected with bits 0 to 3 (tcl10 to tcl13) of the timer clock select register 1 (tcl1). count clock of the tm2 can be selected with bits 4 to 7 (tcl14 to tcl17) of the timer clock select register 1 (tcl1). for the operation in the case the value of the compare register is changed during the timer count operation, refer to 9.5 8-bit timer/event counters 1 and 2 precautions (3) . figure 9-8. interval timer operation timing remark interval time = (n + 1) x t : n = 00h to ffh count clock tm1 count value inttm1 cr10 to1 interval time interval time interval time interrupt request acknowledge interrupt request acknowledge n n n n count start clear clear t 00 01 n 00 01 n 00 01 n 237 chapter 9 8-bit timer/event counters 1 and 2 table 9-6. 8-bit timer/event counter 1 interval time minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 ti1 input cycle 2 8 x ti1 input cycle ti1 input edge cycle 0001 ti1 input cycle 2 8 x ti1 input cycle ti1 input edge cycle 2 x 1/f x 2 2 x 1/f x 2 9 x 1/f x 2 10 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 10 x 1/f x 2 11 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 11 x 1/f x 2 12 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 12 x 1/f x 2 13 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 13 x 1/f x 2 14 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 14 x 1/f x 2 15 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 15 x 1/f x 2 16 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. tcl10 to tcl13 : bits 0 to 3 of timer clock select register 1 (tcl1) 4. figures in parentheses apply to operation with f x = 5.0 mhz. 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 tcl13 tcl12 tcl11 tcl10 238 chapter 9 8-bit timer/event counters 1 and 2 table 9-7. 8-bit timer/event counter 2 interval time minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 ti2 input cycle 2 8 x ti2 input cycle ti2 input edge cycle 0001 ti2 input cycle 2 8 x ti2 input cycle ti2 input edge cycle 2 x 1/f x 2 2 x 1/f x 2 9 x 1/f x 2 10 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 10 x 1/f x 2 11 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 11 x 1/f x 2 12 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 12 x 1/f x 2 13 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 13 x 1/f x 2 14 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 14 x 1/f x 2 15 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 15 x 1/f x 2 16 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. tcl14 to tcl17 : bits 4 to 7 timer clock select register 1 (tcl1) 4. figures in parentheses apply to operation with f x = 5.0 mhz. 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 tcl17 tcl16 tcl15 tcl14 239 chapter 9 8-bit timer/event counters 1 and 2 (2) external event counter operation the external event counter counts the number of external clock pulses to be input to the ti1/p33 and ti2/ p34 pins with 8-bit timer registers 1 and 2 (tm1 and tm2). tm1 and tm2 are incremented each time the valid edge specified with the timer clock select register (tcl1) is input. either the rising or falling edge can be selected. when the tm1 and tm2 counted values match the values of 8-bit compare registers (cr10 and cr20), tm1 and tm2 are cleared to 0 and the interrupt request signals (inttm1 and inttm2) are generated. figure 9-9. external event counter operation timings (with rising edge specified) remark n = 00h to ffh ti1 pin input tm1 count value inttm1 cr10 00 01 02 03 04 05 n 1 n 00 01 02 03 n 240 chapter 9 8-bit timer/event counters 1 and 2 (3) square-wave output operation 8-bit timer/event counters 1 and 2 operate as a square wave outputs with any selected frequency at intervals of the value preset to 8-bit compare registers 10 and 20 (cr10 and cr20). the to1/p31 or to2/p32 pin output status is reversed at intervals of the count value preset to cr10 or cr20 by setting bit 0 (toe1) or bit 4 (toe2) of the 8-bit timer output control register (toc1) to 1. this enables a square wave with any selected frequency to be output. table 9-8. 8-bit timer/event counters 1 and 2 square-wave output ranges minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 x 1/f x 2 2 x 1/f x 2 9 x 1/f x 2 10 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 10 x 1/f x 2 11 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 11 x 1/f x 2 12 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 12 x 1/f x 2 13 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 13 x 1/f x 2 14 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 14 x 1/f x 2 15 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 15 x 1/f x 2 16 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. 241 chapter 9 8-bit timer/event counters 1 and 2 figure 9-10. timing of square wave output operation note the initial value of the to1 output can be set by bits 2 and 3 (lvs1 and lvr1) of the 8-bit timer output control register (toc1). count clock tm1 count value 01 02 00 n? n 00 01 02 n? n 00 count start cr10 n n to1 note 242 chapter 9 8-bit timer/event counters 1 and 2 count clock tms (tm1, tm2) count value cr10, cr20 inttm2 to2 interval time interval time interval time interrupt request acknowledge interrupt request acknowledge nn nn count start clear clear 0000 0001 n 0000 0001 n 0000 0001 n t 9.4.2 16-bit timer/event counter mode when bit 2 (tmc12) of the 8-bit timer mode control register (tmc1) is set to 1, the 16-bit timer/event counter mode is set. in this mode, the count clock is selected by using bits 0 through 3 (tcl10 through tcl13) of the timer clock select register (tcl1), and the overflow signal of the 8-bit timer/event counter 1 (tm1) is used as the count clock for the 8-bit timer/event counter 2 (tm2). the counting operation is enabled or disabled in this mode by using bit 0 (tce1) of tmc1. (1) operation as interval timer the 16-bit timer/event counter operates as an interval timer that repeatedly generates an interrupt request at intervals of the count values set in advance to the 2 channels of the 8-bit compare registers (cr10 and cr20). when setting a count value, assign the value of the high-order 8 bits to cr20 and the value of the low-order 8 bits to cr10. for the count values that can be set (interval time), refer to table 9-9 . when the value of 8-bit timer register 1 (tm1) coincides with the value of cr10 and the value of 8-bit timer register 2 (tm1) coincides with the value of cr20, the values of tm1 and tm2 are cleared to 0, and at the same time, an interrupt request signal (inttm2) is generated. for the operation timing of the interval timer, refer to figure 9-11 . select the count clock by using bits 0 through 3 (tcl10 through tcl13) of the timer clock select register 1 (tcl1). the overflow signal of tm1 is used as the count clock for tm2. figure 9-11. interval timer operation timing remark interval time = (n + 1) x t : n = 0000h to ffffh caution even if the 16-bit timer/event counter mode is used, when the tm1 count value matches the cr10 value, interrupt request (inttm1) is generated and the f/f of 8-bit timer/event counter output control circuit 1 is inverted. thus, when using 8-bit timer/event counter as 16-bit interval timer, set the inttm1 mask flag tmmk1 to 1 to disable inttm1 acknowledgment. when reading the 16-bit timer (tms) count value, use the 16-bit memory manipulation instruction. 243 chapter 9 8-bit timer/event counters 1 and 2 table 9-9. interval times when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 ti1 input cycle 2 8 x ti1 input cycle ti1 input edge cycle 0001 ti1 input cycle 2 8 x ti1 input cycle ti1 input edge cycle 2 x 1/f x 2 2 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 18 x 1/f x 2 19 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (104.9 ms) (209.7 ms) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 20 x 1/f x 2 21 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (209.7 ms) (419.4 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 21 x 1/f x 2 22 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (419.4 ms) (838.9 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 22 x 1/f x 2 23 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (838.9 ms) (1.7 s) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 23 x 1/f x 2 24 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (1.7 s) (3.4 s) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 24 x 1/f x 2 25 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (3.4 s) (6.7 s) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 25 x 1/f x 2 26 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (6.7 s) (13.4 s) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 27 x 1/f x 2 28 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (26.8 s) (53.7 s) (409.6 m s) (819.2 m s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. tcl10 to tcl13 : bits 0 to 3 of timer clock select register 1 (tcl1) 4. figures in parentheses apply to operation with at f x = 5.0 mhz. 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 tcl13 tcl12 tcl11 tcl10 244 chapter 9 8-bit timer/event counters 1 and 2 (2) external event counter operations the external event counter counts the number of external clock pulses to be input to the ti1/p33 pin with 2-channel 8-bit timer registers 1 and 2 (tm1 and tm2). tm1 and tm2 are incremented each time the valid edge specified with the timer clock select register 1 (tcl1) is input. either the rising or falling edge can be selected. when the tm1 and tm2 counted values match the values of 8-bit compare registers 10 and 20 (cr10 and cr20), tm1 and tm2 are cleared to 0 and the interrupt request signal (inttm2) is generated. figure 9-12. external event counter operation timings (with rising edge specified) caution even if the 16-bit timer/event counter mode is used, when the tm1 count value matches the cr10 value, interrupt request (inttm1) is generated and the f/f of 8-bit timer/event counter output control circuit 1 is inverted. thus, when using 8-bit timer/event counter as 16-bit interval timer, set the inttm1 mask flag tmmk1 to 1 to disable inttm1 acknowledgment. when reading the 16-bit timer register (tms) count value, use the 16-bit memory manipulation instruction. ti1 pin input tm1, tm2 count value cr10, cr20 inttm2 0000 0001 0002 0003 0004 0005 n ?1 n 0000 0001 0002 0003 n 245 chapter 9 8-bit timer/event counters 1 and 2 (3) square-wave output operation the 8-bit timer/event counters 1 and 2 operate as square wave outputs with any selected frequency at intervals of the value preset to 8-bit compare registers (cr10 and cr20). to set the count value, set the values of the higher 8 bits to cr20 and set the values of the lower 8 bits to cr10. the to2/p32 pin output status is reversed at intervals of the count value preset to cr10 and cr20 by setting bit 4 (toe2) of the 8-bit timer output control register (toc1) to 1. this enables a square wave with any selected frequency to be output. table 9-10. square-wave output ranges when 2-channel 8-bit timer/event counters (tm1 and tm2) are used as 16-bit timer/event counter minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 2 x 1/f x 2 2 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (26.2 ms) (52.4 ms) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 18 x 1/f x 2 19 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (52.4 ms) (104.9 ms) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (104.9 ms) (209.7 ms) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 20 x 1/f x 2 21 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (209.7 ms) (419.4 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 21 x 1/f x 2 22 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (419.4 ms) (838.9 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 22 x 1/f x 2 23 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (838.9 ms) (1.7 s) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 23 x 1/f x 2 24 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (1.7 s) (3.4 s) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 24 x 1/f x 2 25 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (3.4 s) (6.7 s) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 25 x 1/f x 2 26 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (6.7 s) (13.4 s) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 27 x 1/f x 2 28 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (26.8 s) (53.7 s) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. 246 chapter 9 8-bit timer/event counters 1 and 2 9.5 8-bit timer/event counters 1 and 2 precautions (1) timer start errors an error with a maximum of one clock may occur concerning the time required for a match signal to be gener- ated after timer start. this is because 8-bit timer registers 1 and 2 (tm1 and tm2) are started asynchronously with the count pulse. figure 9-13. 8-bit timer registers 1 and 2 start timing (2) 8-bit compare register 10 and 20 setting the 8-bit compare registers 10 and 20 (cr10 and cr20) can be set to 00h. thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be carried out. when the 8-bit compare register is used as 16-bit timer/event counter, write data to cr10 and cr20 after setting bit 0 (tce1) of the 8-bit timer mode control register 1 to 0 and stopping timer operation. figure 9-14. external event counter operation timing count pulse tm1, tm2 count value 00h 01h 02h 03h 04h timer start ti1, ti2, input cr10, cr20 tm1, tm2 count value to1, to2 interrupt request flag 00h 00h 00h 00h 00h 247 chapter 9 8-bit timer/event counters 1 and 2 (3) operation after compare register change during timer count operation if the values after the 8-bit compare registers 10 and 20 (cr10 and cr20) are changed are smaller than those of 8-bit timer registers (tm1 and tm2), tm1 and tm2 continue counting, overflow and then restart counting from 0. thus, if the value (m) after cr10 and cr20 change is smaller than value (n) before the change, it is necessary to restart the timer after changing cr10 and cr20. figure 9-15. timing after compare register change during timer count operation remark n > x > m count pulse cr10, cr20 tm1, tm2 count value x ?1 x ffh 00h 01h 02h m n 248 [memo] 249 chapter 10 8-bit timer/event counters 5 and 6 10.1 8-bit timer/event counters 5 and 6 functions the 8-bit timer event counters 5 and 6 (tm5, tm6) have the following functions. ? interval timer ? external event counter ? square-wave output ? pwm output 250 chapter 10 8-bit timer/event counters 5 and 6 (1) 8-bit interval timer interrupt requests are generated at the preset time intervals. table 10-1. 8-bit timer/event counters 5 and 6 interval times minimum interval width maximum interval width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 1/f x 2 8 x 1/f x 1/f x (200 ns) (51.2 m s) (200 ns) 1/f x 2 x 1/f x 2 8 x 1/f x 2 9 x 1/f x 1/f x 2 x 1/f x (200 ns) (400 ns) (51.2 m s) (102.4 m s) (200 ns) (400 ns) 2 x 1/f x 2 2 x 1/f x 2 9 x 1/f x 2 10 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 10 x 1/f x 2 11 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 11 x 1/f x 2 12 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 12 x 1/f x 2 13 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 13 x 1/f x 2 14 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 14 x 1/f x 2 15 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 15 x 1/f x 2 16 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. 251 chapter 10 8-bit timer/event counters 5 and 6 (2) external event counter the number of pulses of an externally input signal can be measured. (3) square-wave output a square wave with any selected frequency can be output. table 10-2. 8-bit timer/event counters 5 and 6 square-wave output ranges minimum pulse width maximum pulse width resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 1/f x 2 8 x 1/f x 1/f x (200 ns) (51.2 m s) (200 ns) 1/f x 2 x 1/f x 2 8 x 1/f x 2 9 x 1/f x 1/f x 2 x 1/f x (200 ns) (400 ns) (51.2 m s) (102.4 m s) (200 ns) (400 ns) 2 x 1/f x 2 2 x 1/f x 2 9 x 1/f x 2 10 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 10 x 1/f x 2 11 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 11 x 1/f x 2 12 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 12 x 1/f x 2 13 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 13 x 1/f x 2 14 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 14 x 1/f x 2 15 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 15 x 1/f x 2 16 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. (4) pwm output tm5 and tm6 can generate 8-bit resolution pwm output. 252 chapter 10 8-bit timer/event counters 5 and 6 10.2 8-bit timer/event counters 5 and 6 configurations the 8-bit timer/event counters 5 and 6 consist of the following hardware. table 10-3. 8-bit timer/event counters 5 and 6 configurations item configuration timer register 8 bits x 2 (tm5, tm6) register compare register: 8 bits x 2 (cr50, cr60) timer output 2 (to5, to6) timer clock select register 5 and 6 (tcl5, tcl6) control register 8-bit timer mode control registers 5 and 6 (tmc5, tmc6) port mode register 10 (pm10) note note refer to figure 6-20 block diagram of p100 and p101 . figure 10-1. 8-bit timer/event counters 5 and 6 block diagram note refer to figure 10-2 for details of configurations of 8-bit timer/event counters 5 and 6 output control circuits. remark n = 5, 6 ti5/p100/to5 ti6/p101/to6 internal bus 8-bit compare register (crn0) match 8-bit timer register n (tmn) 4 selector 2 clear 6 ovf internal bus tcl n3 tcl n2 tcl n1 tcl n0 timer clock select register n output control note 8-bit timer mode control register n inttmn to5/p100/ti5, to6/p101/ti6 tmc n6 lvs n lvr n tmc n1 toe n tce n f xx -f xx /2 10 f xx /2 12 selector 253 chapter 10 8-bit timer/event counters 5 and 6 figure 10-2. block diagram of 8-bit timer/event counters 5 and 6 output control circuit remarks 1. the section in the broken line is an output control circuit. 2. n = 5, 6 (1) compare register 50 and 60 (cr50, 60) these 8-bit registers compare the value set to cr50 to 8-bit timer register 5 (tm5) count value, and the value set to cr60 to the 8-bit timer register 6 (tm6) count value, and, if they match, generate interrupts request (inttm5 and inttm6, respectively). cr50 and cr60 are set with an 8-bit memory manipulation instruction. they cannot be set with a 16-bit memory manipulation instruction. the 00h to ffh values can be set. reset input sets cr50 and cr60 values to 00h. caution to use pwm mode, set crn0 value before setting tmcn (n = 5, 6) to pwm mode. (2) 8-bit timer registers 5 and 6 (tm5, tm6) these 8-bit registers count count pulses. tm5 and tm6 are read with an 8-bit memory manipulation instruction. reset input sets tm5 and tm6 to 00h. reset lvrn lvsn tmcn1 tmcn6 ovfn inttmn tcen inttmn r s q pwm output circuit timer output f/f2 level f/f r s inv q tmcn1 tmcn6 selector p100, p101 output latch pm100, pm101 to5/p100/ti5, to6/p101/ti6 toen 254 chapter 10 8-bit timer/event counters 5 and 6 10.3 8-bit timer/event counters 5 and 6 control registers the following three types of registers are used to control the 8-bit timer/event counters 5 and 6. ? timer clock select register 5 and 6 (tcl5, tcl6) ? 8-bit timer mode control registers 5 and 6 (tmc5, tmc6) ? port mode register 10 (pm10) (1) timer clock select register 5 (tcl5) this register sets count clocks of 8-bit timer register 5. tcl5 is set with an 8-bit memory manipulation instruction. reset input sets tcl5 to 00h. figure 10-3. timer clock select register 5 format note when clock is input from the external, timer output (pwm output) cannot be used. caution when rewriting tcl5 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. ti5 : 8-bit timer register 5 input pin 4. mcs : bit 0 of oscillation mode selection register (osms) 5. figures in parentheses apply to operation with f x = 5.0 mhz. 0 0 0 0 tcl53 tcl52 tcl51 tcl50 76543210 symbol tcl5 tcl53 tcl52 tcl51 tcl50 0 0 0 0 ti5 falling edge note 0 0 0 1 ti5 rising edge note 0100 f xx f x (setting prohibited) f x /2 (2.5 mhz) 0101 f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 0110 f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 0111 f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1000 f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1001 f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1010 f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1011 f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 1100 f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 1101 f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 1110 f x /2 11 1111f xx /2 11 f x /2 11 (2.4 khz) (1.2 khz) mcs = 1 8-bit timer register 5 count clock selection mcs = 0 other than above setting prohibited ff52h 00h r/w address after reset r/w 2f xx (5.0 mhz) f x (5.0 mhz) 255 chapter 10 8-bit timer/event counters 5 and 6 (2) timer clock select register 6 (tcl6) this register sets count clocks of 8-bit timer register 6. tcl6 is set with an 8-bit memory manipulation instruction. reset input sets tcl6 to 00h. figure 10-4. timer clock select register 6 format note when clock is input from the external, timer output (pwm output) cannot be used. caution when rewriting tcl6 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. ti6 : 8-bit timer register 6 input pin 4. mcs : bit 0 of oscillation mode selection register (osms) 5. figures in parentheses apply to operation with f x = 5.0 mhz. 0 0 0 0 tcl63 tcl62 tcl61 tcl60 76543210 symbol tcl6 tcl63 tcl62 tcl61 tcl60 0 0 0 0 ti6 falling edge note 0 0 0 1 ti6 rising edge note 0100 f xx f x (setting prohibited) f x /2 (2.5 mhz) 0101 f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 0110 f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 0111 f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 1000 f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 1001 f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 1010 f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 1011 f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 1100 f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 1101 f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 1110 f x /2 11 1111f xx /2 11 f x /2 11 (2.4 khz) (1.2 khz) mcs = 1 8-bit timer register 5 count clock selection mcs = 0 other than above setting prohibited ff56h 00h r/w address after reset r/w 2f xx (5.0 mhz) f x (5.0 mhz) 256 chapter 10 8-bit timer/event counters 5 and 6 (3) 8-bit timer mode control register 5 (tmc5) this register enables/stops operation of 8-bit timer register 5, sets the operating mode of 8-bit timer register 5 and controls operation of 8-bit timer/event counter 5 output control circuit. it sets r-s flip-flop (timer output f/f 1,2) setting/resetting, the active level in pwm mode, inversion enabling/ disabling in modes other than pwm mode and 8-bit timer/event counter 5 timer output enabling/disabling. tmc5 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc5 to 00h. figure 10-5. 8-bit timer output control register format cautions 1. timer operation must be stopped before setting tmc5. 2. if lvs5 and lvr5 are read after data are set, they will be 0. 3. set bits 4 and 5 to 0. tce5 tmc56 0 0 lvs5 lvr5 tmc51 toe5 <7> 6 5 4 <3> <2> 1 <0> symbol tmc5 ff53h 00h r/w address after reset r/w toe5 8-bit timer/event counter 5 output control 0 output disabled (port mode) 1 output enabled tmc51 0 active high 1 active low in pwm mode in other mode active level selection timer output f/f1 control inversion operation disabled inversion operation enabled lvs5 lvr5 00 01 10 11 8-bit timer/event counter 5 timer output f/f1 status setting no change timer output f/f1 reset (0) timer output f/f1 set (1) setting prohibited tmc56 8-bit timer/event counter 5 operating mode selection 0 clear & start mode on match of tm5 and cr50 1 pwm mode (free-running) tce5 8-bit timer register 5 operation control 0 operation stop (tm5 clear to 0) 1 operation enable 257 chapter 10 8-bit timer/event counters 5 and 6 (4) 8-bit timer mode control register 6 (tmc6) this register enables/stops operation of 8-bit timer register 6, sets the operating mode of 8-bit timer register 6 and controls operation of 8-bit timer/event counter 6 output control circuit. it sets r-s flip-flop (timer output f/f 1,2) setting/resetting, active level in pwm mode, inversion enabling/ disabling in modes other than pwm mode and 8-bit timer/event counter 6 timer output enabling/disabling. tmc6 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc6 to 00h. figure 10-6. 8-bit timer output control register 6 format cautions 1. timer operation must be stopped before setting tmc6. 2. if lvs6 and lvr6 are read after data are set, they will be 0. 3. set bits 4 and 5 to 0. tce6 tmc66 0 0 lvs6 lvr6 tmc61 toe6 <7> 6 5 4 <3> <2> 1 <0> symbol tmc6 ff57h 00h r/w address after reset r/w toe6 8-bit timer/event counter 6 output control 0 output disabled (port mode) 6 output enabled tmc61 0 active high 1 active low in pwm mode in other mode active level selection timer output f/f1 control inversion operation disabled inversion operation enabled lvs6 lvr6 00 01 10 11 8-bit timer/event counter 6 timer output f/f1 status setting no change timer output f/f1 reset (0) timer output f/f1 set (1) setting prohibited tmc66 8-bit timer/event counter 6 operating mode selection 0 clear & start mode on match of tm6 and cr60 1 pwm mode (free-running) tce6 8-bit timer register 6 operation control 0 operation stop (tm6 clear to 0) 1 operation enable 258 chapter 10 8-bit timer/event counters 5 and 6 (5) port mode register 10 (pm10) this register sets port 10 input/output in 1-bit units. when using the p100/ti5/to5 and p101/ti6/to6 pins for timer output, set pm100, pm101 and output latches of p100 and p101 to 0. pm10 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm10 to ffh. figure 10-7. port mode register 10 format 1 7 1 6 11 4 pm103 3210 ff2ah address pm10 symbol pm102 pm101 pm100 5 ffh after reset r/w r/w pm10n 0 1 p10n pin input/output mode selection (n = 0 to 3) output mode (output buffer on) input mode (output buffer off) 259 chapter 10 8-bit timer/event counters 5 and 6 10.4 8-bit timer/event counters 5 and 6 operations 10.4.1 interval timer operations setting the 8-bit timer mode control registers (tmc5 and tmc6) as shown in figure 10-8 allows operation as an interval timer. interrupt requests are generated repeatedly using the count value preset in 8-bit compare registers (cr50 and cr60) as the interval. when the count value of the 8-bit timer register 5 or 6 (tm5, tm6) matches the value set to cr50 or cr60, counting continues with the tm5 or tm6 value cleared to 0 and the interrupt request signal (inttm5, inttm6) is generated. count clock of the 8-bit timer register 5 (tm5) can be selected with the timer clock select register 5 (tcl5) and count clock of the 8 bit timer register 6 (tm6) can be selected with the timer clock select register 6 (tcl6). for the operation in the case the value of the compare register is changed during the timer count operation, refer to 10.5 8-bit timer/event counters 5 and 6 precautions (3) . figure 10-8. 8-bit timer mode control register settings for interval timer operation remarks 1. 0/1 : setting 0 or 1 allows another function to be used simultaneously with the interval timer. see 10.3 (3), (4) for details. 2. n = 5, 6 figure 10-9. interval timer operation timings remarks 1. interval time = (n + 1) x t : n = 00h to ffh 2. n = 5, 6 1 tcen 0 tmcn6 0 0 0/1 lvsn lvrn tmcn1 toen tmcn 0/1 0/1 0/1 clear and start on match of tmn and crn0 tmn operation enable t 00 01 n 00 01 n 00 01 n n n n n clear clear count start interrupt request acknowledge interrupt request acknowledge interval time interval time interval time count clock tmn count value crn0 tcen inttmn ton 260 chapter 10 8-bit timer/event counters 5 and 6 table 10-4. 8-bit timer/event counters 5 and 6 interval times minimum interval time maximum interval time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 0000 tin input cycle 2 8 x tin input cycle tin input edge input cycle 0001 tin input cycle 2 8 x tin input cycle tin input edge input cycle (setting prohibited) 1/f x (setting prohibited) 2 8 x 1/f x (setting prohibited) 2 x 1/f x (200 ns) (51.2 m s) (200 ns) 1/f x 2 x 1/f x 2 8 x 1/f x 2 9 x 1/f x 1/f x 2 x 1/f x (200 ns) (400 ns) (51.2 m s) (102.4 m s) (200 ns) (400 ns) 2 x 1/f x 2 2 x 1/f x 2 9 x 1/f x 2 10 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 10 x 1/f x 2 11 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 11 x 1/f x 2 12 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 12 x 1/f x 2 13 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 13 x 1/f x 2 14 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 14 x 1/f x 2 15 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 15 x 1/f x 2 16 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) other than above setting prohibited remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. tcln0 to tcln3 : bits 0 to 3 of timer clock select register n (tcln) 4. figures in parentheses apply to operation with f x = 5.0 mhz. 5. n = 5, 6 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 tcln3 tcln2 tcln1 tcln0 261 chapter 10 8-bit timer/event counters 5 and 6 10.4.2 external event counter operation the external event counter counts the number of external clock pulses to be input to the ti5/p100/to5 and ti6/ p101/to6 pins with 8-bit timer registers 5 and 6 (tm5 and tm6). tm5 and tm6 are incremented each time the valid edge specified with timer clock select registers 5 and 6 (tcl5 and tcl6) is input. either rising or falling edge can be selected. when the tm5 and tm6 counted values match the values of 8-bit compare registers (cr50 and cr60), tm5 and tm6 are cleared to 0 and the interrupt request signals (inttm5 and inttm6) are generated. figure 10-10. 8-bit timer mode control register setting for external event counter operation remarks 1. n = 5, 6 2. x : dont care figure 10-11. external event counter operation timings (with rising edge specified) remarks 1. n = 00h to ffh 2. n = 5, 6 1 tcen 0 tmcn6 00x lvsn lvrn tmcn1 toen tmcn xx0 ton output disable clear & start mode on match of tmn and crn0 tmn operation enable 00 01 13 n count clock tmn count value crn0 tcen inttmn 05 n 1 00 02 03 01 02 04 n 262 chapter 10 8-bit timer/event counters 5 and 6 10.4.3 square-wave output a square wave with any selected frequency is output at intervals of the value preset to 8-bit compare registers (cr50 and cr60). the to5/p100/ti5 or to6/p101/ti6 pin output status is reversed at intervals of the count value preset to cr50 or cr60 by setting bit 1 (tmc51) and bit 0 (toe5) of the 8-bit timer output control register 5 (tmc5), or bit 1 (tmc61) and bit 0 (toe1) of the 8-bit timer mode control register 6 (tmc6) to 1. this enables a square wave of any selected frequency to be output. figure 10-12. 8-bit timer mode control register settings for square-wave output operation caution when ti5/p100/to5 or ti6/p101/to6 pin is used as the timer output, set port mode register (pm100 or pm101) and output latch (p100 or p101) to 0. remark n = 5, 6 figure 10-13. timing of square wave output operation note the initial value of the ton output can be set by bits 2 and 3 (lvsn and lvrn) of the 8-bit timer output control register n (tocn). remark n = 5, 6 1 tcen 0 tmcn6 0 0 0/1 lvsn lvrn tmcn1 toen tmcn 0/1 1 1 ton output enable inversion of output on match of tmn and crn0 specifies to0 output f/f1 initial value clear and start mode on match of tmn and crn0 tmn operation enable count clock tmn count value 01 02 00 n? n 00 01 02 n? n 00 count start crn0 n n ton note 263 chapter 10 8-bit timer/event counters 5 and 6 table 10-5. 8-bit timer/event counters 5 and 6 square-wave output ranges minimum pulse time maximum pulse time resolution mcs = 1 mcs = 0 mcs = 1 mcs = 0 mcs = 1 mcs = 0 1/f x 2 8 x 1/f x 1/f x (200 ns) (51.2 m s) (200 ns) 1/f x 2 x 1/f x 2 8 x 1/f x 2 9 x 1/f x 1/f x 2 x 1/f x (200 ns) (400 ns) (51.2 m s) (102.4 m s) (200 ns) (400 ns) 2 x 1/f x 2 2 x 1/f x 2 9 x 1/f x 2 10 x 1/f x 2 x 1/f x 2 2 x 1/f x (400 ns) (800 ns) (102.4 m s) (204.8 m s) (400 ns) (800 ns) 2 2 x 1/f x 2 3 x 1/f x 2 10 x 1/f x 2 11 x 1/f x 2 2 x 1/f x 2 3 x 1/f x (800 ns) (1.6 m s) (204.8 m s) (409.6 m s) (800 ns) (1.6 m s) 2 3 x 1/f x 2 4 x 1/f x 2 11 x 1/f x 2 12 x 1/f x 2 3 x 1/f x 2 4 x 1/f x (1.6 m s) (3.2 m s) (409.6 m s) (819.2 m s) (1.6 m s) (3.2 m s) 2 4 x 1/f x 2 5 x 1/f x 2 12 x 1/f x 2 13 x 1/f x 2 4 x 1/f x 2 5 x 1/f x (3.2 m s) (6.4 m s) (819.2 m s) (1.64 ms) (3.2 m s) (6.4 m s) 2 5 x 1/f x 2 6 x 1/f x 2 13 x 1/f x 2 14 x 1/f x 2 5 x 1/f x 2 6 x 1/f x (6.4 m s) (12.8 m s) (1.64 ms) (3.28 ms) (6.4 m s) (12.8 m s) 2 6 x 1/f x 2 7 x 1/f x 2 14 x 1/f x 2 15 x 1/f x 2 6 x 1/f x 2 7 x 1/f x (12.8 m s) (25.6 m s) (3.28 ms) (6.55 ms) (12.8 m s) (25.6 m s) 2 7 x 1/f x 2 8 x 1/f x 2 15 x 1/f x 2 16 x 1/f x 2 7 x 1/f x 2 8 x 1/f x (25.6 m s) (51.2 m s) (6.55 ms) (13.1 ms) (25.6 m s) (51.2 m s) 2 8 x 1/f x 2 9 x 1/f x 2 16 x 1/f x 2 17 x 1/f x 2 8 x 1/f x 2 9 x 1/f x (51.2 m s) (102.4 m s) (13.1 ms) (26.2 ms) (51.2 m s) (102.4 m s) 2 9 x 1/f x 2 10 x 1/f x 2 17 x 1/f x 2 18 x 1/f x 2 9 x 1/f x 2 10 x 1/f x (102.4 m s) (204.8 m s) (26.2 ms) (52.4 ms) (102.4 m s) (204.8 m s) 2 11 x 1/f x 2 12 x 1/f x 2 19 x 1/f x 2 20 x 1/f x 2 11 x 1/f x 2 12 x 1/f x (409.6 m s) (819.2 m s) (104.9 ms) (209.7 ms) (409.6 m s) (819.2 m s) remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) 3. figures in parentheses apply to operation with f x = 5.0 mhz. 4. n = 5, 6 264 chapter 10 8-bit timer/event counters 5 and 6 10.4.4 pwm output operations setting the 8-bit timer mode control registers (tmc5 and tmc6) as shown in figure 10-14 allows operation as pwm output. pulses with the duty rate determined by the values preset in 8-bit compare registers (cr50 and cr60) output from the to5/p100/ti5 or to6/p101/ti6 pin. select the active level of pwm pulse with bit 1 of the 8-bit timer mode control register 5 (tmc5) or bit 1 of the 8-bit timer mode control register 6 (tmc6). this pwm pulse has an 8-bit resolution. the pulse can be converted into an analog voltage by integrating it with an external low-pass filter (lpf). count clock of the 8-bit timer register 5 (tm5) can be selected with the timer clock select register 5 (tcl5) and count clock of the 8-bit timer register 6 (tm6) can be selected with the timer clock select register 6 (tcl6). pwm output enable/disable can be selected with bit 0 (toe5) of tmc5 or bit 0 (toe6) of tmc6. figure 10-14. 8-bit timer control register settings for pwm output operation remarks 1. n = 5, 6 2. x : dont care 1 tcen 1 tmcn6 00x lvsn lvrn tmcn1 toen tmcn x 0/1 1 ton output enable sets active level pwm mode tmn operation enable 265 chapter 10 8-bit timer/event counters 5 and 6 figure 10-15. pwm output operation timing (active high setting) remark n = 5, 6 figure 10-16. pwm output operation timings (crn0 = 00h, active high setting) remark n = 5, 6 count clock tmn count value crn0 tcen inttmn ton 01 02 ff 00 01 02 n n + 1 n + 2 n + 3 00 ovfn mn n 00 inactive level crn0 changing active level inactive level inactive level (m n) count clock tmn count value crn0 tcen inttmn ton 01 02 ff 00 01 02 ff 00 01 02 00 ovfn m00 00 00 inactive level crn0 changing (m 00) inactive level 266 chapter 10 8-bit timer/event counters 5 and 6 figure 10-17. pwm output operation timings (crn0 = ffh, active high setting) remark n = 5, 6 figure 10-18. pwm output operation timings (crn0 changing, active high setting) remark n = 5, 6 caution if crn0 is changed during tmn operation, the value changed is not reflected until tmn overflows. count clock tmn count value crn0 tcen inttmn ton 01 02 ff 00 01 02 ff 00 01 02 00 ovfn ff ff ff 00 inactive level inactive level active level inactive level active level count clock tmn count value crn0 tcen inttmn ton ovfn active level inactive level 00 ff n + 2 n + 1 n 02 01 00 ff 01 02 m + 2 m + 1 m m + 3 00 active level inactive level crn0 changing n n mm (n m) 267 chapter 10 8-bit timer/event counters 5 and 6 10.5 8-bit timer/event counters 5 and 6 precautions (1) timer start errors an error with a maximum of one clock might occur concerning the time required for a match signal to be generated after the timer starts. this is because 8-bit timer registers 5 and 6 are started asynchronously with the count pulse. figure 10-19. 8-bit timer registers 5 and 6 start timings (2) compare registers 50 and 60 sets the 8-bit compare registers (cr50 and cr60) can be set to 00h. thus, when an 8-bit compare register is used as an event counter, one-pulse count operation can be carried out. figure 10-20. external event counter operation timings count pulse tm5, tm6 count value 00h timer start 01h 02h 03h 04h ti5, ti6 input cr50, cr60 00h tm5, tm6 count value 00h 00h 00h 00h to5, to6 interrupt request flag 268 chapter 10 8-bit timer/event counters 5 and 6 count pulse cr50, cr60 n x x ?1 ffh 00h 01h m 02h tm5, tm6 count value (3) operation after compare register change during timer count operation if the values after the 8-bit compare registers (cr50 and cr60) are changed are smaller than those of 8- bit timer registers (tm5 and tm6), tm5 and tm6 continue counting, overflow and then restarts counting from 0. thus, if the value (m) after cr50 and cr60 change is smaller than that (n) before change it is necessary to restart the timer after changing cr50 and cr60. figure 10-21. timings after compare register change during timer count operation remark n > x > m 269 chapter 11 watch timer 11.1 watch timer functions the watch timer has the following functions. ? watch timer ? interval timer the watch timer and the interval timer can be used simultaneously. (1) watch timer when the 32.768-khz subsystem clock is used, a flag (wtif) is set at 0.5-second or 0.25-second intervals. when the 4.19-mhz (standard: 4.194304 mhz) main system clock is used, a flag (wtif) is set at 0.5-second or 0.25-second intervals. caution 0.5-second intervals cannot be generated with the 5.0-mhz main system clock. you should switch to the 32.768 khz subsystem clock to generate 0.5-second intervals. (2) interval timer interrupt requests (inttm3) are generated at the preset time interval. table 11-1. interval timer interval time when operated at when operated at when operated at f xx = 5.0 mhz f xx = 4.19 mhz f xt = 32.768 khz 2 4 x 1/f w 410 m s 488 m s 488 m s 2 5 x 1/f w 819 m s 977 m s 977 m s 2 6 x 1/f w 1.64 ms 1.95 ms 1.95 ms 2 7 x 1/f w 3.28 ms 3.91 ms 3.91 ms 2 8 x 1/f w 6.55 ms 7.81 ms 7.81 ms 2 9 x 1/f w 13.1 ms 15.6 ms 15.6 ms f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (f xx /2 7 or f xt ) interval time 270 chapter 11 watch timer 11.2 watch timer configuration the watch timer consists of the following hardware. table 11-2. watch timer configuration item configuration counter 5 bits x 1 timer clock select register 2 (tcl2) watch timer mode control register (tmc2) control register 271 chapter 11 watch timer 11.3 watch timer control registers the following two types of registers are used to control the watch timer. ? timer clock select register 2 (tcl2) ? watch timer mode control register (tmc2) (1) timer clock select register 2 (tcl2) this register sets the watch timer count clock. tcl2 is set with an 8-bit memory manipulation instruction. reset input sets tcl2 to 00h. remark besides setting the watch timer count clock, tcl2 sets the watchdog timer count clock and buzzer output frequency. figure 11-1. watch timer block diagram selector tmc21 prescaler selector selector selector intwt 5-bit counter f w 2 14 f w 2 13 inttm3 to 16-bit timer/event counter watch timer mode control register tmc26 tmc25 tmc24 tmc23 tmc22 tmc21 tmc20 internal bus tcl24 timer clock select register 2 f w 2 4 f w 2 5 f w 2 6 f w 2 7 f w 2 8 f w 2 9 f w f xx /2 7 f xt clear clear 3 272 chapter 11 watch timer figure 11-2. timer clock select register 2 format caution when rewriting tcl2 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. x : dont care 5. mcs : bit 0 of oscillation mode selection register (osms) 6. figures in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. tcl27 7 tcl26 6 tcl25 tcl24 4 0 3210 ff42h address tcl2 symbol tcl22 tcl21 tcl20 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tcl22 tcl21 tcl20 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 11 mcs = 1 f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) f x /2 11 (2.4 khz) mcs = 0 f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 12 (1.2 khz) watchdog timer count clock selection 0 1 tcl24 f xx /2 7 f xt (32.768 khz) mcs = 1 f x /2 7 (39.1 khz) mcs = 0 f x /2 8 (19.5 khz) watch timer count clock selection 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 tcl27 tcl26 tcl25 buzzer output disable f xx /2 9 f xx /2 10 f xx /2 11 setting prohibited mcs = 1 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) mcs = 0 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) buzzer output frequency selection 273 chapter 11 watch timer (2) watch timer mode control register (tmc2) this register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/disables prescaler and 5-bit counter operations. tmc2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tmc2 to 00h. figure 11-3. watch timer mode control register format caution when the watch timer is used, the prescaler should not be cleared frequently. remarks 1. f w : watch timer clock frequency (f xx /2 7 or f xt ) 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency 4. f xt : subsystem clock oscillation frequency 0 7 tmc26 6 tmc25 tmc24 4 tmc23 3210 ff4ah address tmc2 symbol tmc22 tmc21 tmc20 5 00h after reset r/w r/w 0 1 tmc23 f xx = 5.0 mhz operation 2 14 /f w (0.4 sec) 2 13 /f w (0.2 sec) watch flag set time selection 0 0 0 0 1 1 other than above 0 0 1 1 0 0 0 1 0 1 0 1 tmc26 tmc25 tmc24 f xx = 5.0 mhz operation 2 4 /f w (410 s) 2 5 /f w (819 s) 2 6 /f w (1.64 ms) 2 7 /f w (3.28 ms) 2 8 /f w (6.55 ms) 2 9 /f w (13.1 ms) setting prohibited f xx = 4.19 mhz operation 2 4 /f w (488 s) 2 5 /f w (977 s) 2 6 /f w (1.95 ms) 2 7 /f w (3.91 ms) 2 8 /f w (7.81 ms) 2 9 /f w (15.6 ms) f xt = 32.768 khz operation 2 4 /f w (488 s) 2 5 /f w (977 s) 2 6 /f w (1.95 ms) 2 7 /f w (3.91 ms) 2 8 /f w (7.81 ms) 2 9 /f w (15.6 ms) prescaler interval time selection f xx = 4.19 mhz operation 2 14 /f w (0.5 sec) 2 13 /f w (0.25 sec) f xt = 32.768 khz operation 2 14 /f w (0.5 sec) 2 13 /f w (0.25 sec) tmc22 0 1 5-bit counter operation control clear after operation stop operation enable tmc21 0 1 prescaler operation control clear after operation stop operation enable tmc20 0 1 watch operating mode selection normal operating mode (flag set at f w /2 14 ) fast feed operating mode (flag set at f w /2 5 ) 274 chapter 11 watch timer 11.4 watch timer operations 11.4.1 watch timer operation when the 32.768-khz subsystem clock or 4.19-mhz main system clock is used, the timer operates as a watch timer with a 0.5-second or 0.25-second interval. the watch timer sets the test input flag (wtif) to 1 at the constant time interval. the standby state (stop mode/ halt mode) can be cleared by setting wtif to 1. when bit 2 (tmc22) of the watch timer mode control register (tmc2) is set to 0, the 5-bit counter is cleared and the count operation stops. for simultaneous operation of the interval timer, zero-second start can be achieved by setting tmc22 to 0 (maximum error: 26.2 ms when operated at f xx = 5.0 mhz). 11.4.2 interval timer operation the watch timer operates as interval timer which generates interrupt requests repeatedly at an interval of the preset count value. the interval time can be selected with bits 4 to 6 (tmc24 to tmc26) of the watch timer mode control register (tmc2). table 11-3. interval timer interval time tmc26 tmc25 tmc24 interval time when operated at when operated at when operated at f xx = 5.0 mhz f xx = 4.19 mhz f xt = 32.768 khz 000 2 4 x 1/f w 410 m s 488 m s 488 m s 001 2 5 x 1/f w 819 m s 977 m s 977 m s 010 2 6 x 1/f w 1.64 ms 1.95 ms 1.95 ms 011 2 7 x 1/f w 3.28 ms 3.91 ms 3.91 ms 100 2 8 x 1/f w 6.55 ms 7.81 ms 7.81 ms 101 2 9 x 1/f w 13.1 ms 15.6 ms 15.6 ms other than above setting prohibited fxx : main system clock frequency (fx or fx/2) fx : main system clock oscillation frequency f xt : subsystem clock oscillation frequency f w : watch timer clock frequency (fxx/2 7 or f xt ) 275 chapter 12 watchdog timer 12.1 watchdog timer functions the watchdog timer has the following functions. ? watchdog timer ? interval timer caution select the watchdog timer mode or the interval timer mode with the watchdog timer mode register (wdtm) (the watchdog timer and the interval timer cannot be used simultaneously). (1) watchdog timer mode an inadvertent program loop (runaway) is detected. upon detection of the runaway, a non-maskable interrupt request or reset can be generated. table 12-1. watchdog timer runaway times runaway detection time mcs = 1 mcs = 0 2 11 x 1/f xx 2 11 x 1/f x (410 m s) 2 12 x 1/f x (819 m s) 2 12 x 1/f xx 2 12 x 1/f x (819 m s) 2 13 x 1/f x (1.64 ms) 2 13 x 1/f xx 2 13 x 1/f x (1.64 ms) 2 14 x 1/f x (3.28 ms) 2 14 x 1/f xx 2 14 x 1/f x (3.28 ms) 2 15 x 1/f x (6.55 ms) 2 15 x 1/f xx 2 15 x 1/f x (6.55 ms) 2 16 x 1/f x (13.1 ms) 2 16 x 1/f xx 2 16 x 1/f x (13.1 ms) 2 17 x 1/f x (26.2 ms) 2 17 x 1/f xx 2 17 x 1/f x (26.2 ms) 2 18 x 1/f x (52.4 ms) 2 19 x 1/f xx 2 19 x 1/f x (104.9 ms) 2 20 x 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : bit 0 of oscillation mode selection register (osms) 4. figures in parentheses apply to operation with f x = 5.0 mhz. 276 chapter 12 watchdog timer (2) interval timer mode interrupt requests are generated at the preset time intervals. table 12-2. interval times interval time mcs = 1 mcs = 0 2 11 x 1/f xx 2 11 x 1/f x (410 m s) 2 12 x 1/f x (819 m s) 2 12 x 1/f xx 2 12 x 1/f x (819 m s) 2 13 x 1/f x (1.64 ms) 2 13 x 1/f xx 2 13 x 1/f x (1.64 ms) 2 14 x 1/f x (3.28 ms) 2 14 x 1/f xx 2 14 x 1/f x (3.28 ms) 2 15 x 1/f x (6.55 ms) 2 15 x 1/f xx 2 15 x 1/f x (6.55 ms) 2 16 x 1/f x (13.1 ms) 2 16 x 1/f xx 2 16 x 1/f x (13.1 ms) 2 17 x 1/f x (26.2 ms) 2 17 x 1/f xx 2 17 x 1/f x (26.2 ms) 2 18 x 1/f x (52.4 ms) 2 19 x 1/f xx 2 19 x 1/f x (104.9 ms) 2 20 x 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : bit 0 of oscillation mode selection register (osms) 4. figures in parentheses apply to operation with f x = 5.0 mhz. 277 chapter 12 watchdog timer prescaler f xx 2 4 f xx 2 5 f xx 2 6 f xx 2 7 f xx 2 8 f xx 2 9 selector watchdog timer mode register internal bus internal bus tcl22 tcl21 tcl20 f xx /2 3 f xx 2 11 timer clock select register 2 3 wdtm4 run wdtm3 8-bit counter tmmk4 run tmif4 intwdt maskable interrupt request reset intwdt non-maskable interrupt request control circuit 12.2 watchdog timer configuration the watchdog timer consists of the following hardware. table 12-3. watchdog timer configuration item configuration timer clock select register 2 (tcl2) watchdog timer mode register (wdtm) figure 12-1. watchdog timer block diagram control register 278 chapter 12 watchdog timer 12.3 watchdog timer control registers the following two types of registers are used to control the watchdog timer. ? timer clock select register 2 (tcl2) ? watchdog timer mode register (wdtm) (1) timer clock select register 2 (tcl2) this register sets the watchdog timer count clock. tcl2 is set with 8-bit memory manipulation instruction. reset input sets tcl2 to 00h. remark besides setting the watchdog timer count clock, tcl2 sets the watch timer count clock and buzzer output frequency. 279 chapter 12 watchdog timer figure 12-2. timer clock select register 2 format caution when rewriting tcl2 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. x : dont care 5. mcs : bit 0 of oscillation mode selection register (osms) 6. figures in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. tcl27 7 tcl26 6 tcl25 tcl24 4 0 3210 ff42h address tcl2 symbol tcl22 tcl21 tcl20 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tcl22 tcl21 tcl20 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 11 mcs = 1 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 11 mcs = 0 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 f x /2 12 watchdog timer count clock selection 0 1 tcl24 f xx /2 7 f xt (32.768 khz) mcs = 1 f x /2 7 (39.1 khz) mcs = 0 f x /2 8 (19.5 khz) watch timer count clock selection 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 tcl27 tcl26 tcl25 buzzer output disable f xx /2 9 f xx /2 10 f xx /2 11 setting prohibited mcs = 1 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) mcs = 0 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) buzzer output frequency selection (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (2.4 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (4.9 khz) (1.2 khz) 280 chapter 12 watchdog timer (2) watchdog timer mode register (wdtm) this register sets the watchdog timer operating mode and enables/disables counting. wdtm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets wdtm to 00h. figure 12-3. watchdog timer mode register format notes 1. once set to 1, wdtm3 and wdtm4 cannot be cleared to 0 by software. 2. operation as an interval timer is started as soon as is set to 1. 3. once set to 1, run cannot be cleared to 0 by software. thus, once counting starts, it can only be stopped by reset input. cautions 1. when 1 is set in run so that the watchdog timer is cleared, the actual overflow time is up to 0.5 % shorter than the time set by timer clock select register 2 (tcl2). 2. when using the watchdog timer modes 1 and 2, be sure that the interrupt request flag (tmif4) is 0 before setting wdtm4 to 1. if wdtm4 is set to 1 while tmif4 is 1, a non- maskable interrupt requests generated regardless of the contents of wdtm3. remark x : dont care rum <7> 0 6 0 wdtm4 4 wdtm3 3210 fff9h address wdtm symbol 000 5 00h after reset r/w r/w run 0 1 watchdog timer operation mode selection note 3 count stop counter is cleared and counting starts. wdtm3 x 0 1 watchdog timer operation mode selection note 1 interval timer mode note 2 (maskable interrupt occurs upon generation of an overflow.) watchdog timer mode 1 (non-maskable interrupt occurs upon generation of an overflow.) watchdog timer mode 2 (reset operation is activated upon generation of an overflow.) wdtm4 0 1 1 281 chapter 12 watchdog timer 12.4 watchdog timer operations 12.4.1 watchdog timer operation when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 1, the watchdog timer is operated to detect any runaway. the watchdog timer count clock (runaway detection time interval) can be selected with bits 0 to 2 (tcl20 to tcl22) of the timer clock select register 2 (tcl2). watchdog timer starts by setting bit 7 (run) of wdtm to 1. after the watchdog timer is started, set run to 1 within the set runaway detection time interval. the watchdog timer can be cleared and counting is started by setting run to 1. if run is not set to 1 and the runaway detection time is past, system reset or a non-maskable interrupt request is generated according to the wdtm bit 3 (wdtm3) value. the watchdog timer can be cleared when run is set to 1. the watchdog timer continues operating in the halt mode but it stops in the stop mode. thus, set run to 1 before the stop mode is set, clear the watchdog timer and then execute the stop instruction. cautions 1. the actual runaway detection time may be shorter than the set time by a maximum of 0.5 %. 2. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 12-4. watchdog timer runaway detection time tcl22 tcl21 tcl20 runaway detection time mcs = 1 mcs = 0 000 2 11 x 1/f xx 2 11 x 1/f x (410 m s) 2 12 x 1/f x (819 m s) 001 2 12 x 1/f xx 2 12 x 1/f x (819 m s) 2 13 x 1/f x (1.64 ms) 010 2 13 x 1/f xx 2 13 x 1/f x (1.64 ms) 2 14 x 1/f x (3.28 ms) 011 2 14 x 1/f xx 2 14 x 1/f x (3.28 ms) 2 15 x 1/f x (6.55 ms) 100 2 15 x 1/f xx 2 15 x 1/f x (6.55 ms) 2 16 x 1/f x (13.1 ms) 101 2 16 x 1/f xx 2 16 x 1/f x (13.1 ms) 2 17 x 1/f x (26.2 ms) 110 2 17 x 1/f xx 2 17 x 1/f x (26.2 ms) 2 18 x 1/f x (52.4 ms) 111 2 19 x 1/f xx 2 19 x 1/f x (104.9 ms) 2 20 x 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : bit 0 of oscillation mode selection register (osms) 4. tcl20 to tcl22 : bits 0 to 2 of timer clock select register 2 (tcl2) 5. figures in parentheses apply to operation with f x = 5.0 mhz. 282 chapter 12 watchdog timer 12.4.2 interval timer operation the watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (wdtm4) of the watchdog timer mode register (wdtm) is set to 0, respectively. the count clock (interval time) can be selected with bits 0 to 2 (tcl20 to tcl22) of the timer clock select register 2 (tcl2). the watchdog timer starts operation as an interval timer when bit 7 (run) of wdtm is set to 1. when the watchdog timer operated as interval timer, the interrupt mask flag (tmmk4) and priority specify flag (tmpr4) are validated and the maskable interrupt request (intwdt) can be generated. among maskable interrupt requests, the intwdt default has the highest priority. the interval timer continues operating in the halt mode but it stops in stop mode. thus, set bit 7 (run) of wdtm to 1 before the stop mode is set, clear the interval timer and then execute the stop instruction. cautions 1. once bit 4 (wdtm4) of wdtm is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless reset input is applied. 2. the interval time just after setting with wdtm may be shorter than the set time by a maximum of 0.5 %. 3. when the subsystem clock is selected for cpu clock, watchdog timer count operation is stopped. table 12-5. interval timer interval time tcl22 tcl21 tcl20 interval time mcs = 1 mcs = 0 000 2 11 x 1/f xx 2 11 x 1/f x (410 m s) 2 12 x 1/f x (819 m s) 001 2 12 x 1/f xx 2 12 x 1/f x (819 m s) 2 13 x 1/f x (1.64 ms) 010 2 13 x 1/f xx 2 13 x 1/f x (1.64 ms) 2 14 x 1/f x (3.28 ms) 011 2 14 x 1/f xx 2 14 x 1/f x (3.28 ms) 2 15 x 1/f x (6.55 ms) 100 2 15 x 1/f xx 2 15 x 1/f x (6.55 ms) 2 16 x 1/f x (13.1 ms) 101 2 16 x 1/f xx 2 16 x 1/f x (13.1 ms) 2 17 x 1/f x (26.2 ms) 110 2 17 x 1/f xx 2 17 x 1/f x (26.2 ms) 2 18 x 1/f x (52.4 ms) 111 2 19 x 1/f xx 2 19 x 1/f x (104.9 ms) 2 20 x 1/f x (209.7 ms) remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : bit 0 of oscillation mode selection register (osms) 4. tcl20 to tcl22 : bits 0 to 2 of timer clock select register 2 (tcl2) 5. figures in parentheses apply to operation with f x = 5.0 mhz. 283 chapter 13 clock output control circuit 13.1 clock output control circuit functions the clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral lsi. clocks selected with the timer clock select register 0 (tcl0) are output from the pcl/p35 pin. follow the procedure below to output clock pulses. (1) select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (tcl00 to tcl03) of tcl0. (2) set the p35 output latch to 0. (3) set bit 5 (pm35) of port mode register 3 (pm3) to 0 (set to output mode). (4) set bit 7 (cloe) of timer clock select register 0 (tcl0) to 1. caution clock output cannot be used when setting p35 output latch to 1. remark when clock output enable/disable is switched, the clock output control circuit does not output pulses with small widths (see the portions marked with * in figure 13-1). figure 13-1. remote controlled output application example cloe pcl/p35 pin output * * 284 chapter 13 clock output control circuit 13.2 clock output control circuit configuration the clock output control circuit consists of the following hardware. table 13-1. clock output control circuit configuration item configuration timer clock select register 0 (tcl0) port mode register 3 (pm3) figure 13-2. clock output control circuit block diagram control register internal bus f xx f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt cloe tcl03 tcl02 tcl01 tcl00 p35 output latch synchronizing circuit 4 pm35 selector timer clock select register 0 port mode register 3 pcl /p35 285 chapter 13 clock output control circuit 13.3 clock output function control registers the following two types of registers are used to control the clock output function. ? timer clock select register 0 (tcl0) ? port mode register 3 (pm3) (1) timer clock select register 0 (tcl0) this register sets pcl output clock. tcl0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets tcl0 to 00h. remark besides setting pcl output clock, tcl0 sets the 16-bit timer register count clock. 286 chapter 13 clock output control circuit figure 13-3. timer clock select register 0 format cautions 1. the ti00/p00/intp0 pin valid edge is set by external interrupt mode register 0 (intm0), and the sampling clock frequency is selected by the sampling clock selection register (scs). 2. when enabling pcl output, set tcl00 to tcl03, then set 1 in cloe with a 1-bit memory manipulation instruction. 3. to read the count value when ti00 has been specified as the tm0 count clock, the value should be read from tm0, not from capture/compare register 01 (cr01). 4. when rewriting tcl0 to other data, stop the clock operation beforehand. cloe <7> tcl06 6 tcl05 tcl04 4 tcl03 3210 ff40h address tcl0 symbol tcl02 tcl01 tcl00 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 1 other than above 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 tcl03 tcl02 tcl01 f xt (32.768 khz) f xx f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 setting prohibited mcs = 1 f x (5.0 mhz) f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) mcs = 0 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) pcl output clock selection cloe 0 1 pcl output control output disable output enable 0 0 0 0 1 1 other than above 0 0 1 1 0 1 0 1 0 1 0 1 tcl06 tcl05 tcl04 ti00 (valid edge specifiable) 2f xx f xx f xx /2 f xx /2 2 watch timer output (inttm3) setting prohibited mcs = 1 setting prohibited f x (5.0 mhz) f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) mcs = 0 f x (5.0 mhz) f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 16-bit timer register count clock selection tcl00 0 1 0 1 0 1 0 1 0 287 chapter 13 clock output control circuit remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. ti00 : 16-bit timer/event counter input pin 5. tm0 : 16-bit timer register 6. mcs : bit 0 of oscillation mode selection register (osms) 7. figures in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. (2) port mode register 3 (pm3) this register set port 3 input/output in 1-bit units. when using the p35/pcl pin for clock output function, set pm35 and output latch of p35 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 13-4. port mode register 3 format pm37 7 pm36 6 pm35 pm34 4 pm33 3210 ff23h address pm3 symbol pm32 pm31 pm30 5 ffh after reset r/w r/w pm3n 0 1 p3n pin input/output mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 288 [memo] 289 chapter 14 buzzer output control circuit 14.1 buzzer output control circuit functions the buzzer output control circuit outputs 1.2-khz, 2.4-khz, 4.9-khz, or 9.8-khz frequency square waves. the buzzer frequency selected with timer clock select register 2 (tcl2) is output from the buz/p36 pin. follow the procedure below to output the buzzer frequency. (1) select the buzzer output frequency with bits 5 to 7 (tcl25 to tcl27) of tcl2. (2) set the p36 output latch to 0. (3) set bit 6 (pm36) of port mode register 3 (pm3) to 0 (set to output mode). caution buzzer output cannot be used when setting p36 output latch to 1. 14.2 buzzer output control circuit configuration the buzzer output control circuit consists of the following hardware. table 14-1. buzzer output control circuit configuration item configuration timer clock select register 2 (tcl2) port mode register 3 (pm3) figure 14-1. buzzer output control circuit block diagram control register internal bus f xx /2 9 f xx /2 10 f xx /2 11 tcl27 tcl26 tcl25 3 pm36 selector timer clock select register 2 port mode register 3 buz/p36 p36 output latch 290 chapter 14 buzzer output control circuit 14.3 buzzer output function control registers the following two types of registers are used to control the buzzer output function. ? timer clock select register 2 (tcl2) ? port mode register 3 (pm3) (1) timer clock select register 2 (tcl2) this register sets the buzzer output frequency. tcl2 is set with an 8-bit memory manipulation instruction. reset input sets tcl2 to 00h. remark besides setting the buzzer output frequency, tcl2 sets the watch timer count clock and the watchdog timer count clock. 291 chapter 14 buzzer output control circuit figure 14-2. timer clock select register 2 format caution when rewriting tcl2 to other data, stop the timer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. f xt : subsystem clock oscillation frequency 4. x : dont care 5. mcs : bit 0 of oscillation mode selection register (osms) 6. figures in parentheses apply to operation with f x = 5.0 mhz or f xt = 32.768 khz. tcl27 7 tcl26 6 tcl25 tcl24 4 0 3210 ff42h address tcl2 symbol tcl22 tcl21 tcl20 5 00h after reset r/w r/w 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 tcl22 tcl21 tcl20 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 11 mcs = 1 f x /2 3 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 11 mcs = 0 f x /2 4 f x /2 5 f x /2 6 f x /2 7 f x /2 8 f x /2 9 f x /2 10 f x /2 12 watchdog timer count clock selection 0 1 tcl24 f xx /2 7 f xt (32.768 khz) mcs = 1 f x /2 7 (39.1 khz) mcs = 0 f x /2 8 (19.5 khz) watch timer count clock selection 0 1 1 1 1 x 0 0 1 1 x 0 1 0 1 tcl27 tcl26 tcl25 buzzer output disable f xx /2 9 f xx /2 10 f xx /2 11 setting prohibited mcs = 1 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) mcs = 0 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) f x /2 12 (1.2 khz) buzzer output frequency selection (625 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (2.4 khz) (313 khz) (156 khz) (78.1 khz) (39.1 khz) (19.5 khz) (9.8 khz) (4.9 khz) (1.2 khz) 292 chapter 14 buzzer output control circuit (2) port mode register 3 (pm3) this register sets port 3 input/output in 1-bit units. when using the p36/buz pin for buzzer output function, set pm36 and output latch of p36 to 0. pm3 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets pm3 to ffh. figure 14-3. port mode register 3 format pm37 7 pm36 6 pm35 pm34 4 pm33 3210 ff23h address pm3 symbol pm32 pm31 pm30 5 ffh after reset r/w r/w pm3n 0 1 p3n pin input/output mode selection (n = 0 to 7) output mode (output buffer on) input mode (output buffer off) 293 chapter 15 a/d converter 15.1 a/d converter functions the a/d converter converts an analog input into a digital value. it consists of 8 channels (ani0 to ani7) with an 8-bit resolution. the conversion method is based on successive approximation and the conversion result is held in the 8-bit a/ d conversion result register (adcr). the following two ways are available to start a/d conversion. (1) hardware start conversion is started by trigger input (intp3). (2) software start conversion is started by setting the a/d converter mode register (adm). one channel of analog input is selected from ani0 to ani7 and a/d conversion is carried out. in the case of hardware start, a/d conversion operation stops and an interrupt request (intad) is generated when an a/d conversion operation ends. in the case of software start, the a/d conversion operation is repeated. each time an a/d conversion operation ends, an interrupt request (intad) is generated. 15.2 a/d converter configuration the a/d converter consists of the following hardware. table 15-1. a/d converter configuration item configuration analog input 8 channels (ani0 to ani7) control register a/d converter mode register (adm) a/d converter input select register (adis) external interrupt mode register 1 (intm1) register successive approximation register (sar) a/d conversion result register (adcr) 294 chapter 15 a/d converter ani0/p10 ani1/p11 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 selector a/d converter mode register selector trigger enable es40, es41 note 3 sample & hold circuit 3 cs internal bus edge detector control circuit series resistor string av dd voltage comparator tap selector intad intp3 successive approximation register (sar) adis3 4 internal bus a/d converter input select register adis2 adis1 adis0 note 1 note 2 intp3/p03 trg fr1 fr0 adm3 adm2 adm1 a/ d conversion result register (adcr) av ref0 av ss figure 15-1. a/d converter block diagram notes 1. selector to select the number of channels to be used for analog input. 2. selector to select the channel for a/d conversion. 3. bits 0, 1 of external interrupt mode register 1 (intm1) 295 chapter 15 a/d converter (1) successive approximation register (sar) this register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (msb). when the result of comparison is held to the least significant bit (lsb) (termination of a/d conversion), the sar contents are transferred to the a/d conversion result register (adcr). (2) a/d conversion result register (adcr) this register holds the a/d conversion result. each time a/d conversion terminates, the conversion result is loaded from the successive approximation register. adcr is read with an 8-bit memory manipulation instruction. reset input makes adcr undefined. (3) sample & hold circuit the sample & hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator. this circuit holds the sampled analog input voltage value during a/d conversion. (4) voltage comparator the voltage comparator compares the analog input to the series resistor string output voltage. (5) series resistor string the series resistor string is connected between av ref0 to av ss and generates a voltage to be compared to the analog input. (6) ani0 to ani7 pins these are 8-channel analog input pins to input analog signals to undergo a/d conversion to the a/d converter. pins other than those selected as analog input by the a/d converter input select register (adis) can be used as input/output ports. cautions 1. use ani0 to ani7 input voltages within the specified range. if a voltage higher than av ref0 or lower than av ss is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes indeterminate and may adversely affect the converted values of other channels. 2. analog input (ani0 to ani7) pins are alternate function pins corresponding to input/ output port (port 1) pin. when a/d conversion is performed with any one of ani0 to ani7 pins selected, do not execute input instruction to port 1 during conversion operation, otherwise, the conversion resolution may be deteriorated. if digital pulse is applied to a pin adjacent to the pin performing a/d conversion, desired a/d conversion value may not be achieved due to the coupling noise. do not apply pulse to a pin adjacent to the pin performing a/d conversion. (7) av ref0 pin this pin inputs the a/d converter reference voltage. it converts signals input to ani0 to ani7 into digital signals according to the voltage applied between av ref0 and av ss . the current flowing in the series resistor string can be reduced by setting the voltage to be input to the av ref0 pin to av ss level in standby mode. 296 chapter 15 a/d converter caution a series resistor string of approximately 10 k w is connected between av ref0 pin and av ss pin. therefore, if the output impedance of the reference voltage source is high, av ref0 pin is connected in parallel with the series resistor string between av ref0 pin and av ss pin. as a result, the reference voltage error will increase. (8) av ss pin this is a gnd potential pin of the a/d converter. keep it at the same potential as the v ss pin when not using the a/d converter. (9) av dd pin this is an a/d converter analog power supply pin. keep it at the same potential as the v ss pin when not using the a/d converter. 15.3 a/d converter control registers the following three types of registers are used to control the a/d converter. ? a/d converter mode register (adm) ? a/d converter input select register (adis) ? external interrupt mode register 1 (intm1) (1) a/d converter mode register (adm) this register sets the analog input channel for a/d conversion, conversion time, conversion start/stop and external trigger. adm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adm to 01h. 297 chapter 15 a/d converter figure 15-2. a/d converter mode register format notes 1. set so that the a/d conversion time is 19.1 m s or more. 2. setting prohibited because a/d conversion time is less than 19.1 m s. cautions 1. the following sequence is recommended for power consumption reduction of a/d converter when the standby function is used: clear bit 7 (cs) to 0 first to stop the a/ d conversion operation, and then execute the halt or stop instruction. 2. when restarting the stopped a/d conversion operation, start the a/d conversion operation after clearing the interrupt request flag (adif) to 0. remarks 1. f x : main system clock oscillation frequency 2. mcs : bit 0 of oscillation mode selection register (osms) cs <7> trg <6> fr1 fr0 4 adm3 3210 ff80h address adm symbol adm2 adm1 hsc 5 01h after reset r/w r/w adm3 0 0 0 0 1 1 1 1 adm2 0 0 1 1 0 0 1 1 adm1 0 1 0 1 0 1 0 1 analog input channel selection ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 trg 0 1 external trigger selection no external trigger (software starts) conversion started by external trigger (hardware starts) fr1 0 0 1 1 fr0 0 1 0 0 a/d conversion time selection note 1 f x = 5.0-mhz operation mcs = 1 80/f x (setting prohibited note 2 ) 40/f x (setting prohibited note 2 ) 50/f x (setting prohibited note 2 ) 100/f x (20.0 s) setting prohibited mcs = 0 160/f x (32.0 s) 80/f x (setting prohibited note 2 ) 100/f x (20.0 s) 200/f x (40.0 s) f x = 4.19-mhz operation mcs = 1 80/f x (19.1 s) 40/f x (setting prohibited note 2 ) 50/f x (setting prohibited note 2 ) 100/f x (23.8 s) mcs = 0 160/f x (38.1 s) 80/f x (19.1 s) 100/f x (23.8 s) 200/f x (47.7 s) cs 0 1 a/d conversion operation control operation stop operation start hsc 1 1 0 1 other combinations 298 chapter 15 a/d converter (2) a/d converter input select register (adis) this register determines whether the ani0/p10 to ani7/p17 pins should be used for analog input channels or ports. pins other than those selected as analog input can be used as input/output ports. adis is set with an 8-bit memory manipulation instruction. reset input sets adis to 00h. cautions 1. set the analog input channel in the following order. (1) set the number of analog input channels with adis. (2) using the a/d converter mode register (adm), select one channel to undergo a/d conversion from among the channels set for analog input with adis. 2. no on-chip pull-up resistor can be used for the channels set for analog input with adis, irrespective of the value of bit 1 (puo1) of the pull-up resistor option register l (puol). figure 15-3. a/d converter input select register format 0 7 0 6 00 4 adis3 3210 ff84h address adis symbol adis2 adis1 adis0 5 00h after reset r/w r/w adis3 0 0 0 0 0 0 0 0 1 other than above number of analog input channel selection no analog input channel (p10 to p17) 1 channel (ani0, p11 to p17) 2 channel (ani0, ani1, p12 to p17) 3 channel (ani0 to ani2, p13 to p17) 4 channel (ani0 to ani3, p14 to p17) 5 channel (ani0 to ani4, p15 to p17) 6 channel (ani0 to ani5, p16, p17) 7 channel (ani0 to ani6, p17) 8 channel (ani0 to ani7) setting prohibited adis2 0 0 0 0 1 1 1 1 0 adis1 0 0 1 1 0 0 1 1 0 adis0 0 1 0 1 0 1 0 1 0 299 chapter 15 a/d converter (3) external interrupt mode register 1 (intm1) this register sets the valid edge for intp3 to intp6. intm1 is set with an 8-bit memory manipulation instruction. reset input sets intm1 to 00h. figure 15-4. external interrupt mode register 1 format es71 7 es70 6 es61 es60 4 es51 3210 ffedh address intm1 symbol es50 es41 es40 5 00h after reset r/w r/w es41 0 0 1 1 es40 0 1 0 1 intp3 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es51 0 0 1 1 es50 0 1 0 1 intp4 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es61 0 0 1 1 es60 0 1 0 1 intp5 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es71 0 0 1 1 es70 0 1 0 1 intp6 valid edge selection falling edge rising edge setting prohibited both falling and rising edges 300 chapter 15 a/d converter 15.4 a/d converter operations 15.4.1 basic operations of a/d converter (1) set the number of analog input channels with a/d converter input select register (adis). (2) from among the analog input channels set with adis, select one channel for a/d conversion with a/d converter mode register (adm). (3) sample the voltage input to the selected analog input channel with the sample & hold circuit. (4) sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until termination of a/d conversion. (5) bit 7 of the successive approximation register (sar) is set and the tap selector sets the series resistor string voltage tap to (1/2) av ref0 . (6) the voltage difference between the series resistor string voltage tap and analog input is compared with a voltage comparator. if the analog input is greater than (1/2) av ref0 , the msb of sar remains set. if the input is smaller than (1/2) av ref0 , the msb is reset. (7) next, bit 6 of sar is automatically set and the operation proceeds to the next comparison. in this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below. ? bit 7 = 1 : (3/4) av ref0 ? bit 7 = 0 : (1/4) av ref0 the voltage tap and analog input voltage are compared and bit 6 of sar is manipulated with the result as follows. ? analog input voltage 3 voltage tap : bit 6 = 1 analog input voltage < voltage tap : bit 6 = 0 (8) comparison of this sort continues up to bit 0 of sar. (9) upon completion of the comparison of 8 bits, any effective digital resultant value remains in sar and the resultant value is transferred to and latched in the a/d conversion result register (adcr). at the same time, the a/d conversion termination interrupt request (intad) can also be generated. 301 chapter 15 a/d converter figure 15-5. a/d converter basic operation a/d conversion operations are performed continuously until bit 7 (cs) of adm is reset (0) by software. if a write to adm is performed during an a/d conversion operation, the conversion operation is initialized, and if the cs bit is set (1), conversion starts again from the beginning. after reset input, the value of adcr is undefined. sar adcr intad a/d converter operation sampling time sampling a / d conversion conversion time undefined 80h c0h or 40h conversion result conversion result 302 chapter 15 a/d converter 15.4.2 input voltage and conversion results the relation between the analog input voltage input to the analog input pins (ani0 to ani7) and the a/d conversion result (the value stored in adcr) is shown by the following expression. adcr = int ( x 256 + 0.5) or (adcr C 0.5) x v in < (adcr + 0.5) x where, int( ) : function which returns integer parts of value in parentheses. v in : analog input voltage av ref0 : av ref0 pin voltage adcr : a/d conversion result register (adcr) figure 15-6 shows the relation between the analog input voltage and the a/d conversion result. figure 15-6. relationships between analog input voltage and a/d conversion result v in av ref0 av ref0 256 av ref0 256 1 512 1 256 3 512 2 256 5 512 3 256 507 512 254 256 509 512 255 256 511 512 1 255 254 253 3 2 1 0 a/d conversion results (adcr) input voltage/av ref0 303 chapter 15 a/d converter 15.4.3 a/d converter operating mode one analog input channel is selected from among ani0 to ani7 with the a/d converter input select register (adis) and a/d converter mode register (adm) and a/d conversion is executed. the following two ways are available to start a/d conversion. ? hardware start: conversion is started by trigger input (intp3). ? software start: conversion is started by setting adm. the a/d conversion result is stored in the a/d conversion result register (adcr) and the interrupt request signal (intad) is simultaneously generated. (1) a/d conversion by hardware start when bit 6 (trg) and bit 7 (cs) of the a/d converter mode register (adm) are set to 1, the a/d conversion standby state is set. when the external trigger signal (intp3) is input, the a/d conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (adm1 to adm3) of adm. upon termination of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr) and the interrupt request signal (intad) is generated. after one a/d conversion operation is started and terminated, another operation is not started until a new external trigger signal is input. if data with cs set to 1 is written to adm again during a/d conversion, the converter suspends its a/d conversion operation and waits for a new external trigger signal to be input. when the external trigger input signal is reinput, a/d conversion is carried out from the beginning. if data with cs set to 0 is written to adm during a/d conversion, the a/d conversion operation stops immediately. figure 15-7. a/d conversion by hardware start remark n = 0, 1, ... , 7 m = 0, 1, ... , 7 adm rewrite cs = 1, trg = 1 standby state anin intp3 a /d conversion adcr intad anin anin anin anim anim anin anin standby state standby state adm rewrite cs = 1, trg = 1 anim anim anim 304 chapter 15 a/d converter (2) a/d conversion operation in software start when bit 6 (trg) and bit 7 (cs) of a/d converter mode register (adm) are set to 0 and 1, respectively, the a/d conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (adm1 to adm3) of adm. upon termination of the a/d conversion, the conversion result is stored in the a/d conversion result register (adcr) and the interrupt request signal (intad) is generated. after one a/d conversion operation is started and terminated, the next a/d conversion operation starts immediately. the a/d conversion operation con- tinues repeatedly until new data is written to adm. if data with cs set to 1 is written to adm again during a/d conversion, the converter suspends its a/d conversion operation and starts a/d conversion on the newly written data. if data with cs set to 0 is written to adm during a/d conversion, the a/d conversion operation stops im- mediately. figure 15-8. a/d conversion by software start remark n = 0, 1, ... , 7 m = 0, 1, ... , 7 conversion start cs = 1, trg = 0 a /d conversion adcr intad anin anin anim anin anim anim anin anin adm rewrite cs = 1, trg = 0 adm rewrite cs = 0, trg = 0 conversion suspended conversion results are not stored stop 305 chapter 15 a/d converter 15.5 a/d converter cautions (1) current consumption in standby mode the a/d converter operates on the main system clock. therefore, its operation stops in stop mode or in halt mode with the subsystem clock. as a current still flows in the av ref0 pin at this time, this current must be cut in order to minimize the overall system power dissipation. in figure 15-9, the power dissipation can be reduced by outputting a low-level signal to the output port in standby mode. however, there is no precision to the actual av ref0 voltage, and therefore the conversion values themselves lack precision and can only be used for relative comparison. figure 15-9. example of method of reducing current consumption in standby mode series resistor string v dd av ref0 av ref0 av ss output port . . pd78078, 78078y = v dd 306 chapter 15 a/d converter (2) input range of ani0 to ani7 the input voltages of ani0 to ani7 should be within the specification range. in particular, if a voltage above av ref0 or below av ss is input (even if within the absolute maximum rating range), the conversion value for that channel will be indeterminate. the conversion values of the other channels may also be affected. (3) noise countermeasures in order to maintain 8-bit resolution, attention must be paid to noise on pins av ref0 and ani0 to ani7. since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in figure 15-10 in order to reduce noise. figure 15-10. analog input pin disposition (4) pins ani0/p10 to ani7/p17 the analog input pins ani0 to ani7 also function as input/output port (port1) pins. when a/d conversion is performed with any of pins ani0 to ani7 selected, be sure not to execute an input instruction to port 1 while conversion is in progress, as this may reduce the conversion resolution. also, if digital pulses are applied to a pin adjacent to the pin in the process of a/d conversion, the expected a/d conversion value may not be obtainable due to coupling noise. therefore, avoid applying pulses to pins adjacent to the pin undergoing a/d conversion. av ref0 or higher or av ss or lower may enter, ani0 to ani7 av ref0 v dd av dd av ss v ss reference voltage input c = 100 to 1000 pf if there is possibility that noise whose level is clamp with a diode with a small v f (0.3 v or less). v dd 307 chapter 15 a/d converter (5) av ref0 pin input impedance a series resistor string of approximately 10 k w is connected between the av ref0 pin and the av ss pin. therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the av ref0 pin and the av ss pin, and there will be a large reference voltage error. (6) interrupt request flag (adif) the interrupt request flag (adif) is not cleared even if the a/d converter mode register (adm) is changed. caution is therefore required since, if an analog input pin is changed during a/d conversion, the a/d conversion result and adif for the pre-change analog input may be set just before the adm rewrite, and when adif is read immediately after the adm rewrite, adif may be set despite the fact that the a/d conversion for the post-change analog input has not ended. when the a/d conversion is stopped and then resumed, clear the adif before it is resumed. figure 15-11. a/d conversion end interrupt request generation timing remark n = 0, 1, ... , 7 m = 0, 1, ... , 7 (7) av dd pin the av dd pin is the analog circuit power supply pin, and supplies power to the input circuits of ani0/p10 to ani7/p17. therefore, be sure to apply the same voltage as v dd to this pin even when the application circuit is designed so as to switch to a backup battery. figure 15-12. handling of av dd pin main power supply av ref0 v dd av dd av ss v ss capacitor for back-up a /d conversion adcr intad anin anin anim anim anin anin anim anim adm rewrite (start of anin conversion) adm rewrite (start of anim conversion) intad is set but anim conversion has not ended 308 [memo] 309 chapter 16 d/a converter 16.1 d/a converter functions the d/a converter converts a digital input into an analog value. it consists of two 8-bit resolution channels of voltage output type d/a converter. the conversion method used is the r-2r resistor ladder method. start the a/d conversion by setting the dace0 and dace1 of the d/a converter mode register (dam). there are two types of modes for the d/a converter, as follows. (1) normal mode outputs an analog voltage signal immediately after the d/a conversion. (2) real-time output mode outputs an analog voltage signal synchronously with the output trigger after the d/a conversion. since a sine wave can be generated in the mode, the use of this mode easily realizes an msk modem for cordless telephone sets. 310 chapter 16 d/a converter 16.2 d/a converter configuration the d/a converter consists of the following hardware. table 16-1. d/a converter configuration item configuration d/a conversion value set register 0 (dacs0) d/a conversion value set register 1 (dacs1) control register d/a converter mode register (dam) figure 16-1. d/a converter block diagram register selector d/a conversion value set register 1 (dacs1) internal bus internal bus 2r 2r 2r 2r r r selector 2r 2r 2r 2r r r dam5 ano1/p131 ano0/p130 d/a converter mode register dacs1 write inttm2 dacs0 write inttm1 av ref1 av ss d/a conversion value set register 0 (dacs0) dam4 dace1 dace0 311 chapter 16 d/a converter (1) d/a conversion value set register 0, 1 (dacs0, dacs1) dacs0 and dacs1 are registers that set the value used to determine analog voltage values output to the ano0 and ano1 pins, re-spectively. dacs0 and dacs1 are set with 8-bit memory manipulation instructions. reset input sets these registers to 00h. analog voltage output to the ano0 and ano1 pins is determined by the following expression. anon output voltage = av ref1 x where, n = 0, 1 cautions 1. in the real-time output mode, when data that are set in dacs0 and dacs1 are read before an output trigger is generated, the previous data are read rather than the set data. 2. in the real-time output mode, data should be set to dacs0 and dacs1 after an output trigger and before the next output trigger. dacsn 256 312 chapter 16 d/a converter 16.3 d/a converter control registers the d/a converter mode register (dam) controls the d/a converter. this register sets d/a converter operation enable/stop. the dam is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 16-2. d/a converter mode register format cautions 1. when using the d/a converter, a dual-function port pin should be set to the input mode, and a pull-up resistor should be disconnected. 2. always set bits 2, 3, 6, and 7 to 0. 3. when d/a conversion is stopped, the output state is high-impedance. 4. the output triggers are inttm1 and inttm2 for channel 0 and channel 1, respectively, in the real-time output mode. 0 7 0 6 dam5 dam4 4 0 3 2 <1> <0> ff98h address dam symbol 0 dace1 dace0 5 00h after reset r/w r/w dam5 0 1 d/a converter channel 1 operating mode normal mode real-time output mode dace0 0 1 d/a converter channel 0 control d/a conversion stop d/a conversion enable dace1 0 1 d/a converter channel 1 control d/a conversion stop d/a conversion enable dam4 0 1 d/a converter channel 0 operating mode normal mode real-time output mode 313 chapter 16 d/a converter 16.4 d/a converter operations (1) select the channel 0 operating mode and channel 1 operating mode with dam4 and dam5, respectively, of the d/a converter mode register (dam). (2) set the data corresponding to the analog voltages output to the ano0/p130 and ano1/p131 pins to the d/a conversion value setting registers 0 and 1 (dacs0 and dacs1), respectively. (3) start the channel 0 and channel 1 d/a conversion operations by setting dace0 and dace1, respectively, of the dam. (4) in the normal mode, the analog voltage signals are output to the ano0/p130 and ano1/p131 pins immediately after the d/a conversion. in the real-time output mode, the analog voltage signals are output synchronously with the output triggers. (5) in the normal mode, the analog voltage signals to be output are held until new data are set in dacs0 and dacs1. in the realtime output mode, new data are set in dacs0 and dacs1 and then they are held until the next trigger is generated. caution set dace0 and dace1 after setting data in dacs0 and dacs1. 314 chapter 16 d/a converter 16.5 d/a converter cautions (1) output impedance of d/a converter because the output impedance of the d/a converter is high, use of current flowing from the anon pins (n = 0,1) is prohibited. if the input impedance of the load for the converter is low, insert a buffer amplifier between the load and the anon pins. in addition, wiring from the anon pins to the buffer amplifier or the load should be as short as possible (because of high output impedance). if the wiring may be long, design the ground pattern so as to be close to those lines or use some other expedient to achieve shorter wiring. figure 16-3. use example of buffer amplifier (a) inverting amplifier (b) voltage-follower (2) output voltage of d/a converter because the output voltage of the converter changes in steps, use the d/a converter output signals in general by connecting a low-pass filter. (3) av ref1 pin when only either one of the d/a converter channels is used with av ref1 < v dd , the other pins that are not used as analog outputs must be set as follows: ? set pm13x bit of the port mode register 13 (pm13) to 1 (input mode) and connect the pin to v ss . ? set pm13x bit of the port mode register 13 (pm13) to 0 (output mode) and the output latch to 0, to output low level from the pin. pd78078, 78078y anon r 1 c r 2 ?the input impedance of the buffer amplifier is r 1 . pd78078, 78078y anon r r 1 c ?the input impedance of the buffer amplifier is r 1 . ?if r 1 is not connected, the output becomes undefined when reset is low. 315 chapter 17 serial interface channel 0 ( m pd78078 subseries) the m pd78078 subseries incorporates three channels of serial interfaces. differences between channels 0, 1, and 2 are as follows (refer to chapter 19 serial interface channel 1 for details of the serial interface channel 1. refer to chapter 20 serial interface channel 2 for details of the serial interface channel 2). table 17-1. differences between channels 0, 1, and 2 none serial transfer mode channel 0 f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output channel 1 f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output channel 2 external clock, baud rate generator output msb/lsb switchable as the start bit serial transfer end interrupt request flag (srif) clock selection transfer end flag transfer method 3-wire serial i/o sbi (serial bus interface) 2-wire serial i/o uart (asynchronous serial interface) use possible none none use possible msb/lsb switchable as the start bit automatic transmit/ receive function serial transfer end interrupt request flag (csiif1) serial transfer end interrupt request flag (csiif0) msb/lsb switchable as the start bit chapter 17 serial interface channel 0 ( m pd78078 subseries) 316 17.1 serial interface channel 0 functions serial interface channel 0 employs the following four modes. ? operation stop mode ? 3-wire serial i/o mode ? sbi (serial bus interface) mode ? 2-wire serial i/o mode caution do not change the operation mode (3-wire serial i/o/2-wire serial i/o/sbi) while operation of the serial interface channel 0 is enabled. stop the serial operation before changing the operation mode. (1) operation stop mode this mode is used when serial transfer is not carried out. power consumption can be reduced. (2) 3-wire serial i/o mode (msb-/lsb-first selectable) this mode is used for 8-bit data transfer using three lines, one each for serial clock (sck0), serial output (so0) and serial input (si0). this enables simultaneous transmission/reception and therefore reduces the data transfer processing time. the start bit of transferred 8-bit data is switchable between msb and lsb, so that devices can be connected regardless of their start bit recognition. this mode should be used when connecting with peripheral i/o devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75x/xl, 78k, and 17k series. (3) sbi (serial bus interface) mode (msb-first) this mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (sck0) and serial data bus (sb0 or sb1). sbi mode complies with the nec serial bus format. in the sbi mode, transfer data is transmitted/received as one of the three data types: address, command, or data. ? address : data to select the target device for serial communication ? command : data to give an instruction to the target device ? data : data actually transmitted the actual transmission is performed in the following procedure: the master device outputs an address on the serial bus and selects a slave device with which the master device is to perform communication from among several devices. the master device and the slave device mutually transmit and receive commands and data to achieve serial transfer. the receiving side can automatically identify the received data as an address, command, or data in hardware. this function enables the input/output ports to be used effectively and the application program serial interface control portions to be simplified. in this mode, the wake-up function for handshake and the output function of acknowledge and busy signals can also be used. chapter 17 serial interface channel 0 ( m pd78078 subseries) 317 master cpu sck0 sb0 sck0 sb0 slave cpu1 sck0 sb0 slave cpu2 sck0 sb0 slave cpun v dd0 (4) 2-wire serial i/o mode (msb-first) this mode is used for 8-bit data transfer using two lines of serial clock (sck0) and serial data bus (sb0 or sb1). this mode enables to cope with any one of the possible data transfer formats by controlling the sck0 level and the sb0 or sb1 output level. thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in the increased number of available input/output port pins. figure 17-1. serial bus interface (sbi) system configuration example chapter 17 serial interface channel 0 ( m pd78078 subseries) 318 17.2 serial interface channel 0 configuration serial interface channel 0 consists of the following hardware. table 17-2. serial interface channel 0 configuration item configuration serial i/o shift register 0 (sio0) slave address register (sva) timer clock select register 3 (tcl3) serial operating mode register 0 (csim0) control register serial bus interface control register (sbic) interrupt timing specify register (sint) port mode register 2 (pm2) note note refer to figure 6-5 block diagram of p20, p21, p23 to p26 and figure 6-6 block diagram of p22 and p27 . figure 17-2. serial interface channel 0 block diagram remark output control selects either cmos output or n-ch open drain output. register csie0 coi wup csim 04 csim 03 csim 02 csim 01 csim 00 serial operating mode register 0 control circuit output control selector si0/sb0 /p25 pm25 output control so0/sb1 /p26 pm26 output control sck0 /p27 pm27 selector p25 output latch p26 output latch cld p27 output latch internal bus bsye ackd acke ackt cmdd reld cmdt relt internal bus slave address register (sva) serial i/o shift register 0 (sio0) bus release/ command/ acknowledge detector serial clock counter serial clock control circuit clr d set q match busy/ acknowledge output circuit interrupt request signal generator ackd cmdd reld wup selector selector cld sic svam tcl33 tcl32 tcl31 tcl30 4 csim01 csim00 csim01 csim00 to2 interrupt timing specify register timer clock select register 3 f xx /2 to f xx /2 8 intcsi0 serial bus interface control register svam chapter 17 serial interface channel 0 ( m pd78078 subseries) 319 (1) serial i/o shift register 0 (sio0) this is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. sio0 is set with an 8-bit memory manipulation instruction. when bit 7 (csie0) of serial operating mode register 0 (csim0) is 1, writing data to sio0 starts serial operation. in transmission, data written to sio0 is output to the serial output (so0) or serial data bus (sb0/sb1). in reception, data is read from the serial input (si0) or sb0/sb1 to sio0. note that, if a bus is driven in the sbi mode or 2-wire serial i/o mode, the bus pin must serve for both input and output. thus, in the case of a device for reception, write ffh to sio0 in advance (except when address reception is carried out by setting bit 5 (wup) of csim0 to 1). in the sbi mode, the busy state can be cleared by writing data to sio0. in this case, bit 7 (bsye) of the serial bus interface control register (sbic) is not cleared to 0. reset input makes sio0 undefined. (2) slave address register (sva) this is an 8-bit register to set the slave address value for connection of a slave device to the serial bus. sva is set with an 8-bit memory manipulation instruction. this register is not used in the 3-wire serial i/o mode. the master device outputs a slave address for selection of a particular slave device to the connected slave device. these two data (the slave address output from the master device and the sva value) are compared with an address comparator. if they match, the slave device has been selected. in that case, bit 6 (coi) of serial operating mode register 0 (csim0) becomes 1. address comparison can also be executed on the data of lsb-masked high-order 7 bits by setting (1) bit 4 (svam) of the interrupt timing specify register (sint). if no matching is detected in address reception, bit 2 (reld) of the serial bus interface control register (sbic) is cleared to 0. in the sbi mode, when bit 5 (wup) of the csim0 is set (1), the wake-up function can be used. in this case, the interrupt request signal (intcsi0) is generated only if the slave address output from the master matches the sva value. this interrupt request enables to recognize the generation of the communication request from the master device. if the bit 5 (sic) of the interrupt timing specify register (sint) is set (1), the wake-up function does not operate even when wup is set (1) (the interrupt request signal is generated when a bus release is detected). when using the wake-up function, clear sic to 0. further, when sva transmits data as master or slave device in the sbi or 2-wire serial i/o mode, errors are detected if any. reset input makes sva undefined. chapter 17 serial interface channel 0 ( m pd78078 subseries) 320 (3) so0 latch this latch holds si0/sb0/p25 and so0/sb1/p26 pin levels. it can be directly controlled by software. in the sbi mode, this latch is set upon termination of the 8th serial clock. (4) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) serial clock control circuit this circuit controls serial clock supply to the serial i/o shift register 0 (sio0). when the internal system clock is used, the circuit also controls clock output to the sck0/p27 pin. (6) interrupt request signal generator this circuit controls interrupt request signal generation. it generates the interrupt request signal in the following cases. ? in the 3-wire serial i/o mode and 2-wire serial i/o mode this circuit generates an interrupt request signal every eight serial clocks. ? in the sbi mode when wup note is 0 ...... generates an interrupt request signal every eight serial clocks. when wup note is 1 ...... generates an interrupt request signal when the serial i/o shift register 0 (sio0) value matches the slave address register (sva) value after address reception. note wup is wake-up function specify bit. it is bit 5 of serial operating mode register 0 (csim0). when using the wake-up function (wup = 1), clear bit 5 (sic) of the interrupt timing specify register (sint) to 0. (7) busy/acknowledge output circuit and bus release/command/acknowledge detector these two circuits output and detect various control signals in the sbi mode. these do not operate in the 3-wire serial i/o mode and 2-wire serial i/o mode. chapter 17 serial interface channel 0 ( m pd78078 subseries) 321 17.3 serial interface channel 0 control registers the following four types of registers are used to control serial interface channel 0. ? timer clock select register 3 (tcl3) ? serial operating mode register 0 (csim0) ? serial bus interface control register (sbic) ? interrupt timing specify register (sint) (1) timer clock select register 3 (tcl3) this register sets the serial clock of serial interface channel 0. tcl3 is set with an 8-bit memory manipulation instruction. reset input sets tcl3 to 88h. chapter 17 serial interface channel 0 ( m pd78078 subseries) 322 figure 17-3. timer clock select register 3 format caution when rewriting tcl3 to other data, stop the serial transfer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : bit 0 of oscillation mode selection register (osms) 4. figures in parentheses apply to operation with f x = 5.0 mhz. serial interface channel 0 serial clock selection tcl33 tcl32 tcl31 tcl30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) other than above setting prohibited serial interface channel 1 serial clock selection tcl37 tcl36 tcl35 tcl34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) other than above setting prohibited 6543210 7 symbol tcl3 tcl37 tcl36 tcl35 tcl34 tcl33 tcl32 tcl31 tcl30 ff43h 88h r/w address after reset r/w chapter 17 serial interface channel 0 ( m pd78078 subseries) 323 (2) serial operating mode register 0 (csim0) this register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. caution do not change the operation mode (3-wire serial i/o/2-wire serial i/o/sbi) while operation of the serial interface channel 0 is enabled. stop the serial operation before changing the operation mode. chapter 17 serial interface channel 0 ( m pd78078 subseries) 324 sbi mode <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 0 sck0 (cmos input/output) r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 1 csim00 x 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function x 10 x 0 x 0 0 x 0 x 0 0 1 1 note 3 note 3 note 3 note 3 msb p25 (cmos input/output) sb0 (n-ch open-drain input/output) sb1 (n-ch open-drain input/output) p26 (cmos input/output) 1 msb lsb 1x0001 note 2 3-wire serial l/o mode si0 note 2 (input) so0 (cmos output) sck0 (cmos input/output) 2-wire serial l/o mode 0 sck0 (n-ch open-drain input/output) 1 11 x 0 x 0 0 x 0 x 0 0 1 1 note 3 note 3 note 3 note 3 msb p25 (cmos input/output) sb0 (n-ch open-drain input/output) sb1 (n-ch open-drain input/output) p26 (cmos input/output) note 2 wup 0 1 wake-up function control note 4 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd = reld = 1) matches the slave address register data in sbi mode r/w coi 0 1 slave address comparison result flag note 5 slave address register not equal to serial i/o shift register 0 data slave address register equal to serial i/o shift register 0 data r csie0 0 1 serial interface channel 0 operation control operation stopped operation enable r/w figure 17-4. serial operating mode register 0 format notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos input/output) when used only for transmission. 3. can be used freely as port function. 4. when using the wake-up function (wup = 1), set bit 5 (sic) of the interrupt timing specify register (sint) to 0. 5. when csie0 = 0, coi becomes 0. remark x : dont care pmxx : port mode register pxx : port output latch chapter 17 serial interface channel 0 ( m pd78078 subseries) 325 (3) serial bus interface control register (sbic) this register sets serial bus interface operation and displays statuses. sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. figure 17-5. serial bus interface control register format (1/2) note bits 2, 3 and 6 (reld, cmdd, and ackd) are read-only bits. remarks 1. bits 0, 1, and 4 (reld, cmdt, and ackt) are 0 when read after data setting. 2. csie0 : bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt used for bus release signal output. when relt = 1, so0 iatch is set to 1. after so0 latch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for command signal output. when cmdt = 1, so0 iatch is cleared to 0. after so0 latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w r reld bus release detection set conditions (reld =1) clear conditions (reld = 0) when bus release signal (rel) is detected ?when transfer start instruction is executed ?if sio0 and sva values do not match in address reception ?when csie0 = 0 ?when reset input is applied r cmdd command detection clear conditions (cmdd = 0) ?when transfer start instruction is executed ?when bus release signal (rel) is detected ?when csie0 = 0 ?when reset input is applied set conditions (cmdd = 1) ?when command signal (cmd) is detected ackt acknowledge signal is output in synchronization with the falling edge clock of sck0 just after execution of the instruction to be set to 1, and after acknowledge signal output, automatically cleared to 0. used as acke = 0. also cleared to 0 upon start of serial interface transfer or when csie0 = 0. r/w chapter 17 serial interface channel 0 ( m pd78078 subseries) 326 figure 17-5. serial bus interface control register format (2/2) note the busy mode can be cancelled with start of serial interface transfer. however, the bsye flag is not cleared to 0. remark csie0 : bit 7 of serial operating mode register 0 (csim0) acke acknowledge signal output control 0 acknowledge signal automatic output disable (output with ackt enable) acknowledge signal is output in synchronization with the 9th clock falling edge of sck0 (automatically output when acke = 1). before completion of transfer acknowledge signal is output in synchronization with the falling edge of sck0 just after execution of the instruction to be set to 1 (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. after completion of transfer 1 r/w r ackd acknowledge detection clear conditions (ackd = 0) falling edge of the sck0 immediately after the busy mode is released while executing the transfer start instruction ?when csie0 = 0 ?when reset input is applied set conditions (ackd = 1) ?when acknowledge signal (ack) is detected at the rising edge of sck0 clock after completion of transfer bsye synchronizing busy signal output control 0 disables busy signal which is output in synchronization with the falling edge of sck0 clock just after execution of the instruction to be cleared to 0. r/w note 1 outputs busy signal at the falling edge of sck0 clock following the acknowledge signal. chapter 17 serial interface channel 0 ( m pd78078 subseries) 327 (4) interrupt timing specify register (sint) this register sets the bus release interrupt and address mask functions and displays the sck0/p27 pin level status. sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. figure 17-6. interrupt timing specify register format notes 1. bit 6 (cld) is a read-only bit. 2. when using wake-up function in the sbi mode, set sic to 0. 3. when csie0 = 0, cld becomes 0. caution set bits 0 to 3 to 0. remark sva : slave address register csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of serial operating mode register 0 (csim0) <6><5><4>3210 7 symbol sint 0 cld sic svam 0 0 0 0 ff63h 00h r/w note 1 address after reset r/w svam 0 1 sva bit to be used as slave address bits 0 to 7 bits 1 to 7 sic 0 intcsi0 interrupt cause selection note 2 csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0/p27 pin level note 3 low level high level r/w r/w r 1 chapter 17 serial interface channel 0 ( m pd78078 subseries) 328 17.4 serial interface channel 0 operations the following four operating modes are available to the serial interface channel 0. ? operation stop mode ? 3-wire serial i/o mode ? sbi mode ? 2-wire serial i/o mode 17.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. thus, power consumption can be reduced. the serial i/o shift register 0 (sio0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register. in the operation stop mode, the p25/si0/sb0, p26/so0/sb1 and p27/sck0 pins can be used as ordinary input/ output ports. (1) register setting the operation stop mode is set with the serial operating mode register 0 (csim0). csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 ff60h 00h r/w address after reset r/w csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 chapter 17 serial interface channel 0 ( m pd78078 subseries) 329 <6><5>43210 <7> symbol csim0 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 sbi mode (see 17.4.3 sbi mode operation .) r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 x 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function x 10 wup 0 1 wake-up function control note 3 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd = reld = 1) matches the slave address register (sva) data in sbi mode r/w 1 msb lsb 1x0001 note 2 3-wire serial l/o mode si0 note 2 (input) so0 (cmos output) sck0 (cmos input/output) 2-wire serial i/o mode (see 17.4.4 2-wire serial i/o mode operation .) 11 note 2 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 17.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is valid for connection of peripheral i/o units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75x/xl, 78k, and 17k series. communication is carried out with three lines of serial clock (sck0), serial output (so0), and serial input (si0). (1) register setting the 3-wire serial i/o mode is set with the serial operating mode register 0 (csim0) and serial bus interface control register (sbic). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos input/output) when used only for transmission. 3. set wup to 0 when the 3-wire serial i/o mode is selected. remark x : dont care pmxx : port mode register pxx : port output latch chapter 17 serial interface channel 0 ( m pd78078 subseries) 330 (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. remark csie0 : bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so0 iatch is set to 1. after so0 iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so0 iatch is cleared to 0. after so0 latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w chapter 17 serial interface channel 0 ( m pd78078 subseries) 331 (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. bit-wise data transmission/ reception is carried out in synchronization with the serial clock. shift operation of the serial i/o shift register 0 (sio0) is carried out at the falling edge of the serial clock (sck0). the transmitted data is held in the so0 latch and is output from the so0 pin. the received data input to the si0 pin is latched in sio0 at the rising edge of sck0. upon termination of 8-bit transfer, sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 17-7. 3-wire serial i/o mode timings the so0 pin is a cmos output pin and outputs current so0 latch statuses. thus, the so0 pin output status can be manipulated by setting bit 0 (relt) and bit 1 (cmdt) of the serial bus interface control register (sbic). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 17.4.5 sck0/p27 pin output manipulation ). (3) other signals figure 17-8 shows relt and cmdt operations. figure 17-8. relt and cmdt operations relt cmdt so0 latch si0 sck0 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so0 do7 do6 do5 do4 do3 do2 do1 do0 csiif0 transfer start at the falling edge of sck0 end of transfer chapter 17 serial interface channel 0 ( m pd78078 subseries) 332 (4) msb/lsb switching as the start bit the 3-wire serial i/o mode enables to select transfer to start at msb or lsb. figure 17-9 shows the configuration of the serial i/o shift register 0 (sio0) and internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. msb/lsb switching as the start bit can be specified with bit 2 (csim02) of the serial operating mode register 0 (csim0). figure 17-9. circuit of switching in transfer bit order start bit switching is realized by switching the bit order for data write to sio0. the sio0 shift order remains unchanged. thus, switching between the msb-first and lsb-first must be performed before writing data to the shift register. (5) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1. ? internal serial clock is stopped or sck0 is a high level after 8-bit serial transfer. caution if csie0 is set to 1 after data write to sio0, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si0 shift register 0 (sio0) read/write gate so0 sck0 dq so0 latch chapter 17 serial interface channel 0 ( m pd78078 subseries) 333 17.4.3 sbi mode operation sbi (serial bus interface) is a high-speed serial interface in compliance with the nec serial bus format. sbi uses a single-master device and employs the clocked serial i/o format with the addition of a bus configuration function. this function enables devices to communicate using only two lines. thus, when making up a serial bus with two or more microcontrollers and peripheral ics, the number of ports to be used and the number of wires on the board can be decreased. the master device outputs three kinds of data to slave devices on the serial data bus: addresses to select a device to be communicated with, commands to instruct the selected device, and data which is actually required. the slave device can identify the received data into address, command, or data, by hardware. this function simplifies application programs which control serial interface channel 0. the sbi function is incorporated into various devices including 75x/xl series and 78k series. figure 17-10 shows a serial bus configuration example when a cpu having a serial interface compliant with sbi and peripheral ics are used. in sbi, the sb0 (sb1) serial data bus pin is an open-drain output pin and therefore the serial data bus line behaves in the same way as the wired-or configuration. in addition, a pull-up resistor must be connected to the serial data bus line. when the sbi mode is used, refer to (11) sbi mode precautions (d) described later. figure 17-10. example of serial bus configuration with sbi caution when exchanging the master cpu/slave cpu, a pull-up resistor is necessary for the serial clock line (sck0) as well because serial clock line (sck0) input/output switching is carried out asynchronously between the master and slave cpus. master cpu sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) slave cpu address 1 slave cpu address 2 slave ic address n serial clock serial data bus v dd chapter 17 serial interface channel 0 ( m pd78078 subseries) 334 (1) sbi functions in the conventional serial i/o format, when a serial bus is configured by connecting two or more devices, many ports and wiring are necessary, to provide chip select signal to identify command and data, and to judge the busy state, because only the data transfer function is available. if these operations are to be controlled by software, the software must be heavily loaded. in sbi, a serial bus can be configured with two signal lines of serial clock sck0 and serial data bus sb0 (sb1). thus, use of sbi leads to reduction in the number of microcontroller ports and that of wirings and routings on the board. the sbi functions are described below. (a) address/command/data identify function serial data is distinguished into addresses, commands, and data. (b) chip select function by address transmission the master executes slave chip selection by address transmission. (c) wake-up function the slave can easily judge address reception (chip select judgment) with the wake-up function (which can be set/reset by software). when the wake-up function is set, the interrupt request signal (intcsi0) is generated upon reception of a match address. thus, when communication is executed with two or more devices, the cpu except the selected slave devices can operate regardless of underway serial communications. (d) acknowledge signal (ack) control function the acknowledge signal to check serial data reception is controlled. (e) busy signal (busy) control function the busy signal to report the slave busy state is controlled. chapter 17 serial interface channel 0 ( m pd78078 subseries) 335 sck0 sb0 (sb1) sck0 sb0 (sb1) sck0 sb0 (sb1) 89 9 a7 a0 ack busy c7 c0 ack busy ready 89 d7 d0 ack busy ready address transfer command transfer data transfer bus release signal command signal address data command (2) sbi definition the sbi serial data format and the signals to be used are defined as follows. serial data to be transferred with sbi consists of three kinds of data, ?ddress? ?ommand? and ?ata? figure 17-11 shows the address, command, and data transfer timings. figure 17-11. sbi transfer timings remark the broken lines indicate the ready state. the bus release signal and the command signal are output by the master device. busy is output by the slave signal. ack can be output by either the master or slave device (normally, the 8-bit data receiver outputs). serial clocks continue to be output by the master device from 8-bit data transfer start to busy reset. chapter 17 serial interface channel 0 ( m pd78078 subseries) 336 sck0 ? sb0 (sb1) (a) bus release signal (rel) the bus release signal is a signal with the sb0 (sb1) line which has changed from the low level to the high level when the sck0 line is at the high level (without serial clock output). this signal is output by the master device. figure 17-12. bus release signal the bus release signal indicates that the master device is going to transmit an address to the slave device. the slave device incorporates hardware to detect the bus release signal. caution if the sb0 (sb1) line changes from low level to high level while the sck0 line is in high level, this is recognized as a bus release signal. therefore, if the changing timing of bus fluctuates because of the substrate capacity, etc., it may be recognized as a bus release signal even while data is being transmitted. care should be taken for the wiring. (b) command signal (cmd) the command signal is a signal with the sb0 (sb1) line which has changed from the high level to the low level when the sck0 line is at the high level (without serial clock output). this signal is output by the master device. figure 17-13. command signal the command signal indicates that the master device is going to transmit a command to the slave device (however, the command signal following a bus release signal indicates that the master device is going to transmit an address). the slave device incorporates hardware to detect the command signal. caution if the sb0 (sb1) line changes from high level to low level while the sck0 line is in high level, this is recognized as a command signal. therefore, if the changing timing of bus fluctuates because of the substrate capacity, etc., it may be recognized as a command signal even while data is being transmitted. care should be taken for the wiring. sck0 ? sb0 (sb1) chapter 17 serial interface channel 0 ( m pd78078 subseries) 337 (c) address an address is 8-bit data which the master device outputs to the slave device connected to the bus line in order to select a particular slave device. figure 17-14. addresses 8-bit data following bus release and command signals is defined as an address. in the slave device, this condition is detected by hardware and whether or not 8-bit data matches the own specification number (slave address) is checked by hardware. if the 8-bit data matches the slave address, the slave device has been selected. after that, communication with the master device continues until a release instruction is received from the master device. figure 17-15. slave selection with address sck0 a7 a6 a5 a4 a3 a2 a1 a0 12345678 sb0 (sb1) address command signal bus release signal master slave 1 non-selection slave 2 selection slave 3 non-selection slave 4 non-selection slave 2 address transmission chapter 17 serial interface channel 0 ( m pd78078 subseries) 338 (d) command and data the master device transmits commands to, and transmits/receives data to/from the slave device selected by address transmission. figure 17-16. commands figure 17-17. data 8-bit data following a command signal is defined as command data. 8-bit data without command signal is defined as data. command and data operation procedures are allowed to determine by user arbitrarily according to communications specifications. sck0 c7 c6 c5 c4 c3 c2 c1 c0 12345678 sb0 (sb1) command command signal sck0 d7 d6 d5 d4 d3 d2 d1 d0 12345678 sb0 (sb1) data chapter 17 serial interface channel 0 ( m pd78078 subseries) 339 (e) acknowledge signal (ack) the acknowledge signal is used to check serial data reception between transmitter and receiver. figure 17-18. acknowledge signal [when output in synchronization with 11th clock sck0] [when output in synchronization with 9th clock sck0] remark the brokens lines indicate the ready state. the acknowledge signal is one-shot pulse to be generated at the falling edge of sck0 after 8-bit data transfer. it can be positioned anywhere and can be synchronized with any clock sck0. after 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge signal. if the acknowledge signal is not returned for the preset period of time after data transmission, it can be judged that data reception has not been carried out correctly. (f) busy signal (busy) and ready signal (ready) the busy signal is intended to report to the master device that the slave device is preparing for data transmission/reception. the ready signal is intended to report to the master device that the slave device is ready for data transmission/reception. figure 17-19. busy and ready signals in sbi, the slave device notifies the master device of the busy state by setting sb0 (sb1) line to the low level. the busy signal output follows the acknowledge signal output from the master or slave device. it is set/reset at the falling edge of sck0. when the busy signal is reset, the master device automatically terminates the output of sck0 serial clock. when the busy signal is reset and the ready signal is set, the master device can start the next transfer. caution in the sbi mode, the busy signal continues to be output after busy clear instruction generation to the falling edge of the next serial clock (sck0). if wup is set to 1 in this period, busy will not be released. therefore, before setting wup to 1, clear busy and then check that sb0 (sb1) pin has become high level. sck0 sb0 (sb1) 8 9 10 11 ack 89 ack sck0 sb0 (sb1) ready ack sck0 sb0 (sb1) busy 89 chapter 17 serial interface channel 0 ( m pd78078 subseries) 340 (3) register setting the sbi mode is set with the serial operating mode register 0 (csim0), the serial bus interface control register (sbic) and the interrupt timing specify register (sint). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. notes 1. bit 6 (coi) is a read-only bit. 2. can be used as a port. 3. when using the wake-up function (wup = 1), set bit 5 (sic) of the interrupt timing specify register (sint) to 0. 4. when csie0 = 0, coi becomes 0. remark x : dont care pmxx : port mode register pxx : port output latch sbi mode <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 sck0 (cmos input/output) r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 1 csim00 x 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function x 10 x 0 x 0 0 x 0 x 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos input/output) sb0 (n-ch open-drain input/output) sb1 (n-ch open-drain input/output) p26 (cmos input/output) wup 0 1 wake-up function control note 3 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd = reld = 1) matches the slave address register (sva) data in sbi mode r/w 11 3-wire serial i/o mode (see 17.4.2 3-wire serial i/o mode operation .) 2-wire serial i/o mode (see 17.4.4 2-wire serial i/o mode operation .) coi 0 slave address comparison result flag note 4 slave address register (sva) not equal to serial i/o shift register 0 (sio0) data slave address register (sva) equal to serial i/o shift register 0 (sio0) data r 1 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 chapter 17 serial interface channel 0 ( m pd78078 subseries) 341 (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. note bits 2, 3, and 6 (reld, cmdd, and ackd) are read-only bits. remarks 1. bits 0, 1, and 4 (relt, cmdt, and ackt) are 0 when read after data setting. 2. csie0 : bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt used for bus release signal output. when relt = 1, so0 iatch is set to 1. after so0 latch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for command signal output. when cmdt = 1, so0 iatch is cleared to 0. after so0 latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w r reld bus release detection set conditions (reld = 1) clear conditions (reld = 0) when bus release signal (rel) is detected ?when transfer start instruction is executed ?if sio0 and sva values do not match in address reception (when wup = 1) when csie0 = 0 when reset input is applied r cmdd command detection clear conditions (cmdd = 0) ?when transfer start instruction is executed ?when bus release signal (rel) is detected ?when csie0 = 0 ?when reset input is applied set conditions (cmdd = 1) ?when command signal (cmd) is detected acknowledge signal is output in synchronization with the falling edge clock of sck0 just after execution of the instruction to be set to (1) and, after acknowledge signal output, automatically cleared to (0). used as acke = 0. also cleared to (0) upon start of serial interface transfer or when csie0 = 0. r/w acke acknowledge signal output control 0 acknowledge signal automatic output disable (output with ackt enable) acknowledge signal is output in synchronization with the 9th clock falling edge of sck0 (automatically output when acke = 1). before completion of transfer acknowledge signal is output in synchronization with falling edge clock of sck0 just after execution of the instruction to be set to 1 (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. after completion of transfer 1 r/w ackt chapter 17 serial interface channel 0 ( m pd78078 subseries) 342 r ackd acknowledge detection clear conditions (ackd = 0) ? sck0 fall immediately after the busy mode is released during the transfer start instruction execution. ? when csie0 = 0 ? when reset input is applied set conditions (ackd = 1) when acknowledge signal (ack) is detected at the rising edge of sck0 clock after completion of transfer bsye synchronizing busy signal output control 0 disables busy signal which is output in synchronization with the falling edge of sck0 clock just after execution of the instruction to be cleared to (0) (sets ready state). r/w note 1 outputs busy signal at the falling edge of sck0 clock following the acknowledge signal. note busy mode can be cleared by start of serial interface transfer. however, bsye flag is not cleared to 0. remark csie0 : bit 7 of serial operating mode register 0 (csim0) chapter 17 serial interface channel 0 ( m pd78078 subseries) 343 (c) interrupt timing specify register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. notes 1. bit 6 (cld) is a read-only bit. 2. when using wake-up function in the sbi mode, set sic to 0. 3. when csie0 = 0, cld becomes 0. caution set bits 0 to 3 to 0. remark sva : slave address register csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of serial operating mode register 0 (csim0) <6><5><4>3210 7 symbol sint 0 cld sic svam 0 0 0 0 ff63h 00h r/w note 1 address after reset r/w svam 0 1 sva bit to be used as slave address bits 0 to 7 bits 1 to 7 sic 0 intcsi0 interrupt factor selection note 2 csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0/p27 pin level note 3 low level high level r/w r/w r 1 344 chapter 17 serial interface channel 0 ( m pd78078 subseries) (4) various signals figures 17-20 to 17-25 show various signals and flag operations in the serial bus interface control register (sbic). table 17-3 lists various signals in sbi. figure 17-20. relt, cmdt, reld, and cmdd operations (master) figure 17-21. reld and cmdd operations (slave) sck0 sb0 (sb1) relt cmdt cmdd reld sio0 slave address write to sio0 (transfer start instruction) write ffh to sio0 (transfer start instruction) sio0 sck0 sb0 (sb1) reld cmdd transfer start instruction a7 a6 a1 a0 12 789 ready a7 a6 a1 a0 ack slave address when addresses match when addresses do not match 345 chapter 17 serial interface channel 0 ( m pd78078 subseries) figure 17-22. ackt operation caution do not set ackt before termination of transfer. sck0 6 sb0 (sb1) ackt 7 8 9 d2 d1 d0 ack when set during this period ack signal is output for a period of one clock just after setting 346 chapter 17 serial interface channel 0 ( m pd78078 subseries) figure 17-23. acke operations (a) when acke = 1 upon completion of transfer (b) when set after completion of transfer (c) when acke = 0 upon completion of transfer (d) when acke = 1 period is short sb0 (sb1) acke 1 2 789 d7 d6 d2 d1 d0 ack when acke = 1 at this point ack signal is output at 9th clock sck0 sb0 (sb1) acke 7 89 d1 d0 ack 6 d2 if set during this period and acke = 1 at the falling edge of the next sck0 ack signal is output for a period of one clock just after setting sck0 sb0 (sb1) acke 1 2 789 d7 d6 d2 d1 d0 when acke = 0 at this point ack signal is not output sck0 sb0 (sb1) acke if set and cleared during this period and acke = 0 at the falling edge of sck0 ack signal is not output d2 d1 d0 sck0 347 chapter 17 serial interface channel 0 ( m pd78078 subseries) figure 17-24. ackd operations (a) when ack signal is output at 9th clock of sck0 (b) when ack signal is output after 9th clock of sck0 (c) clear timing when transfer start is instructed in busy figure 17-25. bsye operation sck0 sb0 (sb1) ackd 789 d1 d0 ack 6 d2 transfer start instruction sio0 transfer start sb0 (sb1) ackd ack 9 sio0 78 d1 6 d2 d0 transfer start instruction transfer start sck0 sck0 sb0 (sb1) ackd ack 9 transfer start instruction sio0 78 d1 6 d2 d0 d6 d7 busy sck0 sb0 (sb1) bsye 7 89 ack 6 when bsye = 1 at this point busy if reset during this period and bsye = 0 at the falling edge of sck0 d2 d1 d0 348 chapter 17 serial interface channel 0 ( m pd78078 subseries) table 17-3. various signals in sbi mode (1/2) timing chart definition signal name output device output condition effects on flag meaning of signal cmd signal is output to indicate that transmit data is an address. i) transmit data is an address after rel signal output. ii) rel signal is not output and trans- mit data is an command. low-level signal to be output to sb0 (sb1) during one-clock period of sck0 after completion of serial reception [synchronous busy signal] low-level signal to be output to sb0 (sb1) following acknowledge signal (1) bsye = 0 (2) execution of instruction for data write to sio0 (transfer start instruction) master/ slave sb0 (sb1) rising edge when sck0 = 1 master bus release signal (rel) ? relt set ? reld set ? cmdd clear ? cmdd set ? cmdt set master command signal (cmd) sb0 (sb1) falling edge when sck0 = 1 acknowledge signal (ack) (1) acke = 1 (2) ackt set ? ackd set completion of reception slave busy signal (busy) ? bsye = 1 serial receive disable because of processing serial receive enable slave ready signal (ready) high-level signal to be output to sb0 (sb1) before serial transfer start and after completion of serial transfer [synchronous busy output] sck0 d0 ready sb0 (sb1) d0 ready sb0 (sb1) ack busy busy ack 9 sck0 ? sb0 (sb1) ? sb0 (sb1) sck0 349 chapter 17 serial interface channel 0 ( m pd78078 subseries) timing chart definition signal name output device output condition effects on flag meaning of signal synchronous clock to output address/command/data, ack signal, synchronous busy signal, etc. address/ command/data are transferred with the first eight synchronous clocks. 8-bit data to be transferred in synchronization with sck0 after output of only cmd signal without rel signal output master numeric values to be processed with slave or master device serial clock (sck0) timing of signal output to serial data bus address value of slave device on the serial bus address (a7 to a0) 8-bit data to be transferred in synchronization with sck0 after output of rel and cmd signals master commands (c7 to c0) instructions and messages to the slave device master/ slave data (d7 to d0) 8-bit data to be transferred in synchronization with sck0 without output of rel and cmd signals table 17-3. various signals in sbi mode (2/2) when csie0 = 1, execution of instruction for data write to sio0 (serial transfer start instruction) note 2 notes 1. when wup = 0, csiif0 is set at the rising edge of the 9th clock of sck0. when wup = 1, an address is received. only when the address matches the slave address register (sva) value, csiif0 is set (whe n they do not match, reld is cleared). 2. in busy state, transfer starts after the ready state is set. master csiif0 set (rising edge of 9th clock of sck0) note 1 sck0 sb0 (sb1) 1278 sck0 sb0 (sb1) 1278 cmd sck0 sb0 (sb1) 1278 rel cmd sck0 sb0 (sb1) 1278910 350 chapter 17 serial interface channel 0 ( m pd78078 subseries) (5) pin configuration the serial clock pin sck0 and serial data bus pin sb0 (sb1) have the following configurations. (a) sck0 ............ serial clock input/output pin <1> master ... cmos and push-pull output <2> slave ..... schmitt input (b) sb0 (sb1) .... serial data input/output dual-function pin both master and slave devices have an n-ch open drain output and a schmitt input. because the serial data bus line has an n-ch open-drain output, an external pull-up resistor is necessary. figure 17-26. pin configuration caution because the n-ch open-drain output must be high-impedance state at time of data reception, write ffh to the serial i/o shift register 0 (sio0) in advance. the n-ch open-drain can be high-impedance state at any time of transfer. however, when the wake-up function specify bit (wup) = 1, the n-ch open-drain output is always high-impedance state. thus, it is not necessary to write ffh to sio0. si0 so0 si0 so0 (clock input) clock output master device clock input (clock output) serial clock sck0 sck0 r l serial data bus sb0 (sb1) sb0 (sb1) n-ch open drain n-ch open drain slave device 351 chapter 17 serial interface channel 0 ( m pd78078 subseries) (6) address match detection method in the sbi mode, a particular slave device can be selected by transmitting slave address from the master device. address match detection can be automatically executed by hardware. with slave address register, csiif0 is set only when the wake-up function specify bit (wup) = 1 and the address transmitted from the master device matches the value set to sva. when bit 5 (sic) of the interrupt timing specify register (sint) is set (1), the wake-up function does not operate even if wup is set (1) (the interrupt request signal is generated when a bus release is detected). when using the wake-up function, clear sic to 0. cautions 1. slave selection/non-selection is detected by matching of the slave address received after bus release (reld = 1). for this match detection, match interrupt request (intcsi0) of the address to be generated with wup = 1 is normally used. thus, execute selection/non-selection detection by slave address when wup = 1. 2. when detecting selection/non-selection without the use of interrupt request with wup = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (7) error detection in the sbi mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, the serial i/o shift register 0 (sio0). thus, transmit errors can be detected in the following way. (a) method of comparing sio0 data before transmission to that after transmission in this case, if two data differ from each other, a transmit error is judged to have occurred. (b) method of using the slave address register (sva) transmit data is set to both sio0 and sva and is transmitted. after termination of transmission, coi bit (match signal coming from the address comparator) of the serial operating mode register 0 (csim0) is tested. if 1, normal transmission is judged to have been carried out. if 0, a transmit error is judged to have occurred. (8) communication operation in the sbi mode, the master device selects normally one slave device as communication target from among two or more devices by outputting an address to the serial bus. after the communication target device has been determined, commands and data are transmitted/received and serial communication is realized between the master and slave devices. figures 17-27 to 17-30 show data communication timing charts. shift operation of the serial i/o shift register 0 (sio0) is carried out at the falling edge of serial clock (sck0). transmit data is latched into the so0 latch and is output with msb set as the first bit from the sb0/p25 or sb1/p26 pin. receive data input to the sb0 (or sb1) pin at the rising edge of sck0 is latched into the sio0. 352 chapter 17 serial interface channel 0 ( m pd78078 subseries) 1 2 3 4 5 6 7 8 9 sck0 pin a7 a6 a5 a4 a3 a2 a1 a0 ack busy sb0 (sb1) pin program processing serial transmission intcsi0 generation ackd set sck0 stop hardware operation wup<- 0 ackt set program processing cmdd set intcsi0 generation ack output hardware operation cmdt set relt set cmdt set write to sio0 interrupt servicing (preparation for the next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) cmdd clear cmdd set reld set serial reception busy output ready (when sva = sio0) address busy clear busy clear figure 17-27. address transmission from master device to slave device (wup = 1) 353 chapter 17 serial interface channel 0 ( m pd78078 subseries) 1 2 3 4 5 6 7 8 9 sck0 pin c7 c6 c5 c4 c3 c2 c1 c0 ack busy sb0 (sb1) pin program processing serial transmission intcsi0 generation ackd set sck0 stop hardware operation ackt set program processing intcsi0 generation ack output hardware operation cmdt set write to sio0 interrupt servicing (preparation for the next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) cmdd set serial reception busy output ready command busy clear busy clear sio0 read command analysis figure 17-28. command transmission from master device to slave device 354 chapter 17 serial interface channel 0 ( m pd78078 subseries) 1 2 3 4 5 6 7 8 9 sck0 pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin program processing serial transmission intcsi0 generation ackd set sck0 stop hardware operation ackt set program processing intcsi0 generation ack output hardware operation write to sio0 interrupt servicing (preparation for the next serial transfer) master device processing (transmitter) transfer line slave device processing (receiver) serial reception busy output ready data busy clear busy clear sio0 read figure 17-29. data transmission from master device to slave device 355 chapter 17 serial interface channel 0 ( m pd78078 subseries) 1 2 3 4 5 6 7 8 9 sck0 pin d7 d6 d5 d4 d3 d2 d1 d0 ack busy sb0 (sb1) pin program processing serial reception intcsi0 generation ack output serial reception hardware operation program processing intcsi0 generation ackd set hardware operation ffh write to sio0 master device processing (receiver) transfer line slave device processing (transmitter) serial transmission busy output ready data busy clear write to sio0 sck0 stop busy clear 12 ready busy d7 d6 ackt set sio0 read receive data processing ffh write to sio0 write to sio0 figure 17-30. data transmission from slave device to master device 356 chapter 17 serial interface channel 0 ( m pd78078 subseries) (9) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1 ? internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer. cautions 1. if csie0 is set to 1 after data write to sio0, transfer does not start. 2. because the n-ch open-drain output must be high-impedance state for data reception, write ffh to sio0 in advance. however, when the wake-up function specify bit (wup) = 1, the n-ch open-drain output is always high-impedance state. thus, it is not necessary to write ffh to sio0. 3. if data is written to sio0 when the slave is busy, the data is not lost. when the busy state is cleared and sb0 (or sb1) input is set to the high level (ready) state, transfer starts. upon end of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. after reset input, perform the following settings to the pins used as data input/output (sb0 or sb1) before serial transfer of the first byte. <1> set 1 to the output latch of p25 and p26 <2> set 1 to bit 0 (relt) of the serial bus interface control register (sbic). <3> set 0 to the output latch of p25 and p26, to which 1 has been set. (10) how to detect the busy state in a slave when device is in the master mode, follow the procedure below to judge whether slave device is in the busy state or not. <1> detect acknowledge signal (ack) or interrupt request signal generation. <2> set the port mode register pm25 (or pm26) of the sb0/p25 (or sb1/p26) pin into the input mode. <3> read out the pin state (when the pin level is high, the ready state is set). after the detection of the ready state, set the port mode register to 0 and return to the output mode. (11) sbi mode precautions (a) slave selection/non-selection is detected by match detection of the slave address received after bus release (reld = 1). for this match detection, match interrupt (intcsi0) of the address to be generated with wup = 1 is normally used. thus, execute selection/non-selection detection by slave address when wup = 1. (b) when detecting selection/non-selection without the use of interrupt with wup = 0, do so by means of transmission/reception of the command preset by program instead of using the address match detection method. (c) in the sbi mode, the busy signal continues to be output after busy clear instruction generation to the falling edge of the next serial clock (sck0). if wup is set to 1 in this period, busy will not be released. therefore, before setting wup to 1, clear busy and then check that sb0 (sb1) pin has become high level. 357 chapter 17 serial interface channel 0 ( m pd78078 subseries) (d) for pins which are to be used for data input/output, be sure to carry out the following settings before serial transfer of the 1st byte after reset input. <1> set 1 to the output latch of p25 and p26 <2> set 1 to bit 0 (relt) of the serial bus interface control register (sbic). <3> set 0 to the output latch of p25 and p26, to which 1 has been set. (e) if the sb0 (sb1) line changes from low level to high level or from high level to low level while the sck0 line is at high level, it is recognized as either a bus release signal or a command signal. therefore, if the changing timing of bus fluctuates because of the wiring capacitance, etc., this may be wrongly interpreted as a bus release signal (or a command signal) even while data is being transmitted. care should be taken in the wiring. 17.4.4 2-wire serial i/o mode operation the 2-wire serial i/o mode can cope with any communication format by program. communication is basically carried out with two lines of serial clock (sck0) and serial data input/output (sb0 or sb1). figure 17-31. serial bus configuration example using 2-wire serial i/o mode master sck0 slave sb0 (sb1) sck0 sb0 (sb1) v dd v dd 358 chapter 17 serial interface channel 0 ( m pd78078 subseries) <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 x 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/p25 pin function so0/sb1/p26 pin function sck0/p27 pin function x 10 wup 0 1 wake-up function control note 3 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after bus release (when cmdd = reld = 1) matches the slave address register (sva) data in sbi mode r/w 2-wire serial l/o mode 0 sck0 (n-ch open-drain input/output) 1 11 x 0 x 0 0 x 0 x 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos input/output sb0 (n-ch open-drain input/output) sb1 (n-ch open-drain input/output) p26 (cmos input/output) 3-wire serial i/o mode (see 17.4.2 3-wire serial i/o mode operation .) sbi mode (see 17.4.3 sbi mode operation .) coi 0 slave address comparison result flag note 4 slave address register (sva) not equal to serial i/o shift register 0 (sio0) data slave address register (sva) equal to serial i/o shift register 0 (sio0) data r 1 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 (1) register setting the 2-wire serial i/o mode is set with the serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specify register (sint). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. notes 1. bit 6 (coi) is a read-only bit. 2. can be used freely as port function. 3. set wup to 0 when the 2-wire serial i/o mode is selected. 4. when csie0 = 0, coi becomes 0. remark x : dont care pmxx : port mode register pxx : port output latch 359 chapter 17 serial interface channel 0 ( m pd78078 subseries) (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. remark csie0 : bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so0 iatch is set to 1. after so0 iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so0 iatch is cleared to 0. after so0 latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w 360 chapter 17 serial interface channel 0 ( m pd78078 subseries) (c) interrupt timing specify register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. notes 1. bit 6 (cld) is a read-only bit. 2. when csie0 = 0, cld becomes 0. caution set bits 0 to 3 to 0. remark csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of serial operating mode register 0 (csim0) <6><5><4>3210 7 symbol sint 0 cld sic 0 0 0 0 ff63h 00h r/w note 1 address after reset r/w sic 0 intcsi0 interrupt factor selection csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0/p27 pin level note 2 low level high level r/w r 1 svam 361 chapter 17 serial interface channel 0 ( m pd78078 subseries) (2) communication operation the 2-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. shift operation of the serial i/o shift register 0 (sio0) is carried out in synchronization with the falling edge of the serial clock (sck0). the transmit data is held in the so0 latch and is output from the sb0/p25 (or sb1/p26) pin on an msb-first basis. the receive data input from the sb0 (or sb1) pin is latched into the sio0 at the rising edge of sck0. upon termination of 8-bit transfer, the sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 17-32. 2-wire serial i/o mode timings the sb0 (or sb1) pin specified for the serial data bus is an n-ch open-drain input/output pin and thus it must be externally connected to a pull-up resistor. because it is necessary to set the n-ch open-drain output to high-impedance state for data reception, write ffh to sio0 in advance. the sb0 (or sb1) pin generates the so0 latch status and thus the sb0 (or sb1) pin output status can be manipulated by setting bit 0 (relt) and bit 1 (cmdt) of the serial bus interface control register (sbic). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 17.4.5 sck0/p27 pin output manipulation ). (3) other signals figure 17-33 shows relt and cmdt operations. figure 17-33. relt and cmdt operations 123 4 5 6 7 8 sck0 d7 d6 d5 d4 d3 d2 d1 d0 sb0 (sb1) csiif0 transfer start at the falling edge of sck0 end of transfer relt cmdt so0 latch 362 chapter 17 serial interface channel 0 ( m pd78078 subseries) (4) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1 ? internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer. cautions 1. if csie0 is set to 1 after data write to sio0, transfer does not start. 2. because the n-ch transistor must be set n-ch open-drain output to high-impedance state for data reception, write ffh to sio0 in advance. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. (5) error detection in the 2-wire serial i/o mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, the serial i/o shift register 0 (sio0). thus, transmit error can be detected in the following way. (a) method of comparing sio0 data before transmission to that after transmission in this case, if two data differ from each other, a transmit error is judged to have occurred. (b) method of using the slave address register (sva) transmit data is set to both sio0 and sva and is transmitted. after termination of transmission, coi bit (match signal coming from the address comparator) of the serial operating mode register 0 (csim0) is tested. if 1, normal transmission is judged to have been carried out. if 0, a transmit error is judged to have occurred. 363 chapter 17 serial interface channel 0 ( m pd78078 subseries) to internal circuit sck0/p27 p27 output latch when csie0 = 1 and csim01 and csim00 are 1 and 0, or 1 and 1. set by bit manipulation instruction sck0 (1 when transfer stops) from serial clock control circuit 17.4.5 sck0/p27 pin output manipulation because the sck0/p27 pin incorporates an output latch, static output is also possible by software in addition to normal serial clock output. p27 output latch manipulation enables setting any value to sck0 by software (si0/sb0 and so0/sb1 pin to be controlled with the relt and cmdt bits of the serial bus interface control register (sbic)). sck0/p27 pin output manipulating procedure is described below. (1) set the serial operating mode register 0 (csim0) (sck0 pin enabled for serial operation in the output mode). sck0 = 1 with serial transfer suspended. (2) manipulate the p27 output latch with a bit manipulation instruction. figure 17-34. sck0/p27 pin configuration 364 [memo] 365 chapter 18 serial interface channel 0 ( m pd78078y subseries) the m pd78078y subseries incorporates three channels of serial interfaces. differences between channels 0, 1, and 2 are as follows (refer to chapter 19 serial interface channel 1 for details of the serial interface channel 1. refer to chapter 20 serial interface channel 2 for details of the serial interface channel 2). table 18-1. differences between channels 0, 1, and 2 serial transfer mode channel 0 f xx /2, f xx /2 2 , f xx /2 3 , f xx / 2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output msb/lsb switchable as the start bit serial transfer end interrupt request flag (csiif0) channel 1 f xx /2, f xx /2 2 , f xx /2 3 , f xx / 2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xx /2 8 , external clock, to2 output msb/lsb switchable as the start bit automatic transmit/ receive function serial transfer end interrupt request flag (csiif1) channel 2 external clock, baud rate generator output msb/lsb switchable as the start bit serial transfer end interrupt request flag (srif) clock selection transfer method transfer end flag i 2 c bus (inter ic bus) 2-wire serial i/o uart (asynchronous serial interface) use possible none none none use possible 3-wire serial i/o 366 chapter 18 serial interface channel 0 ( m pd78078y subseries) 18.1 serial interface channel 0 functions serial interface channel 0 employs the following four modes. ? operation stop mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode ?i 2 c (inter ic) bus mode caution do not change the operation mode (3-wire serial i/o/2-wire serial i/o/i 2 c bus) while the operation of the serial interface channel 0 is enabled. stop the serial operation before changing the operation mode. (1) operation stop mode this mode is used when serial transfer is not carried out. power consumption can be reduced. (2) 3-wire serial i/o mode (msb-/lsb-first selectable) this mode is used for 8-bit data transfer using three lines, one each for serial clock (sck0), serial output (so0) and serial input (si0). this mode enables simultaneous transmission/reception and therefore reduces the data transfer processing time. the start bit of transferred 8-bit data is switchable between msb and lsb, so that devices can be connected regardless of their start bit recognition. this mode should be used when connecting with peripheral i/o devices or display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75x/xl, 78k, and 17k series. (3) 2-wire serial i/o mode (msb-first) this mode is used for 8-bit data transfer using two lines of serial clock (sck0) and serial data bus (sb0 or sb1). this mode enables to cope with any one of the possible data transfer formats by controlling the sck0 level and the sb0 or sb1 output level. thus, the handshake line previously necessary for connection of two or more devices can be removed, resulting in the increased number of available input/output ports. 367 chapter 18 serial interface channel 0 ( m pd78078y subseries) (4) i 2 c (inter ic) bus mode (msb-first) this mode is used for 8-bit data transfer with two or more devices using two lines of serial clock (scl) and serial data bus (sda0 or sda1). this mode is in compliance with the i 2 c bus format. in this mode, the transmitter outputs three kinds of data onto the serial data bus: start condition, data, and stop condition, to be actually sent or received. the receiver automatically distinguishes the received data into start condition, data, or stop condition, by hardware. figure 18-1. serial bus configuration example using i 2 c bus master cpu scl sda0 (sda1) scl sda0 (sda1) slave cpu1 slave cpu2 slave cpun v dd v dd scl sda0 (sda1) scl sda0 (sda1) 368 chapter 18 serial interface channel 0 ( m pd78078y subseries) 18.2 serial interface channel 0 configuration serial interface channel 0 consists of the following hardware. table 18-2. serial interface channel 0 configuration item configuration serial i/o shift register 0 (sio0) slave address register (sva) timer clock select register 3 (tcl3) serial operating mode register 0 (csim0) control register serial bus interface control register (sbic) interrupt timing specify register (sint) port mode register 2 (pm2) note note refer to figure 6-7 block diagram of p20, p21, p23 to p26 and figure 6-8 block diagram of p22 and p27 . register 369 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-2. serial interface channel 0 block diagram remark output control performs selection between cmos output and n-ch open-drain output. csie0 coi wup csim 04 csim 03 csim 02 csim 01 csim 00 serial operating mode register 0 control circuit output control selector si0/sb0/ sda0/p25 pm25 output control so0/sb1/ sda1/p26 pm26 output control sck0/ scl/p27 pm27 selector p25 output latch p26 output latch cld p27 output latch internal bus bsye ackd acke ackt cmdd reld cmdt relt internal bus stop condition/ start condition/ acknowledge detector serial clock counter serial clock control circuit clr d set q match acknowledge output circuit request interrupt signal generator ackd cmdd reld wup selector selector tcl33 tcl32 tcl31 tcl30 4 timer clock select register 3 f xx /2 to f xx /2 8 intcsi0 cld sic svam bsye clc wrel wat1 wat0 csim01 csim00 to2 1/16 divider csim01 csim00 interrupt timing specify register slave address register (sva) svam serial bus interface control register 2 serial i/o shift register 0 (sio0) 370 chapter 18 serial interface channel 0 ( m pd78078y subseries) (1) serial i/o shift register 0 (sio0) this is an 8-bit register to carry out parallel-serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. sio0 is set with an 8-bit memory manipulation instruction. when bit 7 (csie0) of serial operating mode register 0 (csim0) is 1, writing data to sio0 starts serial operation. in transmission, data written to sio0 is output to the serial output (so0) or serial data bus (sb0/sb1). in reception, data is read from the serial input (si0) or sb0/sb1 to sio0. note that, if a bus is driven in the i 2 c bus mode or 2-wire serial i/o mode, the bus pin must serve for both input and output. therefore, the transmission n-ch open-drain output of the device which will start reception of data must be set to high-impedance state beforehand. consequently, write ffh to sio0 in advance. in the i 2 c bus mode, set sio0 to ffh with bit 7 (bsye) of the serial bus interface control register (sbic) set to 0. reset input makes sio0 undefined. caution in the i 2 c bus mode, do not execute write instructions to si0 while wup (bit 5 of serial operation mode register 0 (csim0)) = 1. data can be received when using the wake-up function (wup = 1) even if write instruction to sio0 is not executed. for the wake-up function, refer to 18.4.4 (1) (c) wake-up function. (2) slave address register (sva) this is an 8-bit register to set the slave address value for connection of a slave device to the serial bus. sva is set with an 8-bit memory manipulation instruction. this register is not used in the 3-wire serial i/o mode. the master device outputs a slave address for selection of a particular slave device to the connected slave device. these two data (the slave address output from the master device and the sva value) are compared with an address comparator. if they match, the slave device has been selected. in that case, bit 6 (coi) of serial operating mode register 0 (csim0) becomes 1. address of the data of lsb-masked high-order 7 bits can be compared by setting bit 4 (svam) of the interrupt timing specify register (sint). if no matching is detected in address reception, bit 2 (reld) of the serial bus interface control register (sbic) is cleared to 0. in the i 2 c bus mode, when bit 5 (wup) of csim0 is set (1), the wake-up function can be used. in this case, the interrupt request signal (intcsi0) is generated if the slave address output from the master and the sva value match (the interrupt request signal is generated also when a stop condition is detected). this interrupt request enables to recognize the generation of the communication request from the master device. set sic to 1 when using the wake-up function. further, when sva transmits data as master or slave device in the the i 2 c bus mode or 2-wire serial i/o mode, errors are detected if any. reset input makes sva undefined. (3) so0 latch this latch holds si0/sb0/sda0/p25 and so0/sb1/sda1/p26 pin levels. it can be directly controlled by software. (4) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception and to check whether 8-bit data has been transmitted/received. (5) serial clock control circuit this circuit controls serial clock supply to the serial i/o shift register 0 (sio0). when the internal system clock is used, the circuit also controls clock output to the sck0/scl/p27 pin. 371 chapter 18 serial interface channel 0 ( m pd78078y subseries) (6) interrupt request signal generator this circuit controls interrupt request signal generation. it generates interrupt request signals according to the settings of interrupt timing specification register (sint) bits 0 and 1 (wat0, wat1) and serial operation mode register 0 (csim0) bit 5 (wup), as shown in table 18-3. (7) acknowledge output circuit and stop condition/start condition/acknowledge detector these two circuits output and detect various control signals in the i 2 c mode. these do not operate in the 3-wire serial i/o mode and 2-wire serial i/o mode. table 18-3. serial interface channel 0 interrupt request signal generation serial transfer mode bsye wup wat1 wat0 acke description 3-wire or 2-wire serial i/o mode 0 0 0 0 0 an interrupt request signal is generated each time 8 serial clocks are counted. other than above setting prohibited i 2 c bus mode (transmit) 0 0 1 0 0 an interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). normally, during transmission the settings wat21, wat0 = 1, 0, are not used. they are used only when wanting to coordinate receive time and processing systematically using software. ack information is generated by the receiving side, thus acke should be set to 0 (disable). 1 1 0 an interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). ack information is generated by the receiving side, thus acke should be set to 0 (disable). other than above setting prohibited i 2 c bus mode (receive) 1 0 1 0 0 an interrupt request signal is generated each time 8 serial clocks are counted (8-clock wait). ack information is output by manipulating ackt by software after an interrupt request signal is generated. 1 1 0/1 an interrupt request signal is generated each time 9 serial clocks are counted (9-clock wait). to automatically generate ack information, preset acke to 1 before transfer start. however, in the case of the master, set acke to 0 (disable) before receiving the last data. 1 1 1 1 1 after address is received, if the values of the serial i/o shift register 0 (si00) and the slave address register (sva) match and if stop condition is detected, an interrupt request signal is generated. to automatically generate ack information, preset acke to 1 (enable) before transfer start. other than above s etting prohibited remark bsye: bit 7 of serial bus interface control register (sbic) acke: bit 5 of serial bus interface control register (sbic) 372 chapter 18 serial interface channel 0 ( m pd78078y subseries) 18.3 serial interface channel 0 control registers the following four types of registers are used to control serial interface channel 0. ? timer clock select register 3 (tcl3) ? serial operating mode register 0 (csim0) ? serial bus interface control register (sbic) ? interrupt timing specify register (sint) 373 chapter 18 serial interface channel 0 ( m pd78078y subseries) (1) timer clock select register 3 (tcl3) this register sets the serial clock of serial interface channel 0. tcl3 is set with an 8-bit memory manipulation instruction. reset input sets tcl3 to 88h. figure 18-3. timer clock select register 3 format caution when rewriting tcl3 to other data, stop the serial transfer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : bit 0 of oscillation mode selection register (osms) 4. figures in parentheses apply to operation with f x = 5.0 mhz. serial interface channel 0 serial clock selection tcl33 tcl32 tcl31 tcl30 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 f xx /2 9 f xx /2 10 f xx /2 11 f xx /2 12 mcs = 1 setting prohibited f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.77 khz) f x /2 10 (4.88 khz) f x /2 11 (2.44 khz) f x /2 12 (1.22 khz) m cs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) other than above setting prohibited serial interface channel 1 serial clock selection tcl37 tcl36 tcl35 tcl34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) other than above setting prohibited 6543210 7 symbol tcl3 tcl37 tcl36 tcl35 tcl34 tcl33 tcl32 tcl31 tcl30 ff43h 88h r/w address after reset r/w mcs = 0 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.77 khz) f x /2 10 (4.88 khz) f x /2 11 (2.44 khz) f x /2 12 (1.22 khz) f x /2 13 (0.61 khz) f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) serial clock in i 2 c bus mode serial clock in 2-wire or 3-wire serial i/o mode 374 chapter 18 serial interface channel 0 ( m pd78078y subseries) (2) serial operating mode register 0 (csim0) this register sets serial interface channel 0 serial clock, operating mode, operation enable/stop wake-up function and displays the address comparator match signal. csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. caution do not change the operation mode (3-wire serial i/o/2-wire serial i/o/i 2 c bus) while the operation of the serial interface channel 0 is enabled. stop the serial operation before changing the operation mode. 375 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-4. serial operating mode register 0 format notes 1. bit 6 (coi) is a read-only bit. 2. i 2 c bus mode, the clock frequency becomes 1/16 of that output from to2. 3. can be used as p25 (cmos input/output) when used only for transmission. 4. can be used freely as port function. 5. set bit 5 (sic) of the interrupt timing specify register (sint) to 1 when using the wake-up function (wup = 1). do not execute a write instruction to the serial i/o shift register 0 (sio0) while wup = 1. 6. when csie0 = 0, coi becomes 0. remark x : dont care pmxx : port mode register pxx : port output latch <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0/scl pin from off-chip 8-bit timer register 2 (tm2) output 0 r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 x 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/sda0/ p25 pin function so0/sb1/sda1/ p26 pin function sck0/scl/p27 pin function x 1 msb lsb 1x0001 note 3 3-wire serial l/o mode si0 (input) so0 (cmos output) sck0 (cmos input/output) note 3 2-wire serial l/o mode or i 2 c bus mode 0 sck0/scl (n-ch open-drain input/output) 1 11 x 0 x 0 0 x 0 x 0 0 1 1 note 4 note 4 note 4 note 4 msb p25 (cmos input/output) sb0/sda0 (n-ch open-drain input/output) sb1/sda1 (n-ch open-drain input/output) p26 (cmos input/output) note 3 wup 0 1 wake-up function control note 5 interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after detecting start condition (when cmdd = 1) matches the slave address register (sva) data in i 2 c bus mode r/w coi 0 1 slave address comparison result flag note 6 slave address register (sva) not equal to serial i/o shift register 0 (sio0) data slave address register (sva) equal to serial i/o shift register 0 (sio0) data r csie0 0 1 serial interface channel 0 operation control operation stopped operation enabled r/w note 2 376 chapter 18 serial interface channel 0 ( m pd78078y subseries) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt used for stop condition signal output. when relt = 1, so0 iatch is set to 1. after so0 latch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w note address after reset r/w cmdt used for start condition signal output. when cmdt = 1, so0 iatch is cleared to 0. after so0 latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w r reld stop condition detection set conditions (reld = 1) clear conditions (reld = 0) when stop condition signal is detected ?when transfer start instruction is executed ?if sio0 and sva values do not match in address reception ?when csie0 = 0 ?when reset input is applied r cmdd start condition detection clear conditions (cmdd = 0) ?when transfer start instruction is executed ?when stop condition signal is detected ?when csie0 = 0 ?when reset input is applied set conditions (cmdd = 1) when start condition signal is detected ackt used to generate the ack signal by software when 8-clock wait mode is selected. keeps sda0 (sda1) low from set instruction (ackt = 1) execution to the next fallin g edge of scl. also cleared to 0 upon start of serial interface transfer or when csie0 = 0. r/w (3) serial bus interface control register (sbic) this register sets serial bus interface operation and displays statuses. sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. figure 18-5. serial bus interface control register format (1/2) note bits 2, 3, and 6 (reld, cmdd and ackd) are read-only bits. remark csie0 : bit 7 of serial operating mode register 0 (csim0) 377 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-5. serial bus interface control register format (2/2) notes 1. setting should be performed before transfer. 2. if 8-clock wait mode is selected, the acknowledge signal at reception time must be output using ackt. 3. the busy mode can be canceled by start of serial interface transfer or reception of address signal. however, the bsye flag is not cleared to 0. 4. when using the wake-up function, set bsye to 1. remark csie0 : bit 7 of serial operating mode register 0 (csim0) acke acknowledge signal output control 0 disables acknowledge signal automatic output. (however, output with ackt is enabled) used for reception when 8-clock wait mode is selected or for transmission. note 2 enables acknowledge signal automatic output. outputs acknowledge signal in synchronization with the falling edge of the 9th scl clock cycle (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. used in reception with 9-clock wait mode selected. 1 r/w r ackd acknowledge detection clear conditions (ackd = 0) while executing the transfer start instruction ?when csie0 = 0 ?when reset input is applied set conditions (ackd = 1) ?when acknowledge signal (ack) is detected at the rising edge of scl clock after completion of transfer bsye control of n-ch open-drain output for transmission in i 2 c bus mode 0 output enabled (transmission) r/w note 3 1 note 4 output disabled (reception) note 1 378 chapter 18 serial interface channel 0 ( m pd78078y subseries) (4) interrupt timing specify register (sint) this register sets the bus release interrupt and address mask functions and displays the sck0/scl pin level status. sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. figure 18-6. interrupt timing specify register format (1/2) notes 1. bit 6 (cld) is a read-only bit. 2. when not using the i 2 c mode, set clc to 0. used in i 2 c bus mode. make scl pin enter high-impedance state unless serial transfer is being performed. (except for clock line which is kept high) used to enable master device to generate start condition and stop condition signals. <6> <5> <4> <3> <2> 1 0 7 symbol sint 0 cld sic svam clc wrel wat1 wat0 ff63h 00h r/w note 1 address after reset r/w wrel 0 wait state has been cancelled. cancels wait state. automatically cleared to 0 when the state is cancelled. (used to cancel wait state by means of wat0 and wat1.) clc 0 1 clock level control note 2 used in i 2 c bus mode. make output level of scl pin low unless serial transfer is being performed. r/w 1 wait sate cancellation control r/w wat1 0 1 wait and interrupt control generates interrupt service request at rising edge of 8th sck0 clock cycle. (keeping clock output in high impedance) r/w wat0 0 0 used in i 2 c bus mode. (8-clock wait) generates interrupt service request at rising edge of 8th sck0 clock cycle. (in the case of master device, makes scl output low to enter wait state after 8 clock pulses are output. in the case of slave device, makes scl output low to request wait state after 8 clock pulses are input.) 1 1 used in i 2 c bus mode. (9-clock wait) generates interrupt service request at rising edge of 9th sck0 clock cycle. (in the case of master device, makes scl output low to enter wait state after 9 clock pulses are output. in the case of slave device, makes scl output low to request wait state after 9 clock pulses are input.) 0 setting prohibited 1 379 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-6. interrupt timing specify register format (2/2) notes 1. when using wake-up function in the i 2 c mode, set sic to 0. 2. when csie0 = 0, cld becomes 0. remark sva : slave address register csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of serial operating mode register 0 (csim0) svam 0 1 sva bit to be used as slave address bits 0 to 7 bits 1 to 7 sic 0 intcsi0 interrupt cause selection note 1 csiif0 is set to 1 upon termination of serial interface channel 0 transfer csiif0 is set to 1 upon stop condition detection or termination of serial interface channel 0 transfer cld 0 1 sck0/scl pin level note 2 low level high level r/w r/w r 1 380 chapter 18 serial interface channel 0 ( m pd78078y subseries) 18.4 serial interface channel 0 operations the following four operating modes are available to the serial interface channel 0. ? operation stop mode ? 3-wire serial i/o mode ? 2-wire serial i/o mode ?i 2 c (inter ic) bus mode 18.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. thus, power consumption can be reduced. the serial i/o shift register 0 (sio0) does not carry out shift operation either and thus it can be used as ordinary 8-bit register. in the operation stop mode, the p25/si0/sb0/sda0, p26/so0/sb1/sda1 and p27/sck0/scl pins can be used as general input/output ports. (1) register setting the operation stop mode is set with the serial operating mode register 0 (csim0). csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 ff60h 00h r/w address after reset r/w csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 381 chapter 18 serial interface channel 0 ( m pd78078y subseries) <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output 0 2-wire serial i/o mode (see 18.4.3 2-wire serial i/o mode operation .) r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 x 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/sda0 /p25 pin function so0/sb1/sda1 /p26 pin function sck0/scl/p27 pin function x 11 wup 0 1 wake-up function control interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after detecting start condition (when cmdd = 1) matches the slave address register (sva) data in i 2 c bus mode r/w 1 msb lsb 1x0001 note 2 3-wire serial l/o mode si0 (input) so0 (cmos output) sck0 (cmos input/output) i 2 c bus mode (see 18.4.4 i 2 c bus mode operation .) note 2 note 3 note 2 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 or 18.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is valid for connection of peripheral i/o units and display controllers which incorporate a conventional synchronous clocked serial interface as is the case with the 75x/xl, 78k, and 17k series. communication is carried out with three lines of serial clock (sck0), serial output (so0), and serial input (si0). (1) register setting the 3-wire serial i/o mode is set with the serial operating mode register 0 (csim0) and serial bus interface control register (sbic). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. notes 1. bit 6 (coi) is a read-only bit. 2. can be used as p25 (cmos input/output) when used only for transmission. 3. set wup to 0 when the 3-wire serial i/o mode is selected. remark x : dont care pmxx : port mode register pxx : port output latch 382 chapter 18 serial interface channel 0 ( m pd78078y subseries) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so0 iatch is set to 1. after so0 iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so0 iatch is cleared to 0. after so0 latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. remark csie0 : bit 7 of serial operating mode register 0 (csim0) 383 chapter 18 serial interface channel 0 ( m pd78078y subseries) (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. bit-wise data transmission/ reception is carried out in synchronization with the serial clock. shift operation of the serial i/o shift register 0 (sio0) is carried out at the falling edge of the serial clock (sck0). the transmitted data is held in the so0 latch and is output from the so0 pin. the received data input to the si0 pin is latched in sio0 at the rising edge of sck0. upon termination of 8-bit transfer, sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 18-7. 3-wire serial i/o mode timings the so0 pin is a cmos output pin and outputs current so0 latch statuses. thus, the so0 pin output status can be manipulated by setting the bit 0 (relt) and bit 1 (cmdt) of the serial bus interface control register (sbic). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 18.4.7 sck0/scl/p27 pin output manipulation ). (3) other signals figure 18-8 shows relt and cmdt operations. figure 18-8. relt and cmdt operations relt cmdt so0 latch si0 sck0 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so0 do7 do6 do5 do4 do3 do2 do1 do0 csiif0 transfer start at the falling edge of sck0 end of transfer 384 chapter 18 serial interface channel 0 ( m pd78078y subseries) (4) msb/lsb switching as the start bit the 3-wire serial i/o mode enables to select transfer to start from msb or lsb. figure 18-9 shows the configuration of the serial i/o shift register 0 (sio0) and internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. msb/lsb switching as the start bit can be specified with bit 2 (csim02) of the serial operating mode register 0 (csim0). figure 18-9. circuit of switching in transfer bit order start bit switching is realized by switching the bit order for data write to sio0. the sio0 shift order remains unchanged. thus, msb-first and lsb-first must be switched before writing data to the shift register. (5) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1. ? internal serial clock is stopped or sck0 is a high level after 8-bit serial transfer. caution if csie0 is set to 1 after data write to sio0, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si0 shift register 0 (sio0) read/write gate so0 sck0 dq so0 latch 385 chapter 18 serial interface channel 0 ( m pd78078y subseries) 18.4.3 2-wire serial i/o mode operation the 2-wire serial i/o mode can cope with any communication format by program. communication is basically carried out with two lines of serial clock (sck0) and serial data input/output (sb0 or sb1). figure 18-10. serial bus configuration example using 2-wire serial i/o mode master sck0 slave sb0 (sb1) sck0 sb0 (sb1) v dd v dd 386 chapter 18 serial interface channel 0 ( m pd78078y subseries) <6><5>43210 <7> symbol csim0 csie0 coi wup csim04 csim03 csim02 csim01 csim00 csim01 0 1 serial interface channel 0 clock selection input clock to sck0 pin from off-chip 8-bit timer register 2 (tm2) output r/w 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) csim 04 0 csim00 x 0 1 ff60h 00h r/w note 1 address after reset r/w r/w csim 03 csim 02 pm25 p25 pm26 p26 pm27 p27 operation mode start bit si0/sb0/sda0 /p25 pin function so0/sb1/sda1 /p26 pin function sck0/scl/p27 pin function x wup 0 1 wake-up function control interrupt request signal generation with each serial transfer in any mode interrupt request signal generation when the address received after detecting start condition (when cmdd = 1) matches the slave address register (sva) data in i 2 c bus mode r/w 2-wire serial l/o mode or i 2 c bus mode 0 sck0/scl (n-ch open-drain input/output) 1 11 x 0 x 0 0 x 0 x 0 0 1 1 note 2 note 2 note 2 note 2 msb p25 (cmos input/output sb0/sda0 (n-ch open-drain input/output) sb1/sda1 (n-ch open-drain input/output) p26 (cmos input/output) 3-wire serial i/o mode (see 18.4.2 3-wire serial i/o mode operation .) note 3 coi 0 slave address comparison result flag note 4 slave address register (sva) not equal to serial i/o shift register 0 (sio0) data slave address register (sva) equal to serial i/o shift register 0 (sio0) data r 1 csie0 0 serial interface channel 0 operation control operation stopped operation enabled r/w 1 (1) register setting the 2-wire serial i/o mode is set with the serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specify register (sint). (a) serial operating mode register 0 (csim0) csim0 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim0 to 00h. notes 1. bit 6 (coi) is a read-only bit. 2. can be used freely as port function. 3. set wup to 0 when the 2-wire serial i/o mode is selected. 4. when csie0 = 0, coi becomes 0. remark x : dont care pmxxx : port mode register pxx : port output latch 387 chapter 18 serial interface channel 0 ( m pd78078y subseries) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ackt cmdd reld cmdt relt relt when relt = 1, so0 iatch is set to 1. after so0 iatch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w ff61h 00h r/w address after reset r/w cmdt when cmdt = 1, so0 iatch is cleared to 0. after so0 latch clearance, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w (b) serial bus interface control register (sbic) sbic is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. remark csie0 : bit 7 of serial operating mode register 0 (csim0) (c) interrupt timing specify register (sint) sint is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. notes 1. bit 6 (cld) is a read-only bit. 2. when csie0 = 0, cld becomes 0. caution set bits 0 to 3 to 0 when the 2-wire serial i/o mode is selected. remark csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> 1 0 7 symbol sint 0 cld sic clc wrel wat1 wat0 ff63h 00h r/w note 1 address after reset r/w svam sic 0 intcsi0 interrupt factor selection csiif0 is set upon termination of serial interface channel 0 transfer csiif0 is set upon bus release detection or termination of serial interface channel 0 transfer cld 0 1 sck0 pin level note 2 low level high level r/w r 1 388 chapter 18 serial interface channel 0 ( m pd78078y subseries) (2) communication operation the 2-wire serial i/o mode is used for data transmission/reception in 8-bit units. data transmission/reception is carried out bit-wise in synchronization with the serial clock. shift operation of the serial i/o shift register 0 (sio0) is carried out in synchronization with the falling edge of the serial clock (sck0). the transmit data is held in the so0 latch and is output from the sb0/sda0/ p25 (or sb1/sda1/p26) pin on an msb-first basis. the receive data input from the sb0 (or sb1) pin is latched into sio0 at the rising edge of sck0. upon termination of 8-bit transfer, the sio0 operation stops automatically and the interrupt request flag (csiif0) is set. figure 18-11. 2-wire serial i/o mode timings the sb0 (or sb1) pin specified for the serial data bus is an n-ch open-drain input/output and thus it must be externally connected to a pull-up resistor. because it is necessary to set n-ch open-drain output to high- impedance state for data reception, write ffh to sio0 in advance. the sb0 (or sb1) pin generates the so0 latch status and thus the sb0 (or sb1) pin output status can be manipulated by setting the bit 0 (relt) and bit 1 (cmdt) of the serial bus interface control register (sbic). however, do not carry out this manipulation during serial transfer. control the sck0 pin output level in the output mode (internal system clock mode) by manipulating the p27 output latch (refer to 18.4.7 sck0/scl/p27 pin output manipulation ). 123 4 5 6 7 8 sck0 d7 d6 d5 d4 d3 d2 d1 d0 sb0 (sb1) csiif0 transfer start at the falling edge of sck0 end of transfer 389 chapter 18 serial interface channel 0 ( m pd78078y subseries) (3) other signals figure 18-12 shows relt and cmdt operations. figure 18-12. relt and cmdt operations (4) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 0 (sio0) when the following two conditions are satisfied. ? serial interface channel 0 operation control bit (csie0) = 1 ? internal serial clock is stopped or sck0 is at high level after 8-bit serial transfer. cautions 1. if csie0 is set to 1 after data write to sio0, transfer does not start. 2. because the n-ch open-drain output must be set to high-impedance state for data reception, write ffh to sio0 in advance. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif0) is set. (5) error detection in the 2-wire serial i/o mode, the serial bus sb0 (sb1) status being transmitted is fetched into the destination device, that is, the serial i/o shift register 0 (sio0). thus, transmit error can be detected in the following way. (a) method of comparing sio0 data before transmission to that after transmission in this case, if two data differ from each other, a transmit error is judged to have occurred. (b) method of using the slave address register (sva) transmit data is set to both sio0 and sva and is transmitted. after termination of transmission, coi bit (match signal coming from the address comparator) of the serial operating mode register 0 (csim0) is tested. if 1, normal transmission is judged to have been carried out. if 0, a transmit error is judged to have occurred. relt cmdt so0 latch 390 chapter 18 serial interface channel 0 ( m pd78078y subseries) 18.4.4 i 2 c bus mode operation the i 2 c bus mode is provided for when communication operations are performed between a single master device and multiple slave devices. this mode configures a serial bus that includes only a single master device, and is based on the clocked serial i/o format with the addition of bus configuration functions, which allows the master device to communicate with a number of (slave) devices using only two lines: serial clock (scl) line and serial data bus (sda0 or sda1) line. consequently, when the user plans to configure a serial bus which includes multiple microcontrollers and peripheral devices, using this configuration results in reduction of the required number of port pins and on-board wires. in the i 2 c bus specification, the master sends start condition, data, and stop condition signals to slave devices through the serial data bus, while slave devices automatically detect and distinguish the type of signals due to the signal detection function incorporated as hardware. this simplifies the application program to control i 2 c bus. an example of a serial bus configuration is shown in figure 18-13. this system below is composed of cpus and peripheral ics having serial interface hardware that complies with the i 2 c bus specification. note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open- drain buffers are used for the serial clock pin (scl) and the serial data bus pin (sda0 or sda1) on the i 2 c bus. the signals used in the i 2 c bus mode are described in table 18-4. figure 18-13. example of serial bus configuration using i 2 c bus scl sda0 (sda1) scl sda0 (sda1) scl sda0 (sda1) scl sda slave ic slave cpu2 slave cpu1 master cpu v dd serial clock serial data bus v dd 391 chapter 18 serial interface channel 0 ( m pd78078y subseries) (1) i 2 c bus mode functions in the i 2 c bus mode, the following functions are available. (a) automatic identification of serial data slave devices automatically detect and identifies start condition, data, and stop condition signals sent in series through the serial data bus. (b) chip selection by specifying device addresses the master device can select a specific slave device connected to the i 2 c bus and communicate with it by sending in advance the address data corresponding to the destination device. (c) wake-up function when address data is sent from the master device, slave devices compare it with the value registered in their internal slave address registers. if the values in one of the slave devices match, the slave device internally generates an interrupt request signal to terminate the current processing and communicates with the master device (an interrupt request generates also when a stop condition is detected). therefore, cpus other than the selected slave device on the i 2 c bus can operate independently during the serial communication. (d) acknowledge signal (ack) control function the master device and a slave device send and receive acknowledge signals to confirm that the serial communication has been executed normally. (e) wait signal (wait) control function when a slave device is preparing for data transmission or reception and requires more waiting time, the slave device outputs a wait signal on the bus to inform the master device of the wait status. (2) i 2 c bus definition this section describes the format of serial data communications and functions of the signals used in the i 2 c bus mode. first, the transfer timings of the start condition, data, and stop condition signals, which are output onto the signal data bus of the i 2 c bus, are shown in figure 18-14. figure 18-14. i 2 c bus serial data transfer timing the start condition, slave address, and stop condition signals are output by the master. the acknowledge signal (ack) is output by either the master or the slave device (normally by the device which has received the 8-bit data that was sent). a serial clock (scl) is continuously supplied from the master device. 1-7 8 9 1-7 8 9 1-7 8 9 address r/w ack data ack data ack scl start condition sda0 (sda1) stop condition 392 chapter 18 serial interface channel 0 ( m pd78078y subseries) (a) start condition when the sda0 (sda1) pin level is changed from high to low while the scl pin is high, this transition is recognized as the start condition signal. this start condition signal, which is created using the scl and sda0 (or sda1) pins, is output from the master device to slave devices to initiate a serial transfer. refer to 18.4.5 cautions on use of i 2 c bus mode , for details of the start condition output. the start condition signal is detected by hardware incorporated in slave devices. figure 18-15. start condition (b) address the 7 bits following the start condition signal are defined as an address. the 7-bit address data is output by the master device to specify a specific slave from among those connected to the bus line. each slave device on the bus line must therefore have a different address. therefore, after a slave device detects the start condition, it compares the 7-bit address data received and the data of the slave address register (sva). after the comparison, only the slave device in which the data are a match becomes the communication partner, and subsequently performs communication with the master device until the master device sends a start condition or stop condition signal. figure 18-16. address (c) transfer direction specification the 1 bit that follows the 7-bit address data will be sent from the master device, and it is defined as the transfer direction specification bit. if this bit is 0, it is the master device which will send data to the slave. if it is 1, it is the slave device which will send data to the master. figure 18-17. transfer direction specification h scl sda0 (sda1) 1234567 a6 a5 a4 a3 a2 a1 a0 r/w address scl sda0 (sda1) 234567 a6 a5 a4 a3 a2 a1 a0 r/w transfer direction specification scl 8 1 sda0 (sda1) 393 chapter 18 serial interface channel 0 ( m pd78078y subseries) ? scl sda0 (sda1) (d) acknowledge signal (ack) the acknowledge signal indicates that the transferred serial data has definitely been received. this signal is used between the sending side and receiving side devices for confirmation of correct data transfer. in principle, the receiving side device returns an acknowledge signal to the sending device each time it receives 8-bit data. the only exception is when the receiving side is the master device and the 8-bit data is the last transfer data; the master device outputs no acknowledge signal in this case. the sending side that has tranferred 8-bit data waits for the acknowledge signal which will be sent from the receiving side. if the sending side device receives the acknowledge signal, which means a successful data transfer, it proceeds to the next processing. if this signal is not sent back from the slave device, this means that the data sent has not been received by the slave device, and therefore the master device outputs a stop condition signal to terminate subsequent transmissions. figure 18-18. acknowledge signal (e) stop condition if the sda0 (sda1) pin level changes from low to high while the scl pin is high, this transition is defined as a stop condition signal. the stop condition signal is output from the master to the slave device to terminate a serial transfer. the stop condition signal is detected by hardware incorporated in the slave device. figure 18-19. stop condition 1 234567 a6 a5 a4 a3 a2 a1 a0 r/w scl sda0 (sda1) 9 8 ack 394 chapter 18 serial interface channel 0 ( m pd78078y subseries) (f) wait signal (wait) the wait signal is output by a slave device to inform the master device that the slave device is in wait state due to preparing for transmitting or receiving data. during the wait state, the slave device continues to output the wait signal by keeping the scl pin low to delay subsequent transfers. when the wait state is released, the master device can start the next transfer. for the releasing operation of slave devices, refer to 18.4.5 cautions on use of i 2 c bus mode . figure 18-20. wait signal (a) wait of 8 clock cycles (b) wait of 9 clock cycles scl of master device d2 d1 d0 ack d7 output by manipulating ackt 6789 1 3 24 d6 d5 d4 set low because slave device drives low, though master device returns to hi-z state. no wait is inserted after 9th clock cycle. (and before master device starts next transfer.) scl of slave device scl sda0 (sda1) scl of master device set low because slave device drives low, though master device returns to hi-z state. scl of slave device scl d2 d1 d0 ack d7 output based on the value set in acke in advance 6789 23 d6 d5 1 sda0 (sda1) 395 chapter 18 serial interface channel 0 ( m pd78078y subseries) (3) register setting the i 2 c bus mode is set with the serial operating mode register 0 (csim0), the serial bus interface control register (sbic), and the interrupt timing specify register (sint). (a) serial operating mode register 0 (csim0) csim0 is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets 00h. r/w csim01 csim00 serial interface channel 0 clock selection 0 x input clock from off-chip to scl pin 1 0 8-bit timer register 2 (tm2) output note 2 1 1 clock specified with bits 0 to 3 of timer clock select register 3 (tcl3) r/w csim csim csim pm25 p25 pm26 p26 pm27 p27 operation start si0/sb0/sda0/ so0/sb1/sda1/ sck0/scl/p27 04 03 02 mode bit p25 pin function p26 pin function pin function 0 x 3-wire serial i/o mode (see 18.4.2 3-wire serial i/o mode operation ) 1 1 0 x x 0 0 0 1 2-wire msb p25 sb1/sda1 sck0/scl note 3 note 3 serial i/o or (cmos i/o) n-ch open- n-ch open- i 2 c bus mode drain i/o drain i/o 1 1 1 0 0 x x 0 1 2-wire msb sb0/sda0 p26 sck0/scl note 3 note 3 serial i/o or n-ch open- (cmos i/o) n-ch open- i 2 c bus mode drain i/o drain i/o r/w wup wake-up function control note 4 0 interrupt request signal generation with each serial transfer in any mode 1 in i 2 c bus mode, interrupt request signal is generated when the address data received after start condition detection (when cmdd = 1) matches data in slave address register (sva). r coi slave address comparison result flag note 5 0 slave address register (sva) not equal to data in serial i/o shift register 0 (sio0) 1 slave address register (sva) equal to data in serial i/o shift register 0 (sio0) r/w csie0 serial interface channel 0 operation control 0 stops operation. 1 enables operation. notes 1. bit 6 (coi) is a read-only bit. 2. in the i 2 c bus mode, the clock frequency is 1/16 of the clock frequency output by to2. 3. can be used freely as a port. 4. set bit 5 (sic) of the interrupt timing specify register (sint) to 1 when using the wake-up function (wup = 1). do not execute a write instruction to the serial i/o shift register 0 (sio0) while wup = 1. 5. when csie0 = 0, coi is 0. remark x : dont care pmxxx : port mode register pxx : port output latch <6><5>43210 <7> symbol csim0 ff60h 00h r/w note 1 address after reset r/w csie0 coi wup csim04 csim03 csim02 csim01 csim00 396 chapter 18 serial interface channel 0 ( m pd78078y subseries) <6> <5> <4> <3> <2> <1> <0> <7> symbol sbic bsye ackd acke ff61h 00h r/w note1 address after reset r/w ackt cmdd reld cmdt relt (b) serial bus interface control register (sbic) sbic is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets sbic to 00h. r/w relt use for stop condition output. when relt = 1, so0 latch is set to 1. after so0 latch setting, automatically cleared to 0. also cleared to 0 when csie0 = 0. r/w cmdt use for start condition output. when cmdt = 1, so0 latch is cleared to 0. after clearing so0 latch, automatically cleared to 0. also cleared to 0 when csie0 = 0. r reld stop condition detection 0 clear conditions ? when transfer start instruction is executed ? if sio0 and sva values do not match in address reception ? when csie0 = 0 ? when reset input is applied 1 setting condition ? when stop condition is detected r cmdd start condition detection 0 clear conditions ? when transfer start instruction is executed ? when stop condition is detected ? when csie0 = 0 ? when reset input is applied 1 setting condition ? when start condition is detected r/w ackt sda0 (sda1) is set to low after the set instruction execution (ackt = 1) before the next scl falling edge. used for generating an ack signal by software if the 8-clock wait mode is selected. cleared to 0 if csie = 0 when a transfer by the serial interface is started. r/w acke acknowledge signal automatic output control note 2 0 disabled (with ackt enabled). used when receiving data in the 8-clock wait mode or when transmitting data. note 3 1 enabled. after completion of transfer, acknowledge signal is output in synchronization with the 9th falling edge of scl clock (automatically output when acke = 1). however, not automatically cleared to 0 after acknowledge signal output. used for reception when the 9-clock wait mode is selected. r ackd acknowledge detection 0 clear conditions ? when transfer start instruction is executed ? when csie0 = 0 ? when reset input is applied 1 set conditions ? when acknowledge signal is detected at the rising edge of scl clock after completion of transfer r/w bsye control of n-ch open-drain output for transmission in i 2 c bus mode note 5 note 4 0 output enabled (transmission) 1 output disabled (reception) notes 1. bits 2, 3, and 6 (reld, cmdd, ackd) are read-only bits. 2. this setting must be performed prior to transfer start. 3. in the 8-clock wait mode, use ackt for output of the acknowledge signal after normal data reception. 4. the busy mode can be released by the start of a serial interface transfer or reception of an address signal. however, the bsye flag is not cleared. 5. when using the wake-up function, set bsye to 1. remark csie0 : bit 7 of serial operating mode register 0 (csim0) 397 chapter 18 serial interface channel 0 ( m pd78078y subseries) (c) interrupt timing specification register (sint) sint is set by the 1-bit or 8-bit memory manipulation instruction. reset input sets sint to 00h. r/w wat1 wat0 interrupt control by wait note 2 0 0 interrupt service request is generated on rise of 8th sck0 clock cycle (clock output is high impedance). 0 1 setting prohibited 1 0 used in i 2 c bus mode (8-clock wait) generates an interrupt service request on rise of 8th scl clock cycle. (in case of master device, scl pin is driven low after output of 8 clock cycles, to enter the wait state. in case of slave device, scl pin is driven low after input of 8 clock cycles, to require the wait state.) 1 1 used in i 2 c bus mode (9-clock wait) generates an interrupt service request on rise of 9th scl clock cycle. (in case of master device, scl pin is driven low after output of 9 clock cycles, to enter the wait state. in case of slave device, scl pin is driven low after input of 9 clock cycles, to require the wait state.) r/w wrel wait release control 0 indicates that the wait state has been released. 1 releases the wait state. automatically cleared to 0 after releasing the wait state. this bit is used to release the wait state set by means of wat0 and wat1. r/w clc clock level control 0 used in i 2 c bus mode. in cases other than serial transfer, scl pin output is driven low. 1 used in i 2 c bus mode. in cases other than serial transfer, scl pin output is set to high impedance. (clock line is held high.) used by master device to generate the start condition and stop condition signals. r/w svam sva bits used as slave address 0 bits 0 to 7 1 bits 1 to 7 r/w sic intcsi0 interrupt source selection note 3 0 csiif0 is set to 1 after end of serial interface channel 0 transfer. 1 csiif0 is set to 1 after end of serial interface channel 0 transfer or when stop condition is detected. r cld scl pin level note 4 0 low level 1 high level notes 1. bit 6 (cld) is read-only. 2. when the i 2 c bus mode is used, set 1 and 0, or 1 and 1 in wat0 and wat1, respectively. 3. when using the wake-up function in i 2 c mode, set sic to 1. 4. when csie0 = 0, cld is 0. remark sva : slave address register csiif0 : interrupt request flag corresponding to intcsi0 csie0 : bit 7 of serial operating mode register 0 (csim0) <6> <5> <4> <3> <2> 1 0 7 symbol sint 0 cld sic ff63h 00h r/w note 1 address after reset r/w svam clc wrel wat1 wat0 398 chapter 18 serial interface channel 0 ( m pd78078y subseries) (4) various signals a list of signals in the i 2 c bus mode is given in table 18-4. table 18-4. signals in i 2 c bus mode signal name description start condition definition : sda0 (sda1) falling edge when scl is high ( note 1 ) function : indicates that serial communication starts and subsequent data are address data. signaled by : master signaled when : cmdt is set. affected flag(s) : cmdd (is set.) stop condition definition : sda0 (sda1) rising edge when scl is high ( note 1 ) function : indicates end of serial transmission. signaled by : master signaled when : relt is set. affected flag(s) : reld (is set) and cmdd (is cleared) acknowledge signal (ack) definition : low level of sda0 (sda1) pin during one scl clock cycle after serial reception function : indicates completion of reception of 1 byte. signaled by : master or slave signaled when : ackt is set with acke = 1. affected flag(s) : ackd (is set.) wait (wait) definition : low-level signal output to scl function : indicates state in which serial reception is not possible. signaled by : slave signaled when : wat1, wat0 = 1x. affected flag(s) : none serial clock (scl) definition : synchronization clock for output of various signals function : serial communication synchronization signal. signaled by : master signaled when : see note 2 below. affected flag(s) : csiif0. also see note 3 below. address (a6 to a0) definition : 7-bit data synchronized with scl immediately after start condition signal function : indicates address value for specification of slave on serial bus. signaled by : master signaled when : see note 2 below. affected flag(s) : csiif0. also see note 3 below. transfer direction (r/w) definition : 1-bit data output in synchronization with scl after address output function : indicates whether data transmission or reception is to be performed. signaled by : master signaled when : see note 2 below. affected flag(s) : csiif0. also see note 3 below. data (d7 to d0)) definition : 8-bit data synchronized with scl, not immediately after start condition function : contains data actually to be sent. signaled by : master or slave signaled when : see note 2 below. affected flag(s) : csiif0. also see note 3 below. notes 1. the level of the serial clock can be controlled by clc of the interrupt timing specify register (sint). 2. execution of instruction to write data to sio0 when csie0 = 1 (serial transfer start directive). in the wait state, the serial transfer operation will be started after the wait state is released. 3. if the 8-clock wait is selected when wup = 0, csiif0 is set at the rising edge of the 8th clock cycle of scl. if the 9-clock wait is selected when wup = 0, csiif0 is set at the rising edge of the 9th clock cycle of scl. if wup = 1, csiif0 is set when an address is received and the address matches the slave address register (sva) value and when a stop condition is detected. 399 chapter 18 serial interface channel 0 ( m pd78078y subseries) v dd v dd scl sda0(sda1) master device clock output (clock input) data output data input slave devices (clock output) clock input data output data input scl sda0(sda1) (5) pin configurations the configurations of the serial clock pin scl and the serial data bus pins sda0 (sda1) are shown below. (a) scl pin for serial clock input/output dual-function pin. <1> master .... n-ch open-drain output <2> slave ...... schmitt input (b) sda0 (sda1) serial data input/output dual-function pin. uses n-ch open-drain output and schmitt-input buffers for both master and slave devices. note that pull-up resistors are required to connect to both serial clock line and serial data bus line, because open-drain buffers are used for the serial clock pin (scl) and the serial data bus pin (sda0 or sda1) on the i 2 c bus. figure 18-21. pin configuration caution because the n-ch open-drain output must be in the high-impedance state during data reception, set bit 7 (bsye) of the serial bus interface control register (sbic) to 1 before writing ffh to the serial i/o shift register 0 (sio0). however, do not write ffh to the sio0 during data reception when using the wake-up function (when bit 5 (wup) of the serial operation mode register 0 (csim0)). n-ch open-drain always enters the high-impedance state even if ffh is not written to sio0. 400 chapter 18 serial interface channel 0 ( m pd78078y subseries) (6) address match detection method in the i 2 c mode, the master can select a specific slave device by sending slave address data. address match detection is performed automatically by the slave device hardware. a slave device address has a slave register (sva), and compares its contents and the slave address sent from the master device. if they match and the wake-up function specification (wup) bit is then 1, csiif0 is set (also when a stop condition is detected). when using the wake-up function, set sic to 1. caution whether a slave is selected or not is detected by the matching of the data (address) received after start condition. the matching detection interrupt request (intcsi0) of the address generated in the wup = 1 state is normally used for detecting the matching of the data. therefore, detection of whether a slave is selected or not using slave address must be performed in the wup = 1 state. (7) error detection in the i 2 c bus mode, transmission error can be detected by the following methods because the serial bus sda0 (sda1) status during transmission is also taken into the serial i/o shift register 0 (sio0) of the transmitting device. (a) comparison of sio0 data before and after transmission in this case, a transmission error is judged to have occurred if the two data values are different. (b) using the slave address register (sva) transmit data is set in sio0 and sva before transmission is performed. after transmission, the coi bit (match signal from the address comparator) of serial operating mode register 0 (csim0) is tested: 1 indicates normal transmission, and 0 indicates a transmission error. (8) communication operation in the i 2 c bus mode, the master selects the slave device to be communicated with from among multiple devices by outputting address data onto the serial bus. after the slave address data, the master sends the r/w bit which indicates the data transfer direction, and starts serial communication with the selected slave device. data communication timing charts are shown in figures 18-22 and 18-23. in the transmitting device, the serial i/o shift register 0 (sio0) shifts transmission data to the so latch in synchronization with the falling edge of the serial clock (scl), the so0 latch outputs the data on an msb-first basis from the sda0 or sda1 pin to the receiving device. in the receiving device, the data input from the sda0 or sda1 pin is taken into the sio0 in synchronization with the rising edge of scl. 401 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-22. example of communication from master to slave (with 9-clock wait selected for both master and slave) (1/3) (a) start condition - address l l l 1 a5 a4 a3 a2 a1 a0 w ack a6 2345678 d7 d6 d5 d4 d3 12345 9 l l l l l sio0 <- address sio0 <- data h l l l l l l l h h h h sio0 <- ffh sio0 write coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 sio0 write coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 processing in master device transfer line processing in slave device 402 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-22. example of communication from master to slave (with 9-clock wait selected for both master and slave) (2/3) (b) data l l l l 1 d5 d4 d3 d2 d1 d0 ack d6 d7 2345678 d7 d6 d5 d4 d3 12345 9 l l l l l l l sio0 <- data sio0 <- data h l l l l l l l h h h h sio0 <- ffh sio0 <- ffh sio0 write coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 sio0 write coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 processing in master device transfer line processing in slave device 403 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-22. example of communication from master to slave (with 9-clock wait selected for both master and slave) (3/3) (c) stop condition transfer line l l 1 d5 d4 d3 d2 d1 d0 ack d6 d7 2345678 a6 a5 a4 a3 1234 9 l l l l sio0 <- data sio0 <- address h l l l l h h h sio0 <- ffh sio0 write coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 sio0 write coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 sio0 <- ffh processing in master device processing in slave device 404 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-23. example of communication from slave to master (with 9-clock wait selected for both master and slave) (1/3) (a) start condition - address l l l 1 a0 a1 a2 a3 a4 a5 a6 r ack 2345678 d6 d7 d5 d4 d3 2 1345 9 l l l sio0 <- address sio0 <- ffh h l l l l l l l h h sio0 write coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 sio0 write coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 sio0 <- data processing in master device transfer line processing in slave device 405 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-23. example of communication from slave to master (with 9-clock wait selected for both master and slave) (2/3) (b) data l l l l h h l 1 d1 d0 d2 d3 d4 d5 d6 d7 ack 2345678 d6 d7 d5 d4 d3 2 1345 9 l l l sio0 <- ffh sio0 <- ffh h l l l l l l l l l l h h sio0 write coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 sio0 write coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 sio0 <- data sio0 <- data processing in master device transfer line processing in slave device 406 chapter 18 serial interface channel 0 ( m pd78078y subseries) figure 18-23. example of communication from slave to master (with 9-clock wait selected for both master and slave) (3/3) (c) stop condition l l 1 d1 d0 d2 d3 d4 d5 d6 d7 nak 2345678 a6 a5 a4 a3 1234 9 l l sio0 <- ffh processing in master device transfer line sio0 <- address h l l l l l l h h sio0 write coi ackd cmdd reld cld p27 scl sda0 wup bsye acke cmdt relt clc wrel sic intcsi0 sio0 write coi ackd cmdd reld cld p27 wup bsye acke cmdt relt clc wrel sic intcsi0 csie0 p25 pm25 pm27 processing in slave device sio0 <- data 407 chapter 18 serial interface channel 0 ( m pd78078y subseries) (9) start of transfer a serial transfer is started by setting transfer data in the serial i/o shift register 0 (sio0) if the following two conditions have been satisfied: ? the serial interface channel 0 operation control bit (csie0) = 1. ? after an 8-bit serial transfer, the internal serial clock is stopped or scl is low. cautions 1. set csie0 to 1 before writing data in sio0. setting csie0 to 1 after writing data in sio0 does not initiate transfer operation. 2. because the n-ch open-drain output must be high-impedance state during data reception, set bit 7 (bsye) of the serial bus interface control register (sbic) to 1 before writing ffh to sio0. however, do not write ffh to the sio0 during data reception when using the wake-up function (setting the bit 5 (wup) of the serial operation mode register 0 (csim0)). n-ch open-drain output always enters the high-impedance state even when ffh is not written to sio0. 3. if data is written to sio0 while the slave is in the wait state, that data is held. the transfer is started when scl is output after the wait state is cleared. when an 8-bit data transfer ends, serial transfer is stopped automatically and the interrupt request flag (csiif0) is set. 408 chapter 18 serial interface channel 0 ( m pd78078y subseries) 18.4.5 cautions on use of i 2 c bus mode (1) start condition output (master) the scl pin normally outputs a low-level signal when no serial clock is output. it is necessary to change the scl pin to high in order to output a start condition signal. set the bit 3 (clc) of the interrupt timing specify register (sint) to drive the scl pin high. after setting clc, clear clc to 0 and return the scl pin to low. if clc remains 1, no serial clock is output. if it is the master device which outputs the start condition and stop condition signals, confirm that cld is set to 1 after setting clc to 1; a slave device may have set scl to low (wait state). figure 18-24. start condition output scl clc cmdt cld sda0 (sda1) 409 chapter 18 serial interface channel 0 ( m pd78078y subseries) (2) slave wait release (slave transmission) the wait status of a slave is released by setting the wrel flag, which is bit 2 of the interrupt timing specify register (sint), or by executing a serial i/o shift register 0 (sio0) write instruction. if the slave sends data, the wait is immediately released by execution of an sio0 write instruction and the clock rises without the start transmission bit being output in the data line. therefore, manipulate the p27 output latch through the program as shown in figure 18-25 to transmit data correctly. at this time, control the low-level width ( a in figure 18-25 ) of the first serial clock at the timing used for setting the p27 output latch to 1 after execution of an sio0 write instruction. in addition, if the acknowledge signal from the master is not output (if data transmission from the slave is completed), set 1 in the wrel flag of sint and release the wait. for these timings, see figure 18-23 . figure 18-25. slave wait release (transmission) writing ffh to sio0 setting csiif0 setting ackd serial reception 9 a 23 a0 r ack d7 d6 d5 p27 output latch 1 setting csiif0 ack output serial transmission write data to sio0 p27 output latch 0 wait release software operation hardware operation scl software operation hardware operation transfer line master device operation slave device operation 1 sda0 (sda1) 410 chapter 18 serial interface channel 0 ( m pd78078y subseries) (3) slave wait release (slave reception) the wait status of a slave is released by setting the wrel flag, which is bit 2 of the interrupt timing specify register (sint), or by executing a serial i/o shift register 0 (sio0) write instruction. when a slave receives data, if the scl line immediately enters a high-impedance state due to a write to sio0, the slave may not receive the first bit of the data sent from the master. this is because sio0 cannot start operation if the scl line is in a high-impedance state during execution of a write instruction to sio0 (until the next instruction execution is started). therefore, manipulate the p27 output latch through the program as shown in figure 18-26 to receive data correctly. for these timings, see figure 18-22 . figure 18-26. slave wait release (reception) (4) reception completion of slave during processing of reception completion by a slave device, confirm the statuses of cmdd and coi (if cmdd = 1). this procedure is necessary to use the wake-up function normally. if an uncertain amount of data is sent from the master device, the slave device cannot determine whether the start condition signal or the data will be sent from the master. this may disable use of the wake-up function. writing data to sio0 setting csiif0 setting ackd serial transmission 923 a0 w ack d7 d6 d5 p27 output latch 1 setting csiif0 ack output serial reception write ffh to sio0 p27 output latch 0 wait release software operation hardware operation scl software operation hardware operation transfer line master device operation slave device operation 1 sda0 (sda1) 411 chapter 18 serial interface channel 0 ( m pd78078y subseries) 18.4.6 restrictions in i 2 c bus mode the following restrictions apply to the m pd78078y subseries. ? restrictions when used as slave device in i 2 c bus mode applicable models m pd78076y, 78078y, 78p078y, and ie-78078-r-em description when the wake-up function is executed (by setting the wup flag (bit 5 of the serial operation mode register 0 (csim0)) in the serial transfer status note , data between the other slaves and master will be judged as an address. if this data happens to coincide with the slave address of the m pd78078y subseries, the m pd78078y subseries will initiate communication, destroying the communication data. note the serial transfer status is the status in which the interrupt request flag (csiif0) is set because of the end of serial transfer after the serial i/o shift register 0 (sio0) has been written. preventive measure this restriction can be avoided by modifying the program. before executing the wake-up function, execute the following program that releases serial transfer status. to execute the wake-up function, do not execute an instruction that writes sio0. even if such an instruction is not executed, data can be received when the wake-up function is executed. this program releases the serial transfer status. to release the serial transfer status, the serial interface channel 0 must be set once in the operation stop status (by clearing the csie0 flag (bit 7 of the serial operation mode register (csim0) to 0). however, if the serial interface channel 0 is set in the operation stop status in the i 2 c bus mode, the scl pin output a high level and the sda0 (sda1) pin outputs a low level, affecting communication of the i 2 c bus. therefore, this program places the scl and sda0 (sda1) pins in the high-impedance state to prevent the i 2 c bus from being affected. in the example below, sda0 (/p25) is used as a serial data input/output pin. when sda1 (/p26) is used as the serial data input/output pin, take p2.5 and pm2.5 in the program below as p2.6 and pm2.6, respectively for the timing of each signal when this program is executed, refer to figure 18-22 . 412 chapter 18 serial interface channel 0 ( m pd78078y subseries) ? example of program releasing serial transfer status set1 p2.5 ; <1> set1 pm2.5 ; <2> set1 pm2.7 ; <3> clr1 csie0 ; <4> set1 csie0 ; <5> set1 relt ; <6> clr1 pm2.7 ; <7> clr1 p2.5 ; <8> clr1 pm2.5 ; <9> <1> prevents the sda0 pin from outputting a low level when the i 2 c bus mode is restored by the instruction in <5>. the output of the sda0 pin goes into a high-impedance state. <2> sets the p25 (/sda0) pin in the input mode to prevent the sda0 line from being affected when the port mode is set by the instruction in <4>. the p25 pin is set in the input mode when the instruction in <2> is executed. <3> sets the p27 (/scl) pin in the input mode to prevent the scl line from being affected when the port mode is set by the instruction in <4>. the p27 pin is set in the input mode when the instruction in <3> is executed. <4> changes the mode from the i 2 c bus mode to port mode. <5> restores the mode from the port mode to the i 2 c bus mode. <6> prevents the instruction in <8> from causing the sda0 pin to output a low level. <7> sets the p27 pin in the output mode because the p27 pin must be in the output mode in the i 2 c bus mode. <8> clears the output latch of the p25 pin to 0 because the output latch of the p25 pin must be cleared to 0 in the i 2 c bus mode. <9> sets the p25 pin in the output mode because the p25 pin must be in the output mode in the i 2 c bus mode. remark relt: bit 0 of serial bus interface control register (sbic) 413 chapter 18 serial interface channel 0 ( m pd78078y subseries) 18.4.7 sck0/scl/p27 pin output manipulation the sck0/scl/p27 pin enables static output by manipulating software in addition to normal serial clock output. the value of serial clocks can be set by software (si0/sb0/sda0 and so0/sb1/sda1 pins are controlled with the relt and cmdt bits of serial bus interface control register (sbic)). the sck0/scl/p27 pin output should be manipulated as described below. (1) in 3-wire serial i/o mode and 2-wire serial i/o mode the sck0/scl/p27 pin output level is manipulated by the p27 output latch. <1> set serial operating mode register 0 (csim0) (sck0 pin is set in the output mode and serial operation is enabled). while serial transfer is suspended, sck0 is set to 1. <2> manipulate the content of the p27 output latch by executing the bit manipulation instruction. figure 18-27. sck0/scl/p27 pin configuration to internal circuit sck0/scl/p27 p27 output latch when csie0 = 1 and csim01 and csim00 are 1 and 0, or 1 and 1. sck0 (1 when transfer stops) from serial clock control circuit set by bit manipulation instruction 414 chapter 18 serial interface channel 0 ( m pd78078y subseries) (2) in i 2 c bus mode the sck0/scl/p27 pin output level is manipulated by the clc bit of interrupt timing specify register (sint). <1> set serial operating mode register 0 (csim0) (scl pin is set in the output mode and serial operation is enabled). set 1 to the p27 output latch. while serial transfer is suspended, scl is set to 0. <2> manipulate the content of the clc bit of sint by executing the bit manipulation instruction. figure 18-28. sck0/scl/p27 pin configuration note the level of scl signal follows the contents of logic circuit shown in figure 18-29. figure 18-29. logic circuit of scl signal remarks 1. this figure shows the relationship of each signal, and does not show the internal circuit. 2. clc: bit 3 of interrupt timing specify register (sint) to internal circuit sck0/scl/p27 p27 output latch when csie0 = 1 and csim01 and csim00 are 1 and 0, or 1 and 1. scl from serial clock control circuit set 1 note scl clc (set by bit manipulation instruction) serial clock (low level when transfer stops) wait request signal 415 chapter 19 serial interface channel 1 19.1 serial interface channel 1 functions serial interface channel 1 employs the following three modes. ? operation stop mode ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function (1) operation stop mode this mode is used when serial transfer is not carried out to reduce power consumption. (2) 3-wire serial i/o mode (msb-/lsb-first switchable) this mode is used for 8-bit data transfer using three lines, each for serial clock (sck1), serial output (so1) and, serial input (si1). the 3-wire serial i/o mode enables simultaneous transmission/reception and so decreases the data transfer processing time. since the start bit of 8-bit data to undergo serial transfer is switchable between msb and lsb, connection is enabled with either start bit device. the 3-wire serial i/o mode is valid for connection of peripheral i/o units and display controllers which incorporate a conventional synchronous serial interface such as the 75x/xl, 78k, and 17k series. (3) 3-wire serial i/o mode with automatic transmit/receive function (msb-/lsb-first switchable) this mode has the same functions as those of the 3-wire serial i/o mode with automatic transmit/receive function added. the automatic transmit/receive function is used to transmit/receive data with a maximum of 32 bytes. this function enables the hardware to transmit/receive data to/from the osd (on screen display) device and a device with built-in display controller/driver independently of the cpu, thus the software load can be alleviated. 416 chapter 19 serial interface channel 1 19.2 serial interface channel 1 configuration serial interface channel 1 consists of the following hardware. table 19-1. serial interface channel 1 configuration item configuration register serial i/o shift register 1 (sio1) automatic data transmit/receive address pointer (adtp) control register timer clock select register 3 (tcl3) serial operating mode register 1 (csim1) automatic data transmit/receive control register (adtc) automatic data transmit/receive interval specify register (adti) port mode register 2 (pm2) note note refer to figures 6-5 and 6-7 block diagram of p20, p21, p23 to 26 and figures 6-6 and 6- 8 block diagram of p22 and p27 . figure 19-1. serial interface channel 1 block diagram re arld erce err trf strb busy 1 busy 0 internal bus automatic data transmit/receive control register serial operating mode register 1 adti 7 adti 4 adti 3 adti 2 adti 1 adti 0 5-bit counter serial i/o shift register 1 (sio1) hand- shake serial clock counter selector selector so1/ p21 pm21 p21 output latch dir dir buffer ram automatic data transmit/receive address pointer (adtp) sck1/ p22 pm22 internal bus trf p22 output latch match adti0 to adti4 selector to2 intcsi1 clear sio1 write q r s selector tcl 37 tcl 36 tcl 35 tcl 34 4 timer clock select register 3 f xx /2 to f xx /2 8 internal bus arld csie1 dir ate csim 11 csim 10 ate si1/ p20 stb/ p23 pm23 busy/ p24 automatic data transmit/receive interval specify register 417 chapter 19 serial interface channel 1 (1) serial i/o shift register 1 (sio1) this is an 8-bit register to carry out parallel/serial conversion and to carry out serial transmission/reception (shift operation) in synchronization with the serial clock. sio1 is set with an 8-bit memory manipulation instruction. when value in bit 7 (csie1) of serial operating mode register 1 (csim1) is 1, writing data to sio1 starts serial operation. in transmission, data written to sio1 is output to the serial output (so1). in reception, data is read from the serial input (si1) to sio1. reset input makes sio1 undefined. caution do not write data to sio1 while the automatic transmit/receive function is activated. (2) automatic data transmit/receive address pointer (adtp) this register stores the value (number of transmit data bytes C 1) while the automatic transmit/receive function is activated. as data is transferred/received, it is automatically decremented. adtp is set with an 8-bit memory manipulation instruction. the high-order 3 bits must be set to 0. reset input sets adtp to 00h. caution do not write data to adtp while the automatic transmit/receive function is activated. (3) serial clock counter this counter counts the serial clocks to be output and input during transmission/reception to check whether 8-bit data has been transmitted/received. 418 chapter 19 serial interface channel 1 19.3 serial interface channel 1 control registers the following four types of registers are used to control serial interface channel 1. ? timer clock select register 3 (tcl3) ? serial operating mode register 1 (csim1) ? automatic data transmit/receive control register (adtc) ? automatic data transmit/receive interval specify register (adti) (1) timer clock select register 3 (tcl3) this register sets the serial clock of serial interface channel 1. tcl3 is set with an 8-bit memory manipulation instruction. reset input sets tcl3 to 88h. remark besides setting the serial clock of serial interface channel 1, tcl3 sets the serial clock of serial interface channel 0. figure 19-2. timer clock select register 3 format caution when rewriting other data to tcl3, stop the serial transfer operation beforehand. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : bit 0 of oscillation mode selection register (osms) 4. figures in parentheses apply to operation with f x = 5.0 mhz. serial interface channel 1 serial clock selection tcl37 tcl36 tcl35 tcl34 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 f xx /2 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xx /2 8 mcs = 1 setting prohibited f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) mcs = 0 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) f x /2 4 (313 khz) f x /2 5 (156 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) other than above setting prohibited 6543210 7 symbol tcl3 tcl37 tcl36 tcl35 tcl34 tcl33 tcl32 tcl31 tcl30 ff43h 88h r/w address after reset r/w 419 chapter 19 serial interface channel 1 notes 1. if the external clock input has been selected with csim11 set to 0, set bit 1 (busy1) and bit 2 (strb) of the automatic data transmit/receive control register (adtc) to 0, 0. 2. can be used freely as port function. 3. can be used as p20 (cmos input/output) when only transmitter is used (set bit 7 (re) of adtc to 0). remark x : dont care pmxx : port mode register pxx : port output latch operation enable 6<5>43210 <7> symbol csim1 csie1 dir ate 0 0 0 csim11 csim10 csim11 0 1 serial interface channel 1 clock selection clock externally input to sck1 pin note 1 8-bit timer register 2 (tm2) output sck1 (input) 1 clock specified with bits 4 to 7 of timer clock select register 3 (tcl3) csie 1 0 csim10 x 0 1 ff68h 00h r/w address after reset r/w csim 11 p20 pm21 p21 pm22 shift register 1 operation serial clock counter operation control si1/p20 pin function sck1/p22 pin function x 1 0 1 0 x00 1x 1 note 2 note 2 note 2 note 2 count operation si1 note 3 (input) xxxxx operation stop clear p20 (cmos input/output) p22 (cmos input/output) ate 0 1 serial interface channel 1 operating mode selection 3-wire serial i/o mode 3-wire serial i/o mode with automatic transmit/receive function dir 0 1 start bit msb lsb si1 pin function si1/p20 (input) so1 pin function so1 (cmos output) x pm20 so1/p21 pin function so1 (cmos output) p21 (cmos input/output) sck1 (cmos output) 1 note 2 note 2 note 3 note 3 p22 (2) serial operating mode register 1 (csim1) this register sets serial interface channel 1 serial clock, operating mode, operation enable/stop, and automatic transmit/receive operation enable/stop. csim1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 to 00h. figure 19-3. serial operation mode register 1 format 420 chapter 19 serial interface channel 1 (3) automatic data transmit/receive control register (adtc) this register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy input enable/disable, and error check enable/disable, and displays automatic transmit/receive execution and error detection. adtc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adtc to 00h. figure 19-4. automatic data transmit/receive control register format notes 1. bits 3 and 4 (trf and err) are read-only bits. 2. the termination of automatic transmission/reception should be judged by using trf, not csiif1 (interrupt request flag). caution when an external clock input is selected with bit 1 (csim11) of the serial operating mode register 1 (csim1) set to 0, set strb and busy1 of adtc to 0, 0. remark x: dont care <6> <5> <4> <3> <2> <1> <0> <7> symbol adtc re arld erce err trf strb busy1 busy0 ff69h 00h r/w note 1 address after reset r/w busy1 0 1 1 busy input control not using busy input busy input enable (active high) busy input enable (active low) busy0 x 0 1 strb 0 1 strobe output control strobe output disable strobe output enable trf 1 status in automatic transmit/receive function note 2 detection of termination of automatic transmission/ reception (this bit is set to 0 upon suspension of automatic transmission/reception or when arld = 0.) during automatic transmission/reception (this bit is set to 1 when data is written to sio1.) r/w r/w r r err 0 1 error detection in automatic transmit/receive function no error (set to 0 when data is written to sio1) error occurred r/w arld 0 1 operating mode for automatic transmit/receive function single operating mode repetitive operating mode r/w re 0 1 receive operation in automatic transmit/receive function receive disable receive enable r/w erce 0 error check in automatic transmit/receive function error check disable error check enable (only when busy1 = 1) 0 1 421 chapter 19 serial interface channel 1 (4) automatic data transmit/receive interval specify register (adti) this register sets the automatic data transmit/receive function data transfer interval. adti is set by a 1-bit or 8-bit memory manipulation instruction. reset input sets adti to 00h. figure 19-5. automatic data transmit/receive interval specify register format (1/4) notes 1. the interval is dependent only on cpu processing. 2. the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expressions is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) ++ maximum = (n + 1) ++ cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. bits 5 and 6 must be set to 0. 3. when controlling the data transfer interval by automatic transmit/receive using adti, busy control (refer to 19.4.3 (4) (a) busy control option) becomes invalid. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f sck : serial clock frequency 2 6 28 0.5 f xx 2 6 36 1.5 f xx f xx f sck f xx f sck data transfer interval specification (f xx = 5.0-mhz operation) adti4 adti3 adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 2 18.4 s + 0.5/f sck 31.2 s + 0.5/f sck 44.0 s + 0.5/f sck 56.8 s + 0.5/f sck 69.6 s + 0.5/f sck 82.4 s + 0.5/f sck 95.2 s + 0.5/f sck 108.0 s + 0.5/f sck 120.8 s + 0.5/f sck 133.6 s + 0.5/f sck 146.4 s + 0.5/f sck 159.2 s + 0.5/f sck 172.0 s + 0.5/f sck 184.8 s + 0.5/f sck 197.6 s + 0.5/f sck 210.4 s + 0.5/f sck maximum note 2 20.0 s + 1.5/f sck 32.8 s + 1.5/f sck 45.6 s + 1.5/f sck 58.4 s + 1.5/f sck 71.2 s + 1.5/f sck 84.0 s + 1.5/f sck 96.8 s + 1.5/f sck 109.6 s + 1.5/f sck 122.4 s + 1.5/f sck 135.2 s + 1.5/f sck 148.0 s + 1.5/f sck 160.8 s + 1.5/f sck 173.6 s + 1.5/f sck 186.4 s + 1.5/f sck 199.2 s + 1.5/f sck 212.0 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 data transfer interval control no control of interval by adti note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 422 chapter 19 serial interface channel 1 figure 19-5. automatic data transmit/receive interval specify register format (2/4) note the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expressions is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) ++ maximum = (n + 1) ++ cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. bits 5 and 6 must be set to 0. 3. when controlling the data transfer interval by automatic transmit/receive using adti, busy control (refer to 19.4.3 (4) (a) busy control option) becomes invalid. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f sck : serial clock frequency 2 6 28 0.5 f xx f xx f sck 2 6 36 1.5 f xx f xx f sck data transfer interval specification (f xx = 5.0-mhz operation) adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 223.2 s + 0.5/f sck 236.0 s + 0.5/f sck 248.8 s + 0.5/f sck 261.6 s + 0.5/f sck 274.4 s + 0.5/f sck 287.2 s + 0.5/f sck 300.0 s + 0.5/f sck 312.8 s + 0.5/f sck 325.6 s + 0.5/f sck 338.4 s + 0.5/f sck 351.2 s + 0.5/f sck 364.0 s + 0.5/f sck 376.8 s + 0.5/f sck 389.6 s + 0.5/f sck 402.4 s + 0.5/f sck 415.2 s + 0.5/f sck maximum note 224.8 s + 1.5/f sck 237.6 s + 1.5/f sck 250.4 s + 1.5/f sck 263.2 s + 1.5/f sck 276.0 s + 1.5/f sck 288.8 s + 1.5/f sck 301.6 s + 1.5/f sck 314.4 s + 1.5/f sck 327.2 s + 1.5/f sck 340.0 s + 1.5/f sck 352.8 s + 1.5/f sck 365.6 s + 1.5/f sck 378.4 s + 1.5/f sck 391.2 s + 1.5/f sck 404.0 s + 1.5/f sck 416.8 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 423 chapter 19 serial interface channel 1 figure 19-5. automatic data transmit/receive interval specify register format (3/4) notes 1. the interval is dependent only on cpu processing. 2. the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expressions is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) ++ maximum = (n + 1) ++ cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. bits 5 and 6 must be set to 0. 3. when controlling the data transfer interval by automatic transmit/receive using adti, busy control (refer to 19.4.3 (4) (a) busy control option) becomes invalid. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f sck : serial clock frequency 2 6 28 f xx f xx 2 6 36 f xx f xx 0.5 f sck 1.5 f sck data transfer interval specification (f xx = 2.5-mhz operation) adti4 adti3 adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 2 36.8 s + 0.5/f sck 62.4 s + 0.5/f sck 88.0 s + 0.5/f sck 113.6 s + 0.5/f sck 139.2 s + 0.5/f sck 164.8 s + 0.5/f sck 190.4 s + 0.5/f sck 216.0 s + 0.5/f sck 241.6 s + 0.5/f sck 267.2 s + 0.5/f sck 292.8 s + 0.5/f sck 318.4 s + 0.5/f sck 344.0 s + 0.5/f sck 369.6 s + 0.5/f sck 395.2 s + 0.5/f sck 420.8 s + 0.5/f sck maximum note 2 40.0 s + 1.5/f sck 65.6 s + 1.5/f sck 91.2 s + 1.5/f sck 116.8 s + 1.5/f sck 142.4 s + 1.5/f sck 168.0 s + 1.5/f sck 193.6 s + 1.5/f sck 219.2 s + 1.5/f sck 244.8 s + 1.5/f sck 270.4 s + 1.5/f sck 296.0 s + 1.5/f sck 321.6 s + 1.5/f sck 347.2 s + 1.5/f sck 372.8 s + 1.5/f sck 398.4 s + 1.5/f sck 424.0 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 data transfer interval control no control of interval by adti note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 424 chapter 19 serial interface channel 1 note the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expressions is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) ++ maximum = (n + 1) ++ cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. bits 5 and 6 must be set to 0. 3. when controlling the data transfer interval by automatic transmit/receive using adti, busy control (refer to 19.4.3 (4) (a) busy control option) becomes invalid. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f sck : serial clock frequency f xx f xx f sck 2 6 28 0.5 f xx f xx f sck 2 6 36 1.5 figure 19-5. automatic data transmit/receive interval specify register format (4/4) data transfer interval specification (f xx = 2.5-mhz operation) adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 446.4 s + 0.5/f sck 472.0 s + 0.5/f sck 497.6 s + 0.5/f sck 523.2 s + 0.5/f sck 548.8 s + 0.5/f sck 574.4 s + 0.5/f sck 600.0 s + 0.5/f sck 625.6 s + 0.5/f sck 651.2 s + 0.5/f sck 676.8 s + 0.5/f sck 702.4 s + 0.5/f sck 728.0 s + 0.5/f sck 753.6 s + 0.5/f sck 779.2 s + 0.5/f sck 804.8 s + 0.5/f sck 830.4 s + 0.5/f sck maximum note 449.6 s + 1.5/f sck 475.2 s + 1.5/f sck 500.8 s + 1.5/f sck 526.4 s + 1.5/f sck 552.0 s + 1.5/f sck 577.6 s + 1.5/f sck 603.2 s + 1.5/f sck 628.8 s + 1.5/f sck 654.4 s + 1.5/f sck 680.0 s + 1.5/f sck 705.6 s + 1.5/f sck 731.2 s + 1.5/f sck 756.8 s + 1.5/f sck 782.4 s + 1.5/f sck 808.0 s + 1.5/f sck 833.6 s + 1.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 425 chapter 19 serial interface channel 1 19.4 serial interface channel 1 operations the following three operating modes are available to the serial interface channel 1. ? operation stop mode ? 3-wire serial i/o mode ? 3-wire serial i/o mode with automatic transmit/receive function 19.4.1 operation stop mode serial transfer is not carried out in the operation stop mode. thus, power consumption can be reduced. the serial i/o shift register 1 (sio1) does not carry out shift operation either, and thus it can be used as an ordinary 8-bit register. in the operation stop mode, the p20/si1, p21/so1, p22/sck1, p23/stb, and p24/busy pins can be used as ordinary input/output ports. (1) register setting the operation stop mode is set with the serial operating mode register 1 (csim1). csim1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 to 00h. notes 1. can be used freely as port function. 2. can be used as p20 (cmos input/output) when only transmitter is used (set bit 7 (re) of the automatic data transmit/receive control register (adtc) to 0). remark x : dont care pmxx : port mode register pxx : port output latch operation enable 6<5>43210 <7> symbol csim1 csie1 dir ate 0 0 0 csim11 csim10 sck1 (input) csie 1 0 ff68h 00h r/w address after reset r/w csim 11 p20 pm21 p21 pm22 note 2 shift register 1 operation serial clock counter operation control si1/p20 pin function sck1/p22 pin function x 1 0 1 0 x00 1x 1 note 1 note 1 note 1 note 1 count operation si1 (input) xxxxx operation stop clear p20 (cmos input/output) p22 (cmos input/output) x pm20 so1/p21 pin function so1 (cmos output) p21 (cmos input/output) sck1 (cmos output) 1 note 1 note 1 note 2 note 2 p22 426 chapter 19 serial interface channel 1 19.4.2 3-wire serial i/o mode operation the 3-wire serial i/o mode is valid for connection of peripheral i/o units and display controllers which incorporate a conventional synchronous serial interface such as the 75x/xl, 78k, and 17k series. communication is carried out with three lines of serial clock (sck1), serial output (so1) and serial input (si1). (1) register setting the 3-wire serial i/o mode is set with the serial operating mode register 1 (csim1). csim1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 to 00h. 6<5>43210 <7> symbol csim1 csie1 dir ate 0 0 0 csim11 csim10 csim11 0 1 serial interface channel 1 clock selection clock externally input to sck1 pin note 8-bit timer register 2 (tm2) output 1 clock specified with bits 4 to 7 of timer clock select register 3 (tcl3) csim10 x 0 1 ff68h 00h r/w address after reset r/w ate 0 1 serial interface channel 1 operating mode selection 3-wire serial i/o mode 3-wire serial i/o mode with automatic transmit/receive function dir 0 1 start bit msb lsb si1 pin function si1/p20 (input) so1 pin function so1 (cmos output) operation enable sck1 (input) csie 1 0 csim 11 p20 pm21 p21 pm22 shift register 1 operation serial clock counter operation control si1/p20 pin function sck1/p22 pin function x 1 0 1 0 x00 1x 1 note 1 note 1 note 1 note 1 count operation si1 note 2 (input) xxxxx operation stop clear p20 (cmos input/output) p22 (cmos input/output) x pm20 so1/p21 pin function so1 (cmos output) p21 (cmos input/output) sck1 (cmos output) 1 note 1 note 1 note 2 note 2 p22 notes 1. if the external clock input has been selected with csim11 set to 0, set bit 1 (busy1) and bit 2 (strb) of the automatic data transmit/receive control register (adtc) to 0, 0. 2. can be used freely as port function. 3. can be used as p20 (cmos input/output) when only transmitter is used (set bit 7 (re) of adtc to 0). remark x : dont care pmxx : port mode register pxx : port output latch 427 chapter 19 serial interface channel 1 (2) communication operation the 3-wire serial i/o mode is used for data transmission/reception in 8-bit units. bit-wise data transmission/ reception is carried out in synchronization with the serial clock. shift operation of the serial i/o shift register 1 (sio1) is carried out at the falling edge of the serial clock sck1. the transmit data is held in the so1 latch and is output from the so1 pin. the receive data input to the si1 pin is latched into sio1 at the rising edge of sck1. upon termination of 8-bit transfer, the sio1 operation stops automatically and the interrupt request flag (csiif1) is set. figure 19-6. 3-wire serial i/o mode timings caution so1 pin becomes low level by sio1 write. (3) msb/lsb switching as the start bit the 3-wire serial i/o mode enables to select transfer to start from msb or lsb. figure 19-7 shows the configuration of the serial i/o shift register 1 (sio1) and internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. msb/lsb switching as the start bit can be specified with bit 6 (dir) of the serial operating mode register 1 (csim1). si1 sck1 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so1 do7 do6 do5 do4 do3 do2 do1 do0 csiif1 transfer start at the falling edge of sck1 end of transfer sio1 write 428 chapter 19 serial interface channel 1 figure 19-7. circuit of switching in transfer bit order start bit switching is realized by switching the bit order write to sio1. the sio1 shift order remains unchanged. thus, msb-first and lsb-first must be switched before writing data to the shift register. (4) transfer start serial transfer is started by setting transfer data to the serial i/o shift register 1 (sio1) when the following two conditions are satisfied. ? serial interface channel 1 operation control bit (csie1) = 1 ? internal serial clock is stopped or sck1 is a high level after 8-bit serial transfer. caution if csie1 is set to 1 after data write to sio1, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (csiif1) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si1 shift register 1 (sio1) read/write gate so1 sck1 dq so1 latch 429 chapter 19 serial interface channel 1 19.4.3 3-wire serial i/o mode operation with automatic transmit/receive function this 3-wire serial i/o mode is used for transmission/reception of a maximum of 32-byte data without the use of software. once transfer is started, the data prestored in the ram can be transmitted by the set number of bytes, and data can be received and stored in the ram by the set number of bytes. handshake signals (stb and busy) are supported by hardware to transmit/receive data continuously. osd (on screen display) lsi and peripheral lsi including lcd controller/driver can be connected without difficulty. (1) register setting the 3-wire serial i/o mode with automatic transmit/receive function is set with the serial operating mode register 1 (csim1), the automatic data transmit/receive control register (adtc) and the automatic data transmit/receive interval specify register (adti). (a) serial operating mode register 1 (csim1) csim1 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim1 to 00h. notes 1. if the external clock input has been selected with csim11 set to 0, set bit 1 (busy1) and bit 2 (strb) of the automatic data transmit/receive control register (adtc) to 0, 0. 2. can be used freely as port function. 3. can be used as p20 (cmos input/output) when only transmitter is used (set bit 7 (re) of adtc to 0). remark x : dont care pmxx : port mode register pxx : port output latch operation enable 6<5>43210 <7> symbol csim1 csie1 dir ate 0 0 0 csim11 csim10 csim11 0 1 serial interface channel 1 clock selection clock externally input to sck1 pin note 1 8-bit timer register 2 (tm2) output sck1 (input) 1 clock specified with bits 4 to 7 of timer clock select register 3 (tcl3) csie 1 0 csim10 x 0 1 ff68h 00h r/w address after reset r/w csim 11 p20 pm21 p21 pm22 shift register 1 operation serial clock counter operation control si1/p20 pin function sck1/p22 pin function x 1 0 1 0 x00 1x 1 note 2 note 2 note 2 note 2 count operation si1 note 3 (input) xxxxx operation stop clear p20 (cmos input/output) p22 (cmos input/output) ate 0 serial interface channel 1 operating mode selection 3-wire serial i/o mode dir 0 1 start bit msb lsb si1 pin function si1/p20 (input) so1 pin function so1 (cmos output) x pm20 so1/p21 pin function so1 (cmos output) p21 (cmos input/output) sck1 (cmos output) 1 note 2 note 2 note 3 note 3 p22 1 3-wire serial i/o mode with automatic transmit/receive function 430 chapter 19 serial interface channel 1 (b) automatic data transmit/receive control register (adtc) adtc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adtc to 00h. <6> <5> <4> <3> <2> <1> <0> <7> symbol adtc re arld erce err trf strb busy1 busy0 ff69h 00h r/w note 1 address after reset r/w busy1 0 1 1 busy input control not using busy input busy input enable (active high) busy input enable (active low) busy0 x 0 1 strb 0 1 strobe output control strobe output disable strobe output enable trf 1 status of automatic transmit/receive function note 2 detection of termination of automatic transmission/ reception (this bit is set to 0 upon suspension of automatic transmission/reception or when arld = 0.) during automatic transmission/reception (this bit is set to 1 when data is written to sio1.) r/w r/w r r err 0 1 error detection of automatic transmit/receive function no error (this bit is set to 0 when data is written to sio1) error occurred r/w arld 0 1 operating mode selection of automatic transmit/ receive function single operating mode repetitive operating mode r/w re 0 1 receive control of automatic transmit/receive function receive disable receive enable r/w erce 0 error check control of automatic transmit/ receive function error check disable error check enable (only when busy1 = 1) 0 1 notes 1. bits 3 and 4 (trf and err) are read-only bits. 2. judge the termination of automatic transmission/reception by using trf, not csiif1 (interrupt request flag). caution when an external clock input is selected with bit 1 (csim11) of the serial operating mode register 1 (csim1) set to 0, set strb and busy1 of adtc to 0, 0 (when an external clock is input, handshake control cannot be carried out). remark x: dont care 431 chapter 19 serial interface channel 1 (c) automatic data transmit/receive interval specify register (adti) this register sets the automatic data transmit/receive function data transfer interval. adti is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets adti to 00h. notes 1. the interval is dependent only on cpu processing. 2. the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expressions is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) ++ maximum = (n + 1) ++ cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. bits 5 and 6 must be set to 0. 3. when controlling the data transfer interval by automatic transmit/receive using adti, busy control (refer to 19.4.3 (4) (a) busy control option) becomes invalid. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f sck : serial clock frequency f xx f sck 28 0.5 2 6 f xx f xx 2 6 f xx f sck 36 1.5 minimum note 2 18.4 s + 0.5/f sck 31.2 s + 0.5/f sck 44.0 s + 0.5/f sck 56.8 s + 0.5/f sck 69.6 s + 0.5/f sck 82.4 s + 0.5/f sck 95.2 s + 0.5/f sck 108.0 s + 0.5/f sck 120.8 s + 0.5/f sck 133.6 s + 0.5/f sck 146.4 s + 0.5/f sck 159.2 s + 0.5/f sck 172.0 s + 0.5/f sck 184.8 s + 0.5/f sck 197.6 s + 0.5/f sck 210.4 s + 0.5/f sck maximum note 2 20.0 s + 1.5/f sck 32.8 s + 1.5/f sck 45.6 s + 1.5/f sck 58.4 s + 1.5/f sck 71.2 s + 1.5/f sck 84.0 s + 1.5/f sck 96.8 s + 1.5/f sck 109.6 s + 1.5/f sck 122.4 s + 1.5/f sck 135.2 s + 1.5/f sck 148.0 s + 1.5/f sck 160.8 s + 1.5/f sck 173.6 s + 1.5/f sck 186.4 s + 1.5/f sck 199.2 s + 1.5/f sck 212.0 s + 1.5/f sck data transfer interval specification (f xx = 5.0-mhz operation) adti4 adti3 adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 data transfer interval control no control of interval by adti note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 432 chapter 19 serial interface channel 1 note the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expressions is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) ++ maximum = (n + 1) ++ cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. bits 5 and 6 must be set to 0. 3. when controlling the data transfer interval by automatic transmit/receive using adti, busy control (refer to 19.4.3 (4) (a) busy control option) becomes invalid. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f sck : serial clock frequency 28 0.5 f xx f sck 36 1.5 f xx f sck 2 6 f xx 2 6 f xx minimum note 223.2 s + 0.5/f sck 236.0 s + 0.5/f sck 248.8 s + 0.5/f sck 261.6 s + 0.5/f sck 274.4 s + 0.5/f sck 287.2 s + 0.5/f sck 300.0 s + 0.5/f sck 312.8 s + 0.5/f sck 325.6 s + 0.5/f sck 338.4 s + 0.5/f sck 351.2 s + 0.5/f sck 364.0 s + 0.5/f sck 376.8 s + 0.5/f sck 389.6 s + 0.5/f sck 402.4 s + 0.5/f sck 415.2 s + 0.5/f sck maximum note 224.8 s + 1.5/f sck 237.6 s + 1.5/f sck 250.4 s + 1.5/f sck 263.2 s + 1.5/f sck 276.0 s + 1.5/f sck 288.8 s + 1.5/f sck 301.6 s + 1.5/f sck 314.4 s + 1.5/f sck 327.2 s + 1.5/f sck 340.0 s + 1.5/f sck 352.8 s + 1.5/f sck 365.6 s + 1.5/f sck 378.4 s + 1.5/f sck 391.2 s + 1.5/f sck 404.0 s + 1.5/f sck 416.8 s + 1.5/f sck data transfer interval specification (f xx = 5.0-mhz operation) adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 433 chapter 19 serial interface channel 1 notes 1. the interval is dependent only on cpu processing. 2. the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expressions is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) ++ maximum = (n + 1) ++ cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. bits 5 and 6 must be set to 0. 3. when controlling the data transfer interval by automatic transmit/receive using adti, busy control (refer to 19.4.3 (4) (a) busy control option) becomes invalid. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f sck : serial clock frequency 2 6 f xx 2 6 f xx 28 0.5 f xx f sck 36 1.5 f xx f sck minimum note 2 36.8 s + 0.5/f sck 62.4 s + 0.5/f sck 88.0 s + 0.5/f sck 113.6 s + 0.5/f sck 139.2 s + 0.5/f sck 164.8 s + 0.5/f sck 190.4 s + 0.5/f sck 216.0 s + 0.5/f sck 241.6 s + 0.5/f sck 267.2 s + 0.5/f sck 292.8 s + 0.5/f sck 318.4 s + 0.5/f sck 344.0 s + 0.5/f sck 369.6 s + 0.5/f sck 395.2 s + 0.5/f sck 420.8 s + 0.5/f sck maximum note 2 40.0 s + 1.5/f sck 65.6 s + 1.5/f sck 91.2 s + 1.5/f sck 116.8 s + 1.5/f sck 142.4 s + 1.5/f sck 168.0 s + 1.5/f sck 193.6 s + 1.5/f sck 219.2 s + 1.5/f sck 244.8 s + 1.5/f sck 270.4 s + 1.5/f sck 296.0 s + 1.5/f sck 321.6 s + 1.5/f sck 347.2 s + 1.5/f sck 372.8 s + 1.5/f sck 398.4 s + 1.5/f sck 424.0 s + 1.5/f sck data transfer interval specification (f xx = 2.5-mhz operation) adti4 adti3 adti2 adti1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti7 0 data transfer interval control no control of interval by adti note 1 control of interval by adti (adti0 to adti4) 1 adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 434 chapter 19 serial interface channel 1 note the data transfer interval includes an error. the data transfer minimum and maximum intervals are found from the following expressions (n: value set in adti0 to adti4). however, if a minimum which is calculated by the following expressions is smaller than 2/f sck , the minimum interval time is 2/f sck . minimum = (n + 1) ++ maximum = (n + 1) ++ cautions 1. do not write to adti during operation of the automatic data transmit/receive function. 2. bits 5 and 6 must be set to 0. 3. when controlling the data transfer interval by automatic transmit/receive using adti, busy control (refer to 19.4.3 (4) (a) busy control option) becomes invalid. remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency f sck : serial clock frequency 2 6 f xx 2 6 f xx 28 0.5 f xx f sck 36 1.5 f xx f sck maximum note 449.6 s + 1.5/f sck 475.2 s + 1.5/f sck 500.8 s + 1.5/f sck 526.4 s + 1.5/f sck 552.0 s + 1.5/f sck 577.6 s + 1.5/f sck 603.2 s + 1.5/f sck 628.8 s + 1.5/f sck 654.4 s + 1.5/f sck 680.0 s + 1.5/f sck 705.6 s + 1.5/f sck 731.2 s + 1.5/f sck 756.8 s + 1.5/f sck 782.4 s + 1.5/f sck 808.0 s + 1.5/f sck 833.6 s + 1.5/f sck data transfer interval specification (f xx = 2.5-mhz operation) adti4 adti3 adti2 adti1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 minimum note 446.4 s + 0.5/f sck 472.0 s + 0.5/f sck 497.6 s + 0.5/f sck 523.2 s + 0.5/f sck 548.8 s + 0.5/f sck 574.4 s + 0.5/f sck 600.0 s + 0.5/f sck 625.6 s + 0.5/f sck 651.2 s + 0.5/f sck 676.8 s + 0.5/f sck 702.4 s + 0.5/f sck 728.0 s + 0.5/f sck 753.6 s + 0.5/f sck 779.2 s + 0.5/f sck 804.8 s + 0.5/f sck 830.4 s + 0.5/f sck 6543210 7 symbol adti adti7 0 0 adti4 adti3 adti2 adti1 adti0 ff6bh 00h r/w address after reset r/w adti0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 435 chapter 19 serial interface channel 1 (2) automatic transmit/receive data setting (a) transmit data setting <1> write transmit data from the least significant address fac0h of buffer ram (up to fadfh at maximum). the transmit data should be in the order from high-order address to low-order address. <2> set to the automatic data transmit/receive address pointer (adtp) the value obtained by subtracting 1 from the number of transmit data bytes. (b) automatic transmit/receive mode setting <1> set csie1 and ate of the serial operating mode register 1 (csim1) to 1. <2> set re of the automatic data transmit/receive control register (adtc) to 1. <3> set a data transmit/receive interval in the automatic data transmit/receive interval specify register (adti). <4> write any value to the serial i/o shift register 1 (sio1) (transfer start trigger). caution writing any value to sio1 orders the start of automatic transmit/receive operation and the written value has no meaning. the following operations are automatically carried out when (a) and (b) are carried out. ? after the buffer ram data specified with adtp is transferred to sio1, transmission is carried out (start of automatic transmission/reception). ? the received data is written to the buffer ram address specified with adtp. ? adtp is decremented and the next data transmission/reception is carried out. data transmission/ reception continues until the adtp decremental output becomes 00h and address fac0h data is output (end of automatic transmission/reception). ? when automatic transmission/reception is terminated, trf is cleared to 0. 436 chapter 19 serial interface channel 1 cautions 1. because, in the basic transmission/reception mode, the automatic transmit/receive function writes/reads data to/from the buffer ram after 1-byte transmission/reception, an interval is inserted till the next transmission/reception. as the buffer ram write/ read is performed at the same time as cpu processing, the maximum interval is dependent upon cpu processing and the value of the automatic data transmit/ receive interval specify register (adti) (see (5) automatic transmit/receive interval time). 2. when trf is cleared, the so1 pin becomes low level. remark csiif0 : interrupt request flag trf : bit 3 of automatic data transmit/receive control register (adtc) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif1 trf si1 d7d6d5d4d3d2d1d0 d7d6d5d4d3d2d1d0 interval (3) communication operation (a) basic transmission/reception mode this transmission/reception mode is the same as the 3-wire serial i/o mode in which specified number of data are transmitted/received in 8-bit units. serial transfer is started when any data is written to the serial i/o shift register 1 (sio1) while bit 7 (csie1) of the serial operating mode register 1 (csim1) is set to 1. upon completion of transmission of the last byte, the interrupt request flag (csiif1) is set. however, determine whether the automatic transmission/reception is completed, not with csiif1 but with bit 3 (trf) of the automatic data transmission/reception control register (adtc). if busy control and strobe control are not executed, the p23/stb and p24/busy pins can be used as normal input/output ports. figure 19-8 shows the basic transmission/reception mode operation timings, and figure 19-9 shows the operation flowchart. figure 19-10 shows an example of the buffer ram operation in 6-byte transmission/reception. figure 19-8. basic transmission/reception mode operation timings 437 chapter 19 serial interface channel 1 adtp : automatic data transmit/receive address pointer adti : automatic data transmit/receive interval specify register sio1 : serial i/o shift register 1 trf : bit 3 of automatic data transmit/receive control register (adtc) start write transmit data in buffer ram set adtp to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti write any data to sio1 (start trigger) write transmit data from buffer ram to sio1 transmission/reception operation write receive data from sio1 to buffer ram pointer value = 0 no trf = 0 no end yes yes decrement pointer value software execution hardware execution software execution figure 19-9. basic transmission/reception mode flowchart 438 chapter 19 serial interface channel 1 in 6-byte transmission/reception (arld = 0, re = 1) in basic transmit/receive mode, buffer ram operates as follows. (i) before transmission/reception (refer to figure 19-10 (a)) after any data has been written to the serial i/o shift register 1 (sio1) (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the buffer ram to sio1. when transmission of the first byte is completed, the receive data 1 (r1) is transferred from sio1 to the buffer ram, and automatic data transmit/receive address pointer (adtp) is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1. (ii) 4th byte transmission/reception point (refer to figure 19-10 (b)) transmission/reception of the third byte is completed, and transmit data 4 (t4) is transferred from the buffer ram to sio1. when transmission of the fourth byte is completed, the receive data 4 (r4) is transferred from sio1 to the buffer ram, and adtp is decremented. (iii) completion of transmission/reception (refer to figure 19-10 (c)) when transmission of the sixth byte is completed, the receive data 6 (r6) is transferred from sio1 to the buffer ram, and the interrupt request flag (csiif1) is set (intcsi1 generation). figure 19-10. buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) (1/2) (a) before transmission/reception transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h receive data 1 (r1) sio1 0 csiif1 5 adtp ? 439 chapter 19 serial interface channel 1 figure 19-10. buffer ram operation in 6-byte transmission/reception (in basic transmit/receive mode) (2/2) (b) 4th byte transmission/reception receive data 1 (r1) receive data 2 (r2) receive data 3 (r3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h receive data 4 (r4) sio1 0 csiif1 2 adtp ? receive data 1 (r1) receive data 2 (r2) receive data 3 (r3) receive data 4 (r4) receive data 5 (r5) receive data 6 (r6) fadfh fac5h fac0h sio1 1 csiif1 0 adtp (c) completion of transmission/reception 440 chapter 19 serial interface channel 1 (b) basic transmission mode in this mode, the specified number of 8-bit unit data are transmitted. serial transfer is started when any data is written to the serial i/o shift register 1 (sio1) while bit 7 (csie1) of the serial operating mode register 1 (csim1) is set to 1. upon completion of transmission of the last byte, the interrupt request flag (csiif1) is set. however, determine whether the automatic transmission/reception is completed, not with csiif1 but with the bit 3 (trf) of automatic data transmission/reception control register (adtc). if receive operation, busy control and strobe control are not executed, the p20/si1, p23/stb and p24/ busy pins can be used as normal input/ports. figure 19-11 shows the basic transmission mode operation timings, and figure 19-12 shows the operation flowchart. figure 19-13 shows an example of the buffer ram operation in 6-byte transmission. figure 19-11. basic transmission mode operation timings cautions 1. because, in the basic transmission mode, the automatic transmit/receive function reads data from the buffer ram after 1-byte transmission, an interval is inserted till the next transmission. as the buffer ram read is performed at the same time as cpu processing, the maximum interval is dependent upon cpu processing and the value of the automatic data transmit/receive interval specify register (adti) (see (5) automatic transmit/receive interval time). 2. when trf is cleared, the so1 pin becomes low level. remark csiif1: interrupt request flag trf : bit 3 of automatic data transmit/receive control register (adtc) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif1 trf interval 441 chapter 19 serial interface channel 1 figure 19-12. basic transmission mode flowchart adtp : automatic data transmit/receive address pointer adti : automatic data transmit/receive interval specify register sio1 : serial i/o shift register 1 trf : bit 3 of automatic data transmit/receive control register (adtc) start write transmit data in buffer ram set adtp to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti write any data to sio1 (start trigger) write transmit data from buffer ram to sio1 transmission operation pointer value = 0 no trf = 0 no end yes yes decrement pointer value software execution hardware execution software execution 442 chapter 19 serial interface channel 1 in 6-byte transmission (arld = 0, re = 0) in basic transmit mode, buffer ram operates as follows. (i) before transmission (refer to figure 19-13 (a)) after any data has been written to the serial i/o shift register 1 (sio1) (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the buffer ram to sio1. when transmission of the first byte is completed, the automatic data transmit/receive address pointer (adtp) is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1. (ii) 4th byte transmission point (refer to figure 19-13 (b)) transmission of the third byte is completed, and transmit data 4 (t4) is transferred from the buffer ram to sio1. when transmission of the fourth byte is completed, adtp is decremented. (iii) completion of transmission/reception (refer to figure 19-13 (c)) when transmission of the sixth byte is completed, the interrupt request flag (csiif1) is set (intcsi1 generation). figure 19-13. buffer ram operation in 6-byte transmission (in basic transmit mode) (1/2) (a) before transmission transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp ? 443 chapter 19 serial interface channel 1 figure 19-13. buffer ram operation in 6-byte transmission (in basic transmit mode) (2/2) (b) 4th byte transmission point (c) completion of transmission/reception transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 2 adtp ? transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 1 csiif1 0 adtp 444 chapter 19 serial interface channel 1 (c) repeat transmission mode in this mode, data stored in the buffer ram is transmitted repeatedly. serial transfer is started by writing any data to serial i/o shift register 1 (sio1) when 1 is set in bit 7 (csie1) of the serial operating mode register 1 (csim1). unlike the basic transmission mode, after the last byte (data in address fac0h) has been transmitted, the interrupt request flag (csiif1) is not set, the value at the time when the transmission was started is set in the automatic data transmit/receive address pointer (adtp) again, and the buffer ram contents are transmitted again. when a reception operation, busy control and strobe control are not performed, the p20/si1, p23/stb and p24/busy pins can be used as ordinary input/output ports. the repeat transmission mode operation timing is shown in figure 19-14, and the operation flowchart in figure 19-15. figure 19-16 shows an example of the buffer ram operation in 6-byte repeat transmission. figure 19-14. repeat transmission mode operation timing caution since, in the repeat transmission mode, a read is performed on the buffer ram after the transmission of one byte, the interval is included in the period up to the next transmission. as the buffer ram read is performed at the same time as cpu processing, the maximum interval is dependent upon the cpu operation and the value of the automatic data transmit/receive interval specify register (adti) (see (5) automatic transmit/receive interval time). d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval interval d7 d6 d5 sck1 so1 445 chapter 19 serial interface channel 1 figure 19-15. repeat transmission mode flowchart adtp : automatic data transmit/receive address pointer adti : automatic data transmit/receive interval specify register sio1 : serial i/o shift register 1 start write transmit data in buffer ram set adtp to the value (pointer value) obtained by subtracting 1 from the number of transmit data bytes set the transmission/reception operation interval time in adti write any data to sio1 (start trigger) write transmit data from buffer ram to sio1 transmission operation pointer value = 0 no yes decrement pointer value software execution hardware execution reset adtp 446 chapter 19 serial interface channel 1 in 6-byte transmission (arld = 1, re = 0) in repeat transmit mode, buffer ram operates as follows. (i) before transmission (refer to figure 19-16 (a)) after any data has been written to the serial i/o shift register 1 (sio1) (start trigger: this data is not transferred), transmit data 1 (t1) is transferred from the buffer ram to sio1. when transmission of the first byte is completed, the automatic data transmit/receive address pointer (adtp) is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1. (ii) upon completion of transmission of 6 bytes (refer to figure 19-16 (b)) when transmission of the sixth byte is completed, the interrupt request flag (csiif1) is not set. the first pointer value is set to adtp again. (iii) 7th byte transmission point (refer to figure 19-16 (c)) transmit data 1 (t1) is transferred from the buffer ram to sio1 again. when transmission of the first byte is completed, adtp is decremented. then transmit data 2 (t2) is transferred from the buffer ram to sio1. figure 19-16. buffer ram operation in 6-byte transmission (in repeat transmit mode) (1/2) (a) before transmission transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp ? 447 chapter 19 serial interface channel 1 figure 19-16. buffer ram operation in 6-byte transmission (in repeat transmit mode) (2/2) (b) upon completion of transmission of 6 bytes (c) 7th byte transmission point transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp ? transmit data 1 (t1) transmit data 2 (t2) transmit data 3 (t3) transmit data 4 (t4) transmit data 5 (t5) transmit data 6 (t6) fadfh fac5h fac0h sio1 0 csiif1 5 adtp ? 448 chapter 19 serial interface channel 1 (d) automatic transmission/reception suspending and restart automatic transmission/reception can be temporarily suspended by setting bit 7 (csie1) of the serial operating mode register 1 (csim1) to 0. if during 8-bit data transfer, the transmission/reception is not suspended if bit 7 (csie1) is set to 0, it is suspended upon completion of 8-bit data transfer. when suspended, bit 3 (trf) of the automatic data transmit/receive control register (adtc) is set to 0 after transfer of the 8th bit, and all the port pins used with the serial interface pins for dual function (p20/si1, p21/so1, p22/sck1, p23/stb, and p24/busy) are set to the port mode. for restart of automatic transmission/reception, remaining data can be transferred by setting csie1 to 1 and writing any data to the serial i/o shift register 1 (sio1). cautions 1. if the halt instruction is executed during automatic transmission/reception, transfer is suspended and the halt mode is set if during 8-bit data transfer. when the halt mode is cleared, automatic transmission/reception is restarted from the suspended point. 2. when suspending automatic transmission/reception, do not change the operating mode to 3-wire serial i/o mode while trf = 1. figure 19-17. automatic transmission/reception suspension and restart csie1: bit 7 of serial operating mode register 1 (csim1) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 si1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 restart command csie1 = 1, write to sio1 suspend csie1 = 0 (suspended command) 449 chapter 19 serial interface channel 1 (4) synchronization control busy control and strobe control are functions for synchronizing sending and receiving between the master device and slave device. by using these functions, it is possible to detect bit slippage during sending and receiving. (a) busy control option busy control is a function which causes the master devices serial transmission to wait when the slave device outputs a busy signal to the master device, and maintain the wait state while that busy signal is active. when the busy control option is used, the conditions shown below are necessary. ? bit 5 (ate) of serial operation mode register 1 (csim1) should be set at (1). ? bit 1 (busy1) of the automatic data transmit/receive control register (adtc) should be set at (1). the system configuration between the master device and slave device in cases where the busy control option is used is shown in figure 19-18. figure 19-18. system configuration when the busy control option is used the master device inputs the busy signal output by the slave device to pin busy/p24. in sync with the fall of the serial clock, the master device samples the input busy signal. even if the busy signal becomes active during sending or receiving of 8 bit data, the wait does not apply. if the busy signal becomes active at the rise of the serial clock 2 clock cycles after sending or receiving of 8 bit data ends, the busy input first becomes effective at that point, and thereafter, sending or receiving of data waits during the period that the busy signal is active. the busy signals active level is set in bit 0 (busy0) of adtc. busy0 = 0: active high busy0 = 1: active low furthermore, in the case that the busy control option is used, select the internal clock for the serial clock. the busy signal cannot be controlled with an external clock. the operation timing when the busy control option is used is shown in figure 19-19. caution busy control cannot be used at the same time as interval timing control using the automatic data transmit/receive interval specify register (adti). if both are used simultaneously, busy control becomes invalid. sck1 so1 si1 sck1 so1 si1 busy master device ( pd78078, 78078y subseries) slave device 450 chapter 19 serial interface channel 1 figure 19-19. operation timings when using busy control option (busy0 = 0) caution when trf is cleared, the so1 pin becomes low level. remark csiif1 : interrupt request flag trf : bit 3 of the automatic data transmit/receive control register (adtc) if the busy signal becomes inactive, the wait is canceled. if the sampled busy signal is inactive, sending or receiving of the next 8 bit data begins from the fall of the next serial clock cycle. furthermore, the busy signal is asynchronous with the serial clock, so even if the slave side inactivates the busy signal, it takes nearly 1 clock cycle at the most until it is sampled again. also, it takes another 0.5 clock cycle after sampling until data transmission resumes. therefore, in order to definitely cancel a wait state, it is necessary for the slave side to keep the busy signal for at least 1.5 clock cycles. figure 19-20 shows the timing of the busy signal and wait cancel. in this figure, an example of the case where the busy signal becomes active when sending or receiving starts is shown. sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy csiif1 si1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 trf busy input valid busy input clear wait 451 chapter 19 serial interface channel 1 figure 19-20. busy signal and wait cancel (busy0 = 0) (b) busy & strobe control option strobe control is a function for synchronizing the sending and receiving of data between a master device and slave device. when sending or receiving of 8 bit data ends, the strobe signal is output by the master device from pin stb/p23. through this means, the slave device can know the timing of the end of master data transmission. therefore, even if there is noise in the serial clock and bit slippage occurs, synchronization is maintained and bit slippage has no effect on transmission of the next byte. in the case that the strobe control option is used, the conditions shown below are necessary. ? set bit 5 (ate) of serial operation mode register 1 (csim1) at (1). ? set bit 2 (strb) of the automatic data transmit/receive control register (adtc) at (1). normally, busy control and strobe control are used simultaneously as handshake signals. in this case, together with output of the strobe signal from pin stb/p23, pin busy/p24 can be sampled and sending or receiving can wait while the busy signal is being input. if strobe control is not carried out, pin p23/stb can be used as a normal i/o port. operation timing when busy and strobe control are used is shown in figure 19-21. furthermore, if strobe control is used, the interrupt request flag (csiif1), set when sending or receiving ends, is set after the strobe signal is output. sck1 d7 so1 si1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy (active high) 1.5 clocks (min.) busy input cancel wait in the case where the busy signal becomes inactive directly when sampled busy input effective 452 chapter 19 serial interface channel 1 figure 19-21. operation timings when using busy & strobe control option (busy0 = 0) caution when trf is cleared, the so1 pin becomes low level. remark csiif1: interrupt request flag trf : bit 3 of the automatic data transmit/receive control register (adtc) sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 stb busy si1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 trf busy input valid busy input clear csiif1 453 chapter 19 serial interface channel 1 (c) bit slippage detection function through the busy signal during an automatic transmit/receive operation, noise occur in the serial clock signal output by the master device and bit slippage may occur in the slave device side serial clock. at this time, if the strobe control option is not used, this bit slippage will have an effect on sending of the next byte. in such a case, the busy control option can be used on the master device side and, by checking the busy signal during sending, bit slippage can be detected. bit slippage detection through the busy signal is accomplished as follows. the slave side outputs a busy signal after the serial clock rises on the 8th cycle of data sending or receiving (at this time, if application of the wait state by the busy signal is not desired, the busy signal is made inactive within 2 clock cycles). the master device side samples the busy signal in sync with the fall of the serial clocks front side. if no bit slippage is occurring, the busy signal will be inactive in sampling for 8 clock cycles. if the busy signal is found to be active in sampling, it is regarded as an occurrence of bit slippage error processing is executed (bit 4 (err) of the automatic data transmit/receive control register (adtc) is set at (1)). the operation timing of the bit slippage detection function through the busy signal is shown in figure 19-22. figure 19-22. operation timing of the bit slippage detection function through the busy signal (busy0 = 1) csiif1: interrupt request flag csie1 : bit 7 of serial operating mode register 1 (csim1) err : bit 4 of the automatic data transmit/receive control register (adtc) sck1 d7 so1 si1 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 busy csiif1 csie1 err d7 d7 no busy detection error interrrupt request generation error detection (slave side) sck1 (master side) bit slippage due to noise 454 chapter 19 serial interface channel 1 (5) automatic transmit/receive interval time when using the automatic transmit/receive function, the read/write operations from/to the buffer ram are performed after transmitting/receiving one byte. therefore, an interval is inserted before the next transmit/ receive. since the read/write operations from/to the buffer ram are performed in parallel with the cpu processing when using the automatic transmit/receive function by the internal clock, the interval depends on the value which is set in the automatic transmit/receive interval specification register (adti) and the cpu processing at the rising edge of the eighth serial clock. whether it depends on the adti or not can be selected by the setting of its bit 7 (adti7). when it is set to 0, the interval depends only on the cpu processing. when it is set to 1, the interval depends on the contents of the adti or cpu processing, whichever is greater. when the automatic transmit/receive function is used by an external clock, it must be selected so that the interval may be longer than the value indicated by paragraph (b). figure 19-23. automatic data transmit/receive interval csiif1: interrupt request flag sck1 so1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 csiif1 si1 d7d6d5d4d3d2d1d0 d7d6d5d4d3d2d1d0 interval 455 chapter 19 serial interface channel 1 (a) when the automatic transmit/receive function is used by the internal clock if bit 1 (csim11) of serial operation mode register 1 (csim1) is set at (1), the internal clock operates. if the automatic transmit/receive function is operated by the internal clock, interval timing by cpu processing is as follows. when bit 7 (adti7) of automatic data transmit/receive interval specify register (adti) is set to 0, the interval depends on the cpu processing. when adti7 is set to 1, it depends on the contents of the adti or cpu processing, whichever is greater. refer to figure 19-5. automatic data transmit/receive interval specify register format for the intervals which are set by the adti. table 19-2. interval timing through cpu processing (when the internal clock is operating) cpu processing interval time when using multiplication instruction max. (2.5t sck , 13t cpu ) when using division instruction max. (2.5t sck , 20t cpu ) external access 1 wait mode max. (2.5t sck , 9t cpu ) other than above max. (2.5t sck , 7t cpu ) t sck : 1/f sck f sck : serial clock frequency t cpu : 1/f cpu f cpu : cpu clock (set by bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc) and bit 0 (mcs) of the oscillation mode selection register (osms)) max. (a, b) : a or b, whichever is greater figure 19-24. operation timing with automatic data transmit/receive function performed by internal clock f x : main system clock oscillation frequency f cpu : cpu clock (set by bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc) and bit 0 (mcs) of the oscillation mode selection register (osms). t cpu : 1/f cpu t sck : 1/f sck f sck : serial clock frequency f x f cpu sck1 so1 si1 t cpu t sck d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 interval 456 chapter 19 serial interface channel 1 (b) when the automatic transmit/receive function is used by the external clock if bit 1 (csim11) of serial operating mode register 1 (csim1) is cleared to 0, external clock operation is set. when the automatic transmit/receive function is used by the external clock, it must be selected so that the interval may be longer than the values shown as follows. table 19-3. interval timing through cpu processing (when the external clock is operating) cpu processing interval time when using multiplication instruction 13t cpu or longer when using division instruction 20t cpu or longer external access 1 wait mode 9t cpu or longer other than above 7t cpu or longer t cpu : 1/f cpu f cpu : cpu clock (set by the bits 0 to 2 (pcc0 to pcc2) of the processor clock control register (pcc) and bit 0 (mcs) of the oscillation mode selection register (osms)) 457 chapter 20 serial interface channel 2 20.1 serial interface channel 2 functions serial interface channel 2 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode (1) operation stop mode this mode is used when serial transfer is not carried out to reduce power consumption. (2) asynchronous serial interface (uart) mode in this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. a dedicated uart baud rate generator is incorporated, allowing communication over a wide range of baud rates. in addition, the baud rate can be defined by scaling the input clock to the asck pin. the midi standard baud rate (31.25 kbps) can be used by employing the dedicated uart baud rate generator. (3) 3-wire serial i/o mode (msb-first/lsb-first switchable) in this mode, 8-bit data transfer is performed using three lines: the serial clock (sck2), and serial data lines (si2, so2). in the 3-wire serial i/o mode, simultaneous transmission and reception is possible, increasing the data transfer processing speed. either the msb or lsb can be specified as the start bit for an 8-bit data serial transfer, allowing connection to devices using either as the start bit. the 3-wire serial i/o mode is useful for connection to peripheral i/os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75x/xl series, 78k series, 17k series, etc. 458 chapter 20 serial interface channel 2 20.2 serial interface channel 2 configuration serial interface channel 2 consists of the following hardware. table 20-1. serial interface channel 2 configuration item configuration register transmit shift register (txs) receive shift register (rxs) receive buffer register (rxb) control register serial operating mode register 2 (csim2) asynchronous serial interface mode register (asim) asynchronous serial interface status register (asis) baud rate generator control register (brgc) port mode register 7 (pm7) note note refer to figure 6-15 block diagram of p70 and figure 6-16 block diagram of p71 and p72 . figure 20-1. serial interface channel 2 block diagram note see figure 20-2 for the baud rate generator configuration. internal bus rxe ps1 ps0 asynchronous serial interface mode register cl sl isrm txe sck pe fe ove asynchronous serial interface status register direction control circuit transmit shift register (txs/sio2) receive buffer register (rxb/sio2) direction control circuit receive shift register (rxs) reception control circuit transmission control circuit rxd/si2 /p70 txd/so2 /p71 pm71 intsr/intcsi2 isrm asck/sck2 /p72 csie2 csim 22 csck intser sck output control circuit baud rate generator f xx to f xx /2 10 mdl3 mdl2 mdl1 mdl0 4 internal bus tps3 tps2 tps1 tps0 4 csck sck csie2 txe rxe intst baud rate generator control register note serial operating mode register 2 pm72 459 chapter 20 serial interface channel 2 figure 20-2. baud rate generator block diagram tps3 tps2 tps1 tps0 internal bus mdl3 mdl2 mdl1 mdl0 baud rate generator control register 4 txe csie2 5-bit counter selector selector decoder 1/2 selector terminal clock 1/2 selector receive clock match match mdl0 to mdl3 5-bit counter rxe start bit detection selector f xx to f xx /2 10 tps0 to tps3 sck csck asck/sck2/p72 4 4 start bit sampling clock 460 chapter 20 serial interface channel 2 (1) transmit shift register (txs) this register is used to set the transmit data. the data written in txs is transmitted as serial data. if the data length is specified as 7 bits, bits 0 to 6 of the data written in txs are transferred as transmit data. writing data to txs starts the transmit operation. txs is written to with an 8-bit memory manipulation instruction. it cannot be read. txs value is ffh after reset input. caution txs must not be written to during a transmit operation. txs and the receive buffer register (rxb) are allocated to the same address, and when a read is performed, the value of rxb is read. (2) receive shift register (rxs) this register is used to convert serial data input to the rxd pin to parallel data. when one byte of data is received, the receive data is transferred to the receive buffer register (rxb). rxs cannot be directly manipulated by a program. (3) receive buffer register (rxb) this register holds receive data. each time one byte of data is received, new receive data is transferred from the receive shift register (rxs). if the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of rxb, and the msb of rxb is always set to 0. rxb is read with an 8-bit memory manipulation instruction. it cannot be written to. rxb value is ffh after reset input. caution rxb and the transmit shift register (txs) are allocated to the same address, and when a write is performed, the value is written to txs. (4) transmission control circuit this circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data written in the transmit shift register (txs) in accordance with the contents set in the asynchronous serial interface mode register (asim). (5) reception control circuit this circuit controls receive operations in accordance with the contents set in the asynchronous serial interface mode register (asim). it performs error checks for parity errors, etc., during a receive operation, and if an error is detected, sets a value in the asynchronous serial interface status register (asis) in accordance with the error contents. 461 chapter 20 serial interface channel 2 20.3 serial interface channel 2 control registers serial interface channel 2 is controlled by the following four registers. ? serial operating mode register 2 (csim2) ? asynchronous serial interface mode register (asim) ? asynchronous serial interface status register (asis) ? baud rate generator control register (brgc) (1) serial operating mode register 2 (csim2) this register is set when serial interface channel 2 is used in the 3-wire serial i/o mode. csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim2 to 00h. figure 20-3. serial operating mode register 2 format cautions 1. ensure that bits 0 and 3 to 6 are set to 0. 2. when uart mode is selected, csim2 should be set to 00h. 6543210 <7> symbol csim2 csie2 0 0 0 0 csim 22 csck 0 ff72h 00h r/w address after reset r/w csck 0 1 clock selection in 3-wire serial i/o mode input clock from off-chip to sck2 pin dedicated baud rate generator output csim22 0 1 first bit specification msb lsb csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled 462 chapter 20 serial interface channel 2 <6>543210 <7> symbol asim txe rxe ps1 ps0 cl sl isrm sck ff70h 00h r/w address after reset r/w sck 0 1 clock in asynchronous serial interface mode input clock from off-chip to asck pin dedicated baud rate generator output note isrm 0 1 control of reception completion interrupt in case of error generation reception completion interrupt request generated in case of error generation reception completion interrupt request not generated in case of error generation sl transmit data stop bit length specification cl 1 character length specification 7 bits 8 bits rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled ps1 0 1 01 bit 1 2 bits 0 parity bit specification no parity even parity ps0 0 1 0 parity always added in transmission no parity test in reception (parity error not generated) 0 1 1 odd parity 0 (2) asynchronous serial interface mode register (asim) this register is set when serial interface channel 2 is used in the asynchronous serial interface mode. asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim to 00h. figure 20-4. asynchronous serial interface mode register format note when sck is set to 1 and the baud rate generator output is selected, the asck pin can be used as an input/output port. cautions 1. when the 3-wire serial i/o mode is selected, 00h should be set in asim. 2. the serial transmit/receive operation must be stopped before changing the operating mode. 463 chapter 20 serial interface channel 2 table 20-2. serial interface channel 2 operating mode settings (1) operation stop mode (2) 3-wire serial i/o mode (3) asynchronous serial interface mode notes 1. can be used freely as port function. 2. can be used as p70 (cmos input/output) when only transmitter is used. remark x : dont care pmxx : port mode register pxx : port output latch p72/sck2 /asck pin functions p71/so2 /txd pin functions p70/si2 /rxd pin functions shift clock start bit txe rxe sck csie2 csim22 csck pm70 p70 pm71 p71 pm72 p72 asim csim2 0 00 1 1 0 1 0 1 0 1 1 note 2 x note 2 01 1 0 1 0 x 1 x 1 msb lsb external clock internal clock external clock internal clock si2 so2 (cmos output) sck2 input sck2 output sck2 input sck2 output other than above setting prohibited note 2 si2 note 2 so2 (cmos output) p72/sck2 /asck pin functions p71/so2 /txd pin functions p70/si2 /rxd pin functions shift clock start bit txe rxe sck csie2 csim22 csck pm70 p70 pm71 p71 pm72 p72 asim csim2 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 x note 1 x note 1 0 11 1 x x lsb external clock internal clock external clock internal clock external clock internal clock p70 txd (cmos output) asck input p72 asck input p72 asck input p72 p71 note 1 x x 1 0 1 0 1 1 1 x x x note 1 note 1 x rxd note 1 note 1 x note 1 x 01 1x txd (cmos output) note 1 x note 1 x other than above setting prohibited p72/sck2 /asck pin functions p71/so2 /txd pin functions p70/si2 /rxd pin functions shift clock start bit txe rxe sck csie2 csim22 csck pm70 p70 pm71 p71 pm72 p72 asim csim2 0 0x 0xx x note 1 x note 1 x note 1 x note 1 x note 1 x note 1 p70 p71 p72 other than above setting prohibited 464 chapter 20 serial interface channel 2 (3) asynchronous serial interface status register (asis) this is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode. asis is read with a 1-bit or 8-bit memory manipulation instruction. in 3-wire serial i/o mode, the contents of the asis are undefined. reset input sets asis to 00h. figure 20-5. asynchronous serial interface status register format pe 6543210 7 symbol asis 0 0 0 0 0 fe ove ff71h 00h r address after reset r/w ove 0 1 overrun error flag overrun error not generated overrun error generated note 1 (when next receive operation is completed before data from receive buffer register is read) fe 0 1 framing error flag framing error not generated framing error generated note 2 (when stop bit is not detected) pe 0 1 parity error flag parity error not generated parity error generated (when transmit data parity does not match) notes 1. the receive buffer register (rxb) must be read when an overrun error is generated. overrun errors will continue to be generated until rxb is read. 2. even if the stop bit length has been set as 2 bits by bit 2 (sl) of the asynchronous serial interface mode register, only single stop bit detection is performed during reception. 465 chapter 20 serial interface channel 2 (4) baud rate generator control register (brgc) this register sets the serial clock for serial interface channel 2. brgc is set with an 8-bit memory manipulation instruction. reset input sets brgc to 00h. figure 20-6. baud rate generator control register format (1/2) note can only be used in 3-wire serial i/o mode. remarks 1. f sck : 5-bit counter source clock 2. k : value set in mdl0 to mdl3 (0 k 14) baud rate generator input clock selection mdl3 mdl2 mdl1 mdl0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f sck /16 f sck /17 f sck /18 f sck /19 f sck /20 f sck /21 f sck /22 f sck /23 f sck /24 f sck /25 f sck /26 f sck /27 f sck /28 f sck /29 f sck /30 f sck note 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6543210 7 symbol brgc tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 ff73h 00h r/w address after reset r/w k 466 chapter 20 serial interface channel 2 figure 20-6. baud rate generator control register format (2/2) 5-bit counter source clock selection tps3 tps2 tps1 tps0 n mcs = 1 mcs = 0 0000f xx /2 10 f xx /2 10 (4.9 khz) f x /2 11 (2.4 khz) 11 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 1 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 2 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 3 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 4 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 5 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 6 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 7 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 8 1101f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 9 1110f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 10 other than above setting prohibited caution when a write is performed to brgc during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. therefore, brgc must not be written to during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. f xx : main system clock frequency (f x or f x /2) 3. mcs : bit 0 of oscillation mode selection register (osms) 4. n : value set in tps0 to tps3 (1 n 11) 5. figures in parentheses apply to operation with f x = 5.0 mhz. 467 chapter 20 serial interface channel 2 the baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the asck pin. (a) generation of baud rate transmit/receive clock by means of main system clock the transmit/receive clocks generated by scaling the main system clock. the baud rate generated from the main system clock is found from the following expression. [baud rate] = [hz] where, f x : main system clock oscillation frequency f xx : main system clock frequency (f x or f x /2) n : value set in tps0 to tps3 (1 n 11) k : value set in mdl0 to mdl3 (0 k 14) table 20-3. relationship between main system clock and baud rate fx = 5.0 mhz fx = 4.19 mhz mcs = 1 mcs = 0 mcs = 1 mcs = 0 brgc set value error (%) brgc set value error (%) brgc set value error (%) brgc set value error (%) 75 00h 1.73 0bh 1.14 ebh 1.14 110 06h 0.88 e6h 0.88 03h C2.01 e3h C2.01 150 00h 1.73 e0h 1.73 ebh 1.14 dbh 1.14 300 e0h 1.73 d0h 1.73 dbh 1.14 cbh 1.14 600 d0h 1.73 c0h 1.73 cbh 1.14 bbh 1.14 1200 c0h 1.73 b0h 1.73 bbh 1.14 abh 1.14 2400 b0h 1.73 a0h 1.73 abh 1.14 9bh 1.14 4800 a0h 1.73 90h 1.73 9bh 1.14 8bh 1.14 9600 90h 1.73 80h 1.73 8bh 1.14 7bh 1.14 19200 80h 1.73 70h 1.73 7bh 1.14 6bh 1.14 31250 74h 0 64h 0 71h C1.31 61h C1.31 38400 70h 1.73 60h 1.73 6bh 1.14 5bh 1.14 76800 60h 1.73 50h 1.73 5bh 1.14 mcs: bit 0 of oscillation mode selection register (osms) f xx 2 n x (k + 16) baud rate (bps) 468 chapter 20 serial interface channel 2 (b) generation of baud rate transmit/receive clock by means of external clock from asck pin the transmit/receive clock is generated by scaling the clock input from the asck pin. the baud rate generated from the clock input from the asck pin is obtained with the following expression. [baud rate] = [hz] f asck : frequency of clock input to asck pin k : value set in mdl0 to mdl3 (0 k 14) table 20-4. relationship between asck pin input frequency and baud rate (when brgc is set to 00h) baud rate (bps) asck pin input frequency 75 2.4 khz 110 3.52 khz 150 4.8 khz 300 9.6 khz 600 19.2 khz 1200 38.4 khz 2400 76.8 khz 4800 153.6 khz 9600 307.2 khz 19200 614.4 khz 31250 1000.0 khz 38400 1228.8 khz 2 x (k + 16) f asck 469 chapter 20 serial interface channel 2 20.4 serial interface channel 2 operation serial interface channel 2 has the following three modes. ? operation stop mode ? asynchronous serial interface (uart) mode ? 3-wire serial i/o mode 20.4.1 operation stop mode in the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced. in the operation stop mode, the p70/si2/rxd, p71/so2/txd and p72/sck2/asck pins can be used as normal input/output ports. (1) register setting operation stop mode is set using serial operating mode register 2 (csim2) and the asynchronous serial interface mode register (asim). (a) serial operating mode register 2 (csim2) csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim2 to 00h. csim 22 6543210 <7> symbol csim2 csie2 0 0 0 0 csck 0 ff72h 00h r/w address after reset r/w csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled caution ensure that bit 0 and bits 3 through 6 are set to 0. 470 chapter 20 serial interface channel 2 (b) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim to 00h. sl <6>543210 <7> symbol asim txe rxe ps1 ps0 cl isrm sck ff70h 00h r/w address after reset r/w rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled 471 chapter 20 serial interface channel 2 20.4.2 asynchronous serial interface (uart) mode in this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible. a dedicated uart baud rate generator is incorporated, allowing communication over a wide range of baud rates. in addition, the baud rate can be defined by scaling the input clock to the asck pin. the midi standard baud rate (31.25 kbps) can be used by employing the dedicated uart baud rate generator. (1) register setting uart mode is set using serial operating mode register 2 (csim2), the asynchronous serial interface mode register (asim), the asynchronous serial interface status register (asis), and the baud rate generator control register (brgc). (a) serial operating mode register 2 (csim2) csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim2 to 00h. when the uart mode is selected, 00h should be set in csim2. 6543210 <7> symbol csim2 csie2 0 0 0 0 csim 22 csck 0 csck 0 1 clock selection in 3-wire serial i/o mode input clock from off-chip to sck2 pin dedicated baud rate generator output csim22 0 1 first bit specification msb lsb csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled ff72h 00h r/w address after reset r/w caution ensure that bit 0 and bits 3 through 6 are set to 0. 472 chapter 20 serial interface channel 2 <6>543210 <7> symbol asim txe rxe ps1 ps0 cl sl isrm sck ff70h 00h r/w address after reset r/w sck 0 1 clock selection in asynchronous serial interface mode input clock from off-chip to asck pin dedicated baud rate generator output note isrm 0 1 control of reception completion interrupt in case of error generation reception completion interrupt request generated in case of error generation reception completion interrupt request not generated in case of error generation sl transmit data stop bit length specification cl 1 character length specification 7 bits 8 bits rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled ps1 0 1 01 bit 1 2 bits 0 parity bit specification no parity even parity ps0 0 1 0 parity always added in transmission no parity test in reception (parity error not generated) 0 1 1 odd parity 0 (b) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim to 00h. note when sck is set to 1 and the baud rate generator output is selected, the asck pin can be used as an input/output port. caution the serial transmit/receive operation must be stopped before changing the operating mode. 473 chapter 20 serial interface channel 2 (c) asynchronous serial interface status register (asis) asis is set with an 8-bit memory manipulation instruction. reset input sets asis to 00h. pe 6543210 7 symbol asis 0 0 0 0 0 fe ove ff71h 00h r address after reset r/w ove 0 1 overrun error flag overrun error not generated overrun error generated note 1 (when next receive operation is completed before data from receive buffer register is read) fe 0 1 framing error flag framing error not generated framing error generated note 2 (when stop bit is not detected) pe 0 1 parity error flag parity error not generated parity error generated (when transmit data parity does not match) notes 1. the receive buffer register (rxb) must be read when an overrun error is generated. overrun errors will continue to be generated until rxb is read. 2. even if the stop bit length has been set as 2 bits by bit 2 (sl) of the asynchronous serial interface mode register (asim), only single stop bit detection is performed during reception. 474 chapter 20 serial interface channel 2 (d) baud rate generator control register (brgc) brgc is set with an 8-bit memory manipulation instruction. reset input sets brgc to 00h. baud rate generator input clock selection mdl3 mdl2 mdl1 mdl0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 f sck /16 f sck /17 f sck /18 f sck /19 f sck /20 f sck /21 f sck /22 f sck /23 f sck /24 f sck /25 f sck /26 f sck /27 f sck /28 f sck /29 f sck /30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6543210 7 symbol brgc tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 ff73h 00h r/w address after reset r/w k 5-bit counter source clock selection tps3 tps2 tps1 tps0 n mcs = 1 mcs = 0 0000f xx /2 10 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) 11 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 1 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 2 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 3 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 4 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 5 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 6 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 7 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 8 1101f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 9 1110f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 10 other than above setting prohibited 475 chapter 20 serial interface channel 2 caution when a write is performed to brgc during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. therefore, brgc must not be written to during a communication operation. remarks 1. f sck : 5-bit counter source clock 2. k : value set in mdl0 to mdl3 (0 k 14) 3. f x : main system clock oscillation frequency 4. f xx : main system clock frequency (f x or f x /2) 5. mcs : bit 0 of oscillation mode selection register (osms) 6. n : value set in tps0 to tps3 (1 n 11) 7. figures in parentheses apply to operation with f x = 5.0 mhz. 476 chapter 20 serial interface channel 2 the baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the asck pin. (i) generation of baud rate transmit/receive clock by means of main system clock the transmit/receive clock is generated by scaling the main system clock. the baud rate generated from the main system clock is obtained with the following expression. [baud rate] = [hz] where, f x : main system clock oscillation frequency f xx : main system clock frequency (f x or f x /2) n : value set in tps0 to tps3 (1 n 11) k : value set in mdl0 to mdl3 (0 k 14) table 20-5. relationship between main system clock and baud rate fx = 5.0 mhz fx = 4.19 mhz mcs = 1 mcs = 0 mcs = 1 mcs = 0 brgc set value error (%) brgc set value error (%) brgc set value error (%) brgc set value error (%) 75 00h 1.73 0bh 1.14 ebh 1.14 110 06h 0.88 e6h 0.88 03h C2.01 e3h C2.01 150 00h 1.73 e0h 1.73 ebh 1.14 dbh 1.14 300 e0h 1.73 d0h 1.73 dbh 1.14 cbh 1.14 600 d0h 1.73 c0h 1.73 cbh 1.14 bbh 1.14 1200 c0h 1.73 b0h 1.73 bbh 1.14 abh 1.14 2400 b0h 1.73 a0h 1.73 abh 1.14 9bh 1.14 4800 a0h 1.73 90h 1.73 9bh 1.14 8bh 1.14 9600 90h 1.73 80h 1.73 8bh 1.14 7bh 1.14 19200 80h 1.73 70h 1.73 7bh 1.14 6bh 1.14 31250 74h 0 64h 0 71h C1.31 61h C1.31 38400 70h 1.73 60h 1.73 6bh 1.14 5bh 1.14 76800 60h 1.73 50h 1.73 5bh 1.14 mcs: bit 0 of oscillation mode selection register (osms) baud rate (bps) f xx 2 n x (k + 16) 477 chapter 20 serial interface channel 2 (ii) generation of baud rate transmit/receive clock by means of external clock from asck pin the transmit/receive clock is generated by scaling the clock input from the asck pin. the baud rate generated from the clock input from the asck pin is obtained with the following expression. [baud rate] = [hz] where, f asck : frequency of clock input to asck pin k : value set in mdl0 to mdl3 (0 k 14) table 20-6. relationship between asck pin input frequency and baud rate (when brgc is set to 00h) baud rate (bps) asck pin input frequency 75 2.4 khz 110 3.52 khz 150 4.8 khz 300 9.6 khz 600 19.2 khz 1200 38.4 khz 2400 76.8 khz 4800 153.6 khz 9600 307.2 khz 19200 614.4 khz 31250 1000.0 khz 38400 1228.8 khz 2 n x (k + 16) f asck 478 chapter 20 serial interface channel 2 (2) communication operation (a) data format the transmit/receive data format is shown in figure 20-7. figure 20-7. asynchronous serial interface transmit/receive data format one data frame consists of the following bits. ? start bit ................... 1 bit ? character bits ......... 7 bits/8 bits ? parity bit .................. even parity/odd parity/0 parity/no parity ? stop bit(s) ............... 1 bit/2 bits the specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out with asynchronous serial interface mode register (asim). when 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always 0. the serial transfer rate is selected by asim and the baud rate generator control register (brgc). if a serial data receive error is generated, the receive error contents can be determined by reading the status of the asynchronous serial interface status register (asis). d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit start bit one data frame character bit 479 chapter 20 serial interface channel 2 (b) parity types and operation the parity bit is used to detect a bit error in the communication data. normally, the same kind of parity bit is used on the transmitting side and the receiving side. with even parity and odd parity, a one-bit (odd number) error can be detected. with 0 parity and no parity, an error cannot be detected. (i) even parity ? at transmission control is executed so that the number of bits with a value of 1 contained in the transmit data including parity bit is an even number. the parity bit value should be as follows. the number of bits with a value of 1 is an odd number in transmit data : 1 the number of bits with a value of 1 is an even number in transmit data : 0 ? at reception the number of bits with a value of 1 contained in the receive data including parity bit are counted, and if this is an odd number, a parity error is generated. (ii) odd parity ? at transmission conversely to the situation with even parity, control is executed so that the number of bits with a value of 1 contained in the transmit data including parity bit is an odd number. the parity bit value should be as follows. the number of bits with a value of 1 is an odd number in transmit data : 0 the number of bits with a value of 1 is an even number in transmit data : 1 ? at reception the number of bits with a value of 1 contained in the receive data including parity bit are counted, and if this is an even number, a parity error is generated. (iii) 0 parity when transmitting, the parity bit is set to 0 irrespective of the transmit data. at reception, a parity bit check is not performed. therefore, a parity error is not generated, irrespective of whether the parity bit is set to 0 or 1. (iv) no parity a parity bit is not added to the transmit data. at reception, data is received assuming that there is no parity bit. since there is no parity bit, a parity error is not generated. 480 chapter 20 serial interface channel 2 (c) transmission a transmit operation is started by writing transmit data to the transmit shift register (txs). the start bit, parity bit, and stop bit(s) are added automatically. when the transmit operation starts, the data in the transmit shift register (txs) is shifted out, and when the transmit shift register (txs) is empty, a transmission completion interrupt request (intst) is generated. figure 20-8. asynchronous serial interface transmission completion interrupt request generation timing (a) stop bit length: 1 (b) stop bit length: 2 caution the asynchronous serial interface mode register (asim) should not be rewritten during a transmit operation. if the asim register is rewritten during transmission, subsequent transmit operations may not be possible (the normal state is restored by reset input). it is possible to determine whether transmission is in progress by software by using a transmission completion interrupt request (intst) or the interrupt request flag (stif) set by the intst. d1 d2 d6 d7 parity d0 txd (output) intst stop start d1 d2 d6 d7 parity d0 txd (output) intst stop start 481 chapter 20 serial interface channel 2 (d) reception when the rxe bit of the asynchronous serial interface mode register (asim) is set (1), a receive operation is enabled and sampling of the rxd pin input is performed. rxd pin input sampling is performed using the serial clock specified by asim. when the rxd pin input becomes low, the 5-bit counter of baud rate generaor (see figure 20-2 ) starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output. if the rxd pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is performed. when character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends. when one frame of data has been received, the receive data in the shift register is transferred to the receive buffer register (rxb), and a reception completion interrupt request (intsr) is generated. if an error is generated, the receive data in which the error was generated is still transferred to rxb. when an error is generated, if bit 1 (isrm) of asim is cleared to 0, intsr is generated. if isrm bit is set to 1, intsr is not generated. if the rxe bit is reset (0) during the receive operation, the receive operation is stopped immediately. in this case, the contents of rxb and asis are not changed, and intsr and intser are not generated. figure 20-9. asynchronous serial interface reception completion interrupt request generation timing caution the receive buffer register (rxb) must be read even if a receive error is generated. if rxb is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. d1 d2 d6 d7 parity d0 rxd (input) intsr stop start 482 chapter 20 serial interface channel 2 (e) receive errors three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error. if the data reception result error flag is set in the asynchronous serial interface status register (asis), a receive error interrupt request (intser) is generated. a receive error interrupt is generated prior to a receive completion interrupt request (intsr). receive error causes are shown in table 20-7. it is possible to determine what kind of error was generated during reception by reading the contents of asis in the reception error interrupt servicing (see figures 20-9 and 20-10 ). the contents of asis are reset (0) by reading the receive buffer register (rxb) or receiving the next data (if there is an error in the next data, the corresponding error flag is set). table 20-7. receive error causes receive errors cause parity error transmission-time parity specification and reception data parity do not match framing error stop bit not detected overrun error reception of next data is completed before data is read from receive register buffer figure 20-10. receive error timing note if a receive error is generated while bit 1 (isrm) of the asynchronous serial interface mode register (asim) is set to (1), intsr is not generated. cautions 1. the contents of the asynchronous serial interface status register (asis) are reset (0) by reading the receive buffer register (rxb) or receiving the next data. to ascertain the error contents, asis must be read before reading rxb. 2. the receive buffer register (rxb) must be read even if a receive error is generated. if rxb is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely. rxd (input) intsr note intser (when a framing error or an overrun error is generated) intser (when a parity error is generated) d0 d1 d2 d6 d7 stop start parity 483 chapter 20 serial interface channel 2 (3) uart mode cautions (a) when transmit operation is stopped by clearing (0) bit 7 (txe) of the asynchronous serial interface mode register (asim) during transmission, be sure to set the transmit shift register (txs) to ffh, then set the txe to 1, before executing the next transmission. (b) when receive operation is stopped by clearing (0) bit 6 (rxe) of the asynchronous serial interface mode register (asim) during reception, the state of the receive buffer register (rxb) and whether a receive completion interrupt request (intsr) is generated or not differ depending on the receive stop timing. figure 20-11 shows the timing. figure 20-11. state of receive buffer register (rxb) when receive operation is stopped and whether interrupt request (intsr) is generated or not when rxe is set to 0 at a time indicated by < 1 > , rxb holds the previous data and does not generate intsr. when rxe is set to 0 at a time indicated by < 2 > , rxb renews the data and does not generate intsr. when rxe is set to 0 at a time indicated by < 3 > , rxb renews the data and generates intsr. parity rxd pin rxb intsr < 3 > < 1 > < 2 > 484 chapter 20 serial interface channel 2 20.4.3 3-wire serial i/o mode the 3-wire serial i/o mode is useful for connection of peripheral i/os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75x/xl series, 78k series, 17k series, etc. communication is performed using three lines: the serial clock (sck2), serial output (so2), and serial input (si2). (1) register setting 3-wire serial i/o mode is set using serial operating mode register 2 (csim2), the asynchronous serial interface mode register (asim), and the baud rate generator control register (brgc). (a) serial operating mode register 2 (csim2) csim2 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets csim2 to 00h. caution ensure that bit 0 and bits 3 through 6 are set to 0. 6543210 <7> symbol csim2 csie2 0 0 0 0 csim 22 csck 0 csck 0 1 clock selection in 3-wire serial i/o mode input clock from off-chip to sck2 pin dedicated baud rate generator output csim22 0 1 first bit specification msb lsb csie2 0 1 operation control in 3-wire serial i/o mode operation stopped operation enabled ff72h 00h r/w address after reset r/w 485 chapter 20 serial interface channel 2 <6>543210 <7> symbol asim txe rxe ps1 ps0 cl sl isrm sck ff70h 00h r/w address after reset r/w sck 0 1 clock in asynchronous serial interface mode input clock from off-chip to asck pin dedicated baud rate generator output isrm 0 1 control of reception completion interrupt in case of error generation reception completion interrupt request generated in case of error generation reception completion interrupt request not generated in case of error generation sl transmit data stop bit length specification cl 1 character length specification 7 bits 8 bits rxe 0 1 receive operation control receive operation stopped receive operation enabled txe 0 1 transmit operation control transmit operation stopped transmit operation enabled ps1 0 1 01 bit 1 2 bits 0 parity bit specification no parity even parity ps0 0 1 0 parity always added in transmission no parity test in reception (parity error not generated) 0 1 1 odd parity 0 (b) asynchronous serial interface mode register (asim) asim is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets asim to 00h. when the 3-wire serial i/o mode is selected, 00h should be set in asim. 486 chapter 20 serial interface channel 2 (c) baud rate generator control register (brgc) brgc is set with an 8-bit memory manipulation instruction. reset input sets brgc to 00h. baud rate generator input clock selection mdl3 mdl2 mdl1 mdl0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f sck /16 f sck /17 f sck /18 f sck /19 f sck /20 f sck /21 f sck /22 f sck /23 f sck /24 f sck /25 f sck /26 f sck /27 f sck /28 f sck /29 f sck /30 f sck 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 6543210 7 symbol brgc tps3 tps2 tps1 tps0 mdl3 mdl2 mdl1 mdl0 ff73h 00h r/w address after reset r/w k f sck : 5-bit counter source clock k : value set in mdl0 to mdl3 (0 k 14) 487 chapter 20 serial interface channel 2 5-bit counter source clock selection tps3 tps2 tps1 tps0 n mcs = 1 mcs = 0 0000f xx /2 10 f x /2 10 (4.9 khz) f x /2 11 (2.4 khz) 11 0101f xx f x (5.0 mhz) f x /2 (2.5 mhz) 1 0110f xx /2 f x /2 (2.5 mhz) f x /2 2 (1.25 mhz) 2 0111f xx /2 2 f x /2 2 (1.25 mhz) f x /2 3 (625 khz) 3 1000f xx /2 3 f x /2 3 (625 khz) f x /2 4 (313 khz) 4 1001f xx /2 4 f x /2 4 (313 khz) f x /2 5 (156 khz) 5 1010f xx /2 5 f x /2 5 (156 khz) f x /2 6 (78.1 khz) 6 1011f xx /2 6 f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) 7 1100f xx /2 7 f x /2 7 (39.1 khz) f x /2 8 (19.5 khz) 8 1101f xx /2 8 f x /2 8 (19.5 khz) f x /2 9 (9.8 khz) 9 1110f xx /2 9 f x /2 9 (9.8 khz) f x /2 10 (4.9 khz) 10 other than above setting prohibited caution when a write is performed to brgc during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. therefore, brgc must not be written to during a communication operation. remarks 1. f x : main system clock oscillation frequency 2. f xx : main system clock frequency (f x or f x /2) 3. mcs : bit 0 of oscillation mode selection register (osms) 4. n : value set in tps0 to tps3 (1 n 11) 5. figures in parentheses apply to operation with f x = 5.0 mhz. 488 chapter 20 serial interface channel 2 when the internal clock is used as the serial clock in the 3-wire serial i/o mode, set brgc as described below. brgc setting is not required if an external serial clock is used. (i) when the baud rate generator is not used: select a serial clock frequency with tps0 through tps3. be sure then to set mdl0 through mdl3 to 1,1,1,1. the serial clock frequency becomes 1/2 of the source clock frequency for the 5-bit counter. (ii) when the baud rate generator is used: select a serial clock frequency with mdl0 through mdl3 and tps0 through tps3. be sure then to set mdl0 through mdl3 to 1,1,1,1. the serial clock frequency is calculated by the following formula. f xx serial clock frequency = [hz] 2 n x (k + 16) f x : main system clock oscillation frequency f xx : main system clock frequency (f x or f x /2) n : value set in tps0 to tps3 (1 n 11) k : value set in mdl0 to mdl3 (0 k 14) 489 chapter 20 serial interface channel 2 si2 sck2 12345678 di7 di6 di5 di4 di3 di2 di1 di0 so2 do7 do6 do5 do4 do3 do2 do1 do0 srif transfer start at the falling edge of sck2 end of transfer (2) communication operation in the 3-wire serial i/o mode, data transmission/reception is performed in 8-bit units. data is transmitted/ received bit by bit in synchronization with the serial clock. transmit shift register (txs/sio2) and receive shift register (rxs) shift operations are performed in synchronization with the fall of the serial clock (sck2). then transmit data is held in the so2 latch and output from the so2 pin. also, receive data input to the si2 pin is latched in the receive buffer register (rxb/sio2) on the rise of sck2. at the end of an 8-bit transfer, the operation of txs/sio2 and rxs stops automatically, and the interrupt request flag (srif) is set. figure 20-12. 3-wire serial i/o mode timing 490 chapter 20 serial interface channel 2 (3) msb/lsb switching as the start bit the 3-wire serial i/o mode enables to select transfer to start from msb or lsb. figure 20-13 shows the configuration of the transmit shift register (txs/sio2) and internal bus. as shown in the figure, msb/lsb can be read/written in reverse form. msb/lsb switching as the start bit can be specified with bit 2 (csim22) of the serial operating mode register 2 (csim2). figure 20-13. circuit of switching in transfer bit order start bit switching is realized by switching the bit order for data write to sio2. the sio2 shift order remains unchanged. thus, msb-first and lsb-first must be switched before writing data to the shift register. (4) transfer start serial transfer is started by setting transfer data to the transmission shift register (txs/sio2) when the following two conditions are satisfied. ? serial interface channel 2 operation control bit (csie2) = 1 ? internal serial clock is stopped or sck2 is a high level after 8-bit serial transfer. caution if csie2 is set to 1 after data write to txs/sio2, transfer does not start. upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (srif) is set. 7 6 internal bus 1 0 lsb-first msb-first read/write gate si2 transmit shift register (txs/sio2) read/write gate so2 sck2 dq so2 latch 491 chapter 20 serial interface channel 2 20.4.4 restrictions on using uart mode in the uart mode, a receive completion interrupt request (intsr) is generated after a certain period of time following the generation and clearing of the receive error interrupt request (intser). thereby, the phenomenon shown below may occur. details if the bit 1 (isrm) of the asynchronous serial interface mode register (asim) is set to 1, the setting is made such that receive completion interrupt request (intsr) will not be generated upon the generation of a receive error. however, in the receive error interrupt request (intser) servicing, if the receive buffer register (rxb) is read within a certain timing (a in figure 20-14), internal error flag is cleared (to 0). therefore, no receive error is judged to have been generated, and intsr, which is not supposed to be generated, will be generated. figure 20-14 illustrates the operation above. figure 20-14. receive completion interrupt request generation timing (isrm = 1) remark isrm : bit 1 of asynchronous serial interface mode register (asim) f sck : 5-bit counter source clock of baud rate generator rxb : receive buffer register to avoid this phenomenon, implement the following countermeasures. countermeasures ? in the case of framing error or overrun error prohibit the reading of the receive buffer register (rxb) for a certain period (t2 in figure 20-15) after the generation of a receive error interrupt request (intser). ? in the case of parity error prohibit the reading of the receive buffer register (rxb) for a certain period (t1 + t2 in figure 20-15) after the generation of a receive error interrupt request (intser). f sck intsr interrupt servicing routine on cpu side cleared upon reading rxb rxb reading intser (when framing or overrun error is generated) judged no receive error has been generated, and intsr is generated. error flag (internal flag) a 492 chapter 20 serial interface channel 2 figure 20-15. period that reading receive buffer register is prohibited t1 : the amount of time for one unit of data sent in the baud rate selected with the baud rate generator control register (brgc) (1/baud rate) t2 : the amount of time for 2 clocks of 5-bit counter source clock (f sck ) selected with brgc example of countermeasures an example of the countermeasures is shown below. [condition] f x = 5.0 mhz processor clock control register (pcc) = 00h oscillation mode selection register (osms) = 01h baud rate generator control register (brgc) = b0h (when 2400 bps is selected for baud rate) t cy = 0.4 m s (t cy = 0.2 m s) 1 t1 = = 416.7 m s 2400 t2 = 12.8 x 2 = 25.6 m s t1 + t2 = 2212 (clock) t cy rxd (input) intsr intser (when framing or overrun error is generated) intser (when parity error is generated) d0 t1 t2 d1 d2 d6 d7 stop start parity 493 chapter 20 serial interface channel 2 [example] intser is generated 7 clocks (min.) of cpu clock (time from interrupt request to servicing) instructions for 2205 clocks (min.) of cpu clock are required. uart receive error interrupt request (intser) servicing ei reti mov a,rxb main processing 494 [memo] 495 chapter 21 real-time output port 21.1 real-time output port functions data set previously in the real-time output buffer register can be transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation, then output externally. this is called the real-time output function. the pins that output data externally are called real-time output ports. by using a real-time output, a signal which has no jitter can be output. this port is therefore suitable for control of stepping motors, etc. port mode/real-time output port mode can be specified bit-wise. 21.2 real-time output port configuration the real-time output port consists of the following hardware. table 21-1. real-time output port configuration item configuration register real-time output buffer register (rtbl, rtbh) control register port mode register 12 (pm12) real-time output port mode register (rtpm) real-time output port control register (rtpc) figure 21-1. real-time output port block diagram internal bus real-time output port control register extr byte output trigger control circuit port mode register 12 (pm12) real-time output buffer register higher 4 bits (rtbh) real-time output buffer register lower 4 bits (rtbl) output latch p120 p127 real-time output port mode register (rtpm) intp2 inttm1 inttm2 496 chapter 21 real-time output port (1) real-time output buffer register (rtbl, rtbh) addresses of rtbl and rtbh are mapped individually in the special function register (sfr) area as shown in figure 21-2. when specifying 4 bits x 2 channels as the operating mode, data are set individually in rtbl and rtbh. when specifying 8 bits x 1 channel as the operating mode, data are set to both rtbl and rtbh by writing 8-bit data to either rtbl or rtbh. table 21-2 shows operations during manipulation of rtbl and rtbh. figure 21-2. real-time output buffer register configuration table 21-2. operation in real-time output buffer register manipulation in read note 1 in write note 2 higher 4 bits lower 4 bits higher 4 bits lower 4 bits rtbl rtbh rtbl invalid rtbl rtbh rtbh rtbl rtbh invalid rtbl rtbh rtbl rtbh rtbl rtbh rtbh rtbl rtbh rtbl notes 1. only the bits set in the real-time output port mode can be read. when a read is performed to the bits set in the port mode, 0 is read out. 2. after setting data in the real-time output port, output data should be set in rtbl and rtbh by the time a real-time output trigger is generated. higher 4 bits lower 4 bits rtbl rtbh ff30h ff31h operating mode register to be manipulated 4 bits x 2 channels 8 bits x 1 channel 497 chapter 21 real-time output port 21.3 real-time output port control registers the following three registers control the real-time output port. ? port mode register 12 (pm12) ? real-time output port mode register (rtpm) ? real-time output port control register (rtpc) (1) port mode register 12 (pm12) this register sets the input or output mode of port 12 pins (p120 to p127) which also function as real-time output pins (rtp0 to rtp7). to use port 12 as a real-time output port, the port pin that performs real-time output must be set in the output mode (pm12n = 0: n = 0 to 7). pm12 is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to ffh. figure 21-3. port mode register 12 format (2) real-time output port mode register (rtpm) this register selects the real-time output port mode/port mode bit-wise. rtpm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 21-4. real-time output port mode register format cautions 1. when using these bits as a real-time output port, set the ports to which real-time output is performed to the output mode (set the bits of the port mode register 12 (pm12) to 0). 2. in the port specified as a real-time output port, data cannot be set to the output latch. therefore, when setting an initial value, data should be set to the output latch before setting the real-time output mode. 7 rtpm7 6 rtpm6 5 rtpm5 4 rtpm4 3 rtpm3 2 rtpm2 1 rtpm1 0 rtpm0 symbol rtpm address ff34h 00h after reset r/w r/w rtpmn 0 1 port mode real-time output port mode real-time output port selection (n = 0 to 7) 7 pm127 6 pm126 5 pm125 4 pm124 3 pm123 2 pm122 1 pm121 0 pm120 symbol pm12 address ff2ch ffh after reset r/w r/w pm12n 0 1 output mode (output buffer on) input mode (output buffer off) selects i/o mode of p12n pin (n = 0 to 7) 498 chapter 21 real-time output port 7 0 symbol rtpc 6 0 5 0 4 0 3 0 2 0 <1> byte <0> extr address ff36h 00h after reset r/w r/w extr 0 1 real-time output control by intp2 intp2 not specified as real-time output trigger intp2 specified as real-time output trigger byte 0 1 real-time output port operating mode 4 bits x 2 channels 8 bits x 1 channel (3) real-time output port control register (rtpc) this register sets the real-time output port operating mode and output trigger. table 21-3 shows the relationship between the real-time output port operating mode and output trigger. rtpc is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets this register to 00h. figure 21-5. real-time output port control register format table 21-3. real-time output port operating mode and output trigger byte extr operating mode rtbh ? port output rtbl ? port output 0 inttm2 inttm1 1 inttm1 intp2 0 inttm1 1 intp2 4 bits x 2 channels 8 bits x 1 channel 0 1 499 chapter 22 interrupt functions 22.1 interrupt function types the following three types of interrupt functions are used. (1) non-maskable interrupt this interrupt is acknowledged unconditionally even in a disabled state. it does not undergo interrupt priority control and is given top priority over all other interrupt requests. it generates a standby release signal. the non-maskable interrupt has one source of interrupt request from the watchdog timer. (2) maskable interrupts these interrupts undergo mask control. maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register (pr0l, pr0h, and pr1l). multiple high priority interrupts can be applied to low priority interrupts. if two or more interrupts with the same priority are simultaneously generated, each interrupts has a predetermined priority (see table 22-1 ). a standby release signal is generated. the maskable interrupt has seven sources of external interrupt requests and fifteen sources of internal interrupt requests. (3) software interrupt this is a vectored interrupt to be generated by executing the brk instruction. it is acknowledged even in a disabled state. the software interrupt does not undergo interrupt priority control. 500 chapter 22 interrupt functions 22.2 interrupt sources and configuration there are total of 24 non-maskable, maskable, and software interrupts in the interrupt sources (see table 22-1 ). table 22-1. interrupt source list (1/2) interrupt source name trigger watchdog timer overflow (with watchdog timer mode 1 selected) watchdog timer overflow (with interval timer mode selected) 1 intp0 0006h (c) 2 intp1 0008h 3 intp2 000ah 4 intp3 pin input edge detection external 000ch (d) 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h end of serial interface channel 0 transfer end of serial interface channel 1 transfer serial interface channel 2 uart reception error generation end of serial interface channel 2 uart reception end of serial interface channel 2 3-wire transfer end of serial interface channel 2 uart transfer C intwdt (a) 0 intwdt (b) 8 intcsi0 0014h 9 intcsi1 0016h 11 001ah intsr intcsi2 12 intst 001ch interrupt type default priority note 1 internal/ external vector table address basic configuration type note 2 non- maskable internal internal (b) notes 1. default priorities are intended for two or more simultaneously generated maskable interrupt requests. 0 is the highest priority and 20 is the lowest priority. 2. basic configuration types (a) to (e) correspond to (a) to (e) of figure 22-1. maskable 0004h 10 intser 0018h 501 chapter 22 interrupt functions table 22-1. interrupt source list (2/2) interrupt source name trigger reference time interval signal from watch timer generation of 16-bit timer register, capture/compare register (cr00) match signal generation of 16-bit timer register, capture/compare register (cr01) match signal generation of 8-bit timer/event counter 1 match signal generation of 8 bit timer/event counter 2 match signal 18 intad end of a/d converter conversion 0028h generation of 8-bit timer/event counter 5 match signal generation of 8-bit timer/event counter 6 match signal software brk brk instruction execution 003eh (e) vector table address 14 inttm00 0020h 15 inttm01 0022h maskable 16 inttm1 internal 0024h (b) 17 inttm2 0026h 19 inttm5 002ah 20 inttm6 002ch notes 1. default priorities are intended for two or more simultaneously generated maskable interrupt requests. 0 is the highest priority and 20 is the lowest priority. 2. basic configuration types (a) to (e) correspond to (a) to (e) of figure 22-1. 13 inttm3 001eh default priority note 1 interrupt type internal/ external basic configuration type note 2 502 chapter 22 interrupt functions figure 22-1. basic configuration of interrupt function (1/2) (a) internal non-maskable interrupt internal bus priority control circuit vector table address generator standby release signal interrupt request (b) internal maskable interrupt internal bus ie pr isp mk if interrupt request priority control circuit vector table address generator standby release signal (c) external maskable interrupt (intp0) internal bus ie pr isp mk if priority control circuit vector table address generator standby release signal interrupt request sampling clock edge detector sampling clock select register (scs) external interrupt mode register (intm0) 503 chapter 22 interrupt functions figure 22-1. basic configuration of interrupt function (2/2) (d) external maskable interrupt (except intp0) (e) software interrupt external interrupt mode register (intm0, intm1) edge detector interrupt request ie pr isp mk if priority control circuit vector table address generator standby release signal internal bus internal bus priority control circuit vector table address generator interrupt request if : interrupt request flag ie : interrupt enable flag isp : inservice priority flag mk : interrupt mask flag pr : priority specify flag 504 chapter 22 interrupt functions 22.3 interrupt function control registers the following six types of registers are used to control the interrupt functions. ? interrupt request flag register (if0l, if0h, if1l) ? interrupt mask flag register (mk0l, mk0h, mk1l) ? priority specify flag register (pr0l, pr0h, pr1l) ? external interrupt mode register (intm0, intm1) ? sampling clock select register (scs) ? program status word (psw) table 22-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding to interrupt request sources. table 22-2. various flags corresponding to interrupt request sources interrupt source interrupt request flag interrupt mask flag priority specify flag register register register intwdt tmif4 if0l tmmk4 mk0l tmpr4 pr0l intp0 pif0 pmk0 ppr0 intp1 pif1 pmk1 ppr1 intp2 pif2 pmk2 ppr2 intp3 pif3 pmk3 ppr3 intp4 pif4 pmk4 ppr4 intp5 pif5 pmk5 ppr5 intp6 pif6 pmk6 ppr6 intcsi0 csiif0 if0h csimk0 mk0h csipr0 pr0h intcsi1 csiif1 csimk1 csipr1 intser serif sermk serpr intsr/intcsi2 srif srmk srpr intst stif stmk stpr inttm3 tmif3 tmmk3 tmpr3 inttm00 tmif00 tmmk00 tmpr00 inttm01 tmif01 tmmk01 tmpr01 inttm1 tmif1 if1l tmmk1 mk1l tmpr1 pr1l inttm2 tmif2 tmmk2 tmpr2 intad adif admk adpr inttm5 tmif5 tmmk5 tmpr5 inttm6 tmif6 tmmk6 tmpr6 505 chapter 22 interrupt functions (1) interrupt request flag registers (if0l, if0h, if1l) the interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. it is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of reset input. if0l, if0h, and if1l are set with a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register if0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to 00h. figure 22-2. interrupt request flag register format note wtif is test input flag. vectored interrupt request is not generated. cautions 1. tmif4 flag is r/w enabled only when a watchdog timer is used as an interval timer. if used in the watchdog timer mode 1, set tmif4 flag to 0. 2. set always 0 in if1l bit 5 and bit 6. <7> pif6 symbol if0l <6> pif5 <5> pif4 <4> pif3 <3> pif2 <2> pif1 <1> pif0 <0> tmif4 address ffe0h 00h after reset r/w r/w xxifx 0 1 interrupt request flag no interrupt request signal interrupt request signal is generated; interrupt request state <7> tmif01 if0h <6> tmif00 <5> tmif3 <4> stif <3> srif <2> serif <1> csiif1 <0> csiif0 <7> wtif note if1l 6 0 5 0 <4> tmif6 <3> tmif5 <2> adif <1> tmif2 <0> tmif1 ffe1h 00h r/w ffe2h 00h r/w 506 chapter 22 interrupt functions (2) interrupt mask flag registers (mk0l, mk0h, mk1l) the interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. mk0l, mk0h, and mk1l are set with a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register mk0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 22-3. interrupt mask flag register format note wtmk controls standby mode release enable/disable and does not control interrupt functions. cautions 1. if tmmk4 flag is read when a watchdog timer is used in the watchdog timer mode 1, the read value becomes undefined. 2. because port 0 has a dual function as the external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. therefore, 1 should be set in the interrupt mask flag before using the output mode. 3. set always 1 in mk1l bit 5 and bit 6. <7> pmk6 symbol mk0l <6> pmk5 <5> pmk4 <4> pmk3 <3> pmk2 <2> pmk <1> pmk <0> tmmk4 address ffe4h ffh after reset r/w r/w xx mk x 0 1 interrupt servicing control interrupt servicing enabled interrupt servicing disabled <7> tmmk01 mk0h <6> tmmk00 <5> tmmk3 <4> stmk <3> srmk <2> sermk <1> csimk1 <0> csimk0 <7> wtmk note mk1l 6 1 5 1 <4> tmmk6 <3> tmmk5 <2> admk <1> tmmk2 <0> tmmk1 ffe5h ffh r/w ffe6h ffh r/w 507 chapter 22 interrupt functions (3) priority specify flag registers (pr0l, pr0h, pr1l) the priority specify flag is used to set the corresponding maskable interrupt priority orders. pr0l, pr0h, and pr1l are set with a 1-bit or 8-bit memory manipulation instruction. if if0l and if0h are used as a 16-bit register pr0, use a 16-bit memory manipulation instruction for the setting. reset input sets these registers to ffh. figure 22-4. priority specify flag register format cautions 1. when a watchdog timer is used in the watchdog timer mode 1, set 1 in tmpr4 flag. 2. set always 1 in pr1l bit 5 to bit 7. <7> ppr6 symbol pr0l <6> ppr5 <5> ppr4 <4> ppr3 <3> ppr2 <2> ppr1 <1> ppr0 <0> tmpr4 address ffe8h ffh after reset r/w r/w 0 1 priority level selection high priority level low priority level <7> tmpr01 pr0h <6> tmpr00 <5> tmpr3 <4> stpr <3> srpr <2> serpr <1> csipr1 <0> csipr0 7 1 pr1l 6 1 5 1 <4> tmpr6 <3> tmpr5 <2> adpr <1> tmpr2 <0> tmpr1 ffe9h ffh r/w ffeah ffh r/w xx pr x 508 chapter 22 interrupt functions address ffech 00h after reset r/w r/w 0 0 1 1 intp0 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es11 7 es31 symbol intm0 6 es30 5 es21 4 es20 3 es11 2 es10 1 0 0 0 0 1 0 1 es10 0 0 1 1 intp1 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es21 0 1 0 1 es20 0 0 1 1 intp2 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es31 0 1 0 1 es30 (4) external interrupt mode register (intm0, intm1) these registers set the valid edge for intp0 to intp6. intm0 and intm1 are set by 8-bit memory manipulation instructions. reset input sets these registers to 00h. figure 22-5. external interrupt mode register 0 format caution set 0, 0, 0 to bits 1 through 3 (tmc01 through tmc03) of the 16-bit timer mode control register (tmc0) and stop the timer operation before setting the valid edges of intp0/ti00/ p00 pin. 509 chapter 22 interrupt functions address ffedh 00h after reset r/w r/w 0 0 1 1 intp3 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es41 7 es71 symbol intm1 6 es70 5 es61 4 es60 3 es51 2 es50 1 es41 0 es40 0 1 0 1 es40 0 0 1 1 intp4 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es51 0 1 0 1 es50 0 0 1 1 intp5 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es61 0 1 0 1 es60 0 0 1 1 intp6 valid edge selection falling edge rising edge setting prohibited both falling and rising edges es71 0 1 0 1 es70 figure 22-6. external interrupt mode register 1 format 510 chapter 22 interrupt functions address ff47h 00h after reset r/w r/w 0 0 1 1 intp0 sampling clock selection f xx /2 n f xx /2 7 f xx /2 5 f xx /2 6 scs1 7 0 symbol scs 6 0 5 0 4 0 3 0 2 0 1 scs1 0 scs0 0 1 0 1 scs0 mcs = 1 mcs = 0 f x /2 7 (39.1 khz) f x /2 5 (156.3 khz) f x /2 6 (78.1 khz) f x /2 8 (19.5 khz) f x /2 6 (78.1 khz) f x /2 7 (39.1 khz) (5) sampling clock select register (scs) this register is used to set the valid edge clock sampling clock to be input to intp0. when remote controlled data reception is carried out using intp0, digital noise is removed with sampling clocks. scs is set with an 8-bit memory manipulation instruction. reset input sets scs to 00h. figure 22-7. sampling clock select register format caution f xx /2 n is a clock to be supplied to the cpu and f xx /2 5 , f xx /2 6 and f xx /2 7 are clocks to be supplied to the peripheral hardware. f xx /2 n stops in the halt mode. remarks 1. n : value (n = 0 to 4) at bits 0 to 2 (pcc0 to pcc2) of processor clock control register 2. f xx : main system clock frequency (f x or f x /2) 3. f x : main system clock oscillation frequency 4. mcs : bit 0 of oscillation mode selection register (osms) 5. figures in parentheses apply to operation with f x = 5.0 mhz. 511 chapter 22 interrupt functions t smp sampling clock intp0 pif0 ? because intp0 level is not active in sampling, pif0 output remains at low level. when the setting intp0 input level is active twice in succession, the noise eliminator sets interrupt request flag (pif0) to 1. figure 22-8 shows the noise eliminator input/output timing. figure 22-8. noise eliminator input/output timing (during rising edge detection) (a) when input is less than the sampling cycle (t smp ) (b) when input is equal to or twice the sampling cycle (t smp ) (c) when input is twice or more than the cycle frequency (t smp ) t smp sampling clock intp0 pif0 because sampling intp0 level is active twice in succession in <2>, pif0 flag is set to 1. <1> <2> t smp sampling clock intp0 pif0 when intp0 level is active twice in succession, pif0 flag is set to 1. 512 chapter 22 interrupt functions 7 ie psw 6 z 5 rbs1 4 ac 3 rbs0 2 0 1 isp 0 cy 02h after reset isp 0 used when normal instruction is executed priority of interrupt currently being received high-priority interrupt servicing (low-priority interrupt disable) 1 interrupt request not acknowledged or low-priority interrupt servicing (all-maskable interrupts enable) ie interrupt request acknowledge enable/disable 0 disable 1 enable (6) program status word (psw) the program status word is a register to hold the instruction execution result and the current status for interrupt request. the ie flag to set maskable interrupt enable/disable and the isp flag to control multiple interrupt servicing are mapped. besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (ei and di). when a vectored interrupt request is acknowledged, and when the brk instruction is executed, the contents of psw automatically is saved into a stack and the ie flag is reset to 0. if a maskable interrupt request is acknowledged contents of the priority specify flag of the acknowledged interrupt are transferred to the isp flag. the acknowledged contents of psw is also saved into the stack with the push psw instruction. it is reset from the stack with the reti, retb, and pop psw instructions. reset input sets psw to 02h. figure 22-9. program status word format 513 chapter 22 interrupt functions 22.4 interrupt servicing operations 22.4.1 non-maskable interrupt request acknowledge operation a non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. it does not undergo interrupt priority control and has highest priority over all other interrupts. if a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stacks, psw and pc, in that order, the ie and isp flags are reset to 0, and the vector table contents are loaded into pc and branched. a new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following reti instruction execution) and one main routine instruction is executed. if a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution. figure 22-10 shows the flowchart from non-maskable interrupt request generation to acknowledge. figure 22- 11 shows the non-maskable interrupt request acknowledge timing. figure 22-12 shows the acknowledge operation if multiple non-maskable interrupt requests are generated. 514 chapter 22 interrupt functions figure 22-10. flowchart from non-maskable interrupt generation to acknowledge wdtm4 = 1 (with watchdog timer mode selected)? overflow in wdt? wdtm3 = 0 (with non-maskable interrupt selected)? interrupt request generation wdt interrupt servicing? interrupt control register unaccessed? interrupt service start interrupt request held pending reset processing interval timer start no yes yes no yes no yes no yes no wdtm : watchdog timer mode register wdt : watchdog timer figure 22-11. non-maskable interrupt request acknowledge timing tmif4 : watchdog timer interrupt request flag instruction the interrupt request generated in this period is acknowledged at timing. instruction cpu instruction tmif4 psw and pc save, jump to interrupt servicing interrupt sevicing program 515 chapter 22 interrupt functions figure 22-12. non-maskable interrupt request acknowledge operation (a) if a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution (b) if two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution nmi request <2> nmi request <1> 1 instruction execution main routine nmi request <1> execute nmi request <2> reserve reserved nmi request <2> processing nmi request <3> nmi request <2> nmi request <1> 1 instruction execution main routine nmi request <1> execute nmi request <2> reserve nmi request <3> reserve reserved nmi request <2> processing nmi request <3> not acknowledged (only 1 nmi request is acknowledged even if two or more nmi requests are generated.) 516 chapter 22 interrupt functions 22.4.2 maskable interrupt request acknowledge operation a maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (mk) flag is cleared to 0. a vectored interrupt request is acknowledged in an interrupt enable state (with ie flag set to 1). however, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with isp flag reset to 0). wait times maskable interrupt request generation to interrupt servicing are shown in figure 22-3. refer to figures 22-14 and 22-15 for the interrupt request acknowledge timing. table 22-3. times from maskable interrupt request generation to interrupt service minimum time maximum time note when xxprx = 0 7 clocks 32 clocks when xxprx = 1 8 clocks 33 clocks note if an interrupt request is generated just before a divide instruction, the wait time is maximized. remark 1 clock: (f cpu : cpu clock) if two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is acknowledged first. if two or more requests are specified for the same priority with the priority specify flag, the interrupt request with the higher default priority is acknowledged first. any reserved interrupt requests are acknowledged when they become acknowledgeable. figure 22-13 shows interrupt request acknowledge algorithms. when a maskable interrupt request is acknowledged, the contents of program status word (psw) and program counter (pc) are saved to stacks, in this order. then, the ie flag is reset (to 0), and the value of the acknowledged interrupt priority specify flag is transferred to the isp flag. further, the vector table data determined for each interrupt request is loaded into pc and branched. return from the interrupt is possible with the reti instruction. f cpu 1 517 chapter 22 interrupt functions figure 22-13. interrupt request acknowledge processing algorithm xxif : interrupt request flag xxmk : interrupt mask flag xxpr : priority specify flag ie : flag to control maskable interrupt request acknowledge isp : flag to indicate the priority of interrupt being serviced (0 = an interrupt with higher priority is being serviced, 1 = interrupt request is not acknowledged or an interrupt with lower priority is being serviced) start xxif = 1? xxmk = 0? xxpr = 0? any simultaneously generated high-priority interrupt requests? any simultaneously generated xxpr = 0 interrupt requests? ie = 1? isp = 1? vectored interrupt servicing interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve interrupt request reserve vectored interrupt servicing any high- priority interrupt among simultaneously generated xx pr = 0 interrupt requests? ie = 1? yes (high priority) yes no yes no no no yes (interrupt request generation) no yes no (low priority) yes yes no yes yes no no 518 chapter 22 interrupt functions figure 22-14. interrupt request acknowledge timing (minimum time) remark 1 clock: (f cpu : cpu clock) figure 22-15. interrupt request acknowledge timing (maximum time) remark 1 clock: (f cpu : cpu clock) 22.4.3 software interrupt request acknowledge operation a software interrupt request is acknowledged by brk instruction execution. software interrupt cannot be disabled. if a software interrupt is acknowledged, the contents of program status word (psw) and program counter (pc) are saved to stacks, in this order. then the ie flag is reset (to 0), and the contents of the vector tables (003eh and 003fh) are loaded into pc and branched. return from the software interrupt is possible with the retb instruction. caution do not use the reti instruction for returning from the software interrupt. f cpu 1 instruction divide instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 33 clocks 32 clocks cpu processing xxif (xxpr = 1) xxif (xxpr = 0) 25 clocks f cpu 1 instruction instruction psw and pc save, jump to interrupt servicing 6 clocks interrupt servicing program 8 clocks 7 clocks cpu processing xxif (xxpr = 1) xxif (xxpr = 0) 519 chapter 22 interrupt functions 22.4.4 multiple interrupt servicing a multiple interrupt consists in acknowledging another interrupt during the execution of the interrupt. a multiple interrupt is generated only in the interrupt request acknowledge enable state (ie = 1) (except non- maskable interrupt). as soon as an interrupt request is acknowledged, it enters the acknowledge disable state (ie = 0). therefore, in order to enable a multiple interrupt, it is necessary to set the interrupt enable state by setting the ie flag (1) with the ei instruction during interrupt servicing. even in an interrupt enabled state, a multiple interrupt may not be enabled. however, it is controlled according to the interrupt priority. there are two priorities, the default priority and the programmable priority. the multiple interrupt is controlled by the programmable priority control. if an interrupt request with the same or higher priority than that of the interrupt being serviced is generated, it is acknowledged as a multiple interrupt. in the case of an interrupt with a priority lower than that of the interrupt being processed, it is not acknowledged as a multiple interrupt. interrupt request not acknowledged as a multiple interrupt due to interrupt disable or a low priority is reserved and acknowledged following one instruction execution of the main processing after the completion of the interrupt being serviced. during non-maskable interrupt servicing, multiple interrupts are not enabled. table 22-4 shows an interrupt request enabled for multiple interrupt during interrupt servicing, and figure 22- 16 shows multiple interrupt examples. table 22-4. interrupt request enabled for multiple interrupt during interrupt servicing maskable interrupt request xxpr = 0 xxpr = 1 ie = 1 ie = 0 ie = 1 ie = 0 non-maskable interrupt d d d d d isp = 0 e e d d d isp = 1 e e d e d software interrupt e e d e d remarks 1. e : multiple interrupt enable 2. d : multiple interrupt disable 3. isp and ie are the flags contained in psw isp = 0 : an interrupt with higher priority is being serviced isp = 1 : an interrupt request is not accepted or an interrupt with lower priority is being serviced ie = 0 : interrupt request acknowledge is disabled ie = 1 : interrupt request acknowledge is enabled 4. xxpr is a flag contained in pr0l, pr0h, and pril xxpr = 0 : higher priority level xxpr = 1 : lower priority level non-maskable interrupt request multiple interrupt request interrupt being serviced maskable interrupt 520 chapter 22 interrupt functions figure 22-16. multiple interrupt example (1/2) example 1. two multiple interrupts generated during interrupt intxx servicing, two interrupt requests, intyy and intzz are acknowledged, and a multiple interrupt is generated. an ei instruction is issued before each interrupt request acknowledge, and the interrupt request acknowledge enable state is set. example 2. multiple interrupt is not generated by priority control the interrupt request intyy generated during interrupt intxx servicing is not acknowledged because the interrupt priority is lower than that of intxx, and a multiple interrupt is not generated. intyy request is retained and acknowledged after execution of 1 instruction execution of the main processing. pr = 0 : higher priority level pr = 1 : lower priority level ie = 0 : interrupt request acknowledge disable main processing ei intxx (pr = 1) intyy (pr = 0) ie = 0 ei reti intxx servicing intzz (pr = 0) ie = 0 ei reti intyy servicing ie = 0 reti intzz servicing main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 1) ei ie = 0 ei reti reti 521 chapter 22 interrupt functions figure 22-16. multiple interrupt example (2/2) example 3. a multiple interrupt is not generated because interrupts are not enabled because interrupts are not enabled in interrupt intxx servicing (an ei instruction is not issued), interrupt request intyy is not acknowledged, and a multiple interrupt is not generated. the intyy request is reserved and acknowledged after 1 instruction execution of the main processing. pr = 0 : higher priority level ie = 0 : interrupt request acknowledge disable main processing intxx servicing intyy servicing intxx (pr = 0) 1 instruction execution ie = 0 intyy (pr = 0) ie = 0 reti reti ei 522 chapter 22 interrupt functions 22.4.5 interrupt request reserve some instructions may reserve the acknowledge of an instruction request until the completion of the execution of the next instruction even if the interupt request is generated during the execution. the following shows such instructions (interrupt request reserve instruction). ? mov psw, #byte ? mov a, psw ? mov psw, a ? mov1 psw.bit, cy ? mov1 cy, psw.bit ? and1 cy, psw.bit ? or1 cy, psw.bit ? xor1 cy, psw.bit ? set1/clr1 psw.bit ? retb ? reti ? push psw ? pop psw ? bt psw.bit, $addr16 ? bf psw.bit, $addr16 ? btclr psw.bit, $addr16 ?ei ?di ? manipulate instructions for if0l, if0h, if1l, mk0l, mk0h, mk1l, pr0l, pr0h, pr1l, intm0, intm1 registers caution brk instruction is not an interrupt request reserve instruction described above. however, in a software interrupt started by the execution of brk instruction, the ie flag is cleared to 0. therefore, interrupt requests are not acknowledged even when a maskable interrupt request is issued during the execution of the brk instruction. however, non-maskable interrupt requests are acknowledged. figure 22-17 shows the interrupt request hold timing. figure 22-17. interrupt request hold remarks 1. instruction n: instruction that holds interrupts requests 2. instruction m: instructions other than interrupt request pending instruction 3. the xxpr (priority level) values do not affect the operation of xxif (interrupt request). cpu processing xxif instruction n instruction m save psw and pc, jump to interrupt service interrupt service program 523 chapter 22 interrupt functions 22.5 test functions in this function, when the watch timer overflows and when a rising edge of port 4 is detected, the corresponding test input flag is set (1), and a standby release signal is generated. unlike the interrupt function, vectored processing is not performed. there are two test input factors as shown in table 22-5. the basic configuration is shown in figure 22-18. table 22-5. test input factors test input factors name trigger intwt clock timer overflow internal intpt4 negative edge detection at port 4 external figure 22-18. basic configuration of test function if : test input flag mk: test mask flag 22.5.1 registers controlling the test function the test function is controlled by the following three registers. ? interrupt request flag register 1l (if1l) ? interrupt mask flag register 1l (mk1l) ? key return mode register (krm) the names of the test input flag and test mask flag corresponding to the test input signals are listed in table 22-6. table 22-6. flags corresponding to test input signals test input signal name test input flag test mask flag intwt wtif wtmk intpt4 krif krmk internal/ external internal bus mk if test input signal standby release signal 524 chapter 22 interrupt functions (1) interrupt request flag register 1l (if1l) it indicates whether a clock timer overflow is detected or not. it is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. it is set to 00h by the reset signal input. figure 22-19. format of interrupt request flag register 1l caution set bits 5 and 6 to 0. (2) interrupt mask flag register 1l (mk1l) it is used to set the standby mode enable/disable at the time the standby mode is released by the clock timer. it is set by a 1-bit memory manipulation instruction and 8-bit memory manipulation instruction. it is set to ffh by the reset signal input. figure 22-20. format of interrupt mask flag register 1l caution set bits 5 and 6 to 1. <7> wtif symbol if1l 6 0 5 0 <4> tmif6 <3> tmif5 <2> adif <1> tmif2 <0> tmif1 address ffe2h 00h after reset r/w r/w 0 1 clock timer overflow detection flag not detected detected wtif <7> wtmk symbol mk1l 6 1 5 1 <4> tmmk6 <3> tmmk5 <2> admk <1> tmmk2 <0> tmmk1 address ffe6h ffh after reset r/w r/w 0 1 standby mode control by clock timer enables releasing the standby mode. disables releasing the standby mode. wtmk 525 chapter 22 interrupt functions (3) key return mode register (krm) this register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge detection). krm is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets krm to 02h. figure 22-21. key return mode register format caution when port 4 falling edge detection is used, clear krif to 0 (not cleared to 0 automatically). 22.5.2 test input signal acknowledge operation (1) internal test signal if the watch timer overflows, an internal test input signal (intwt) is generated, by which the wtif flag is set. at this time, if it is not masked with the interrupt mask flag (wtmk), a standby release signal is generated. the watch function is available by checking the wtif flag at a shorter cycle than the watch timer overflow cycle. (2) external test signal when a falling edge is input to the port 4 (p40 to p47) pins, an external test input signal (intpt4) is generated, by which the krif flag is set. at this time, if it is not masked with the interrupt mask flag (krmk), a standby release signal is generated. if port 4 is used as key matrix return signal input, whether or not a key input has been applied can be checked from the krif status. 7 0 symbol krm 6 0 5 0 4 0 3 0 2 0 <1> krmk <0> krif address fff6h 02h after reset r/w r/w 0 1 key return signal not detected detected (port 4 rising edge detection) krif 0 1 standby mode control by key return signal standby mode release enabled standby mode release disabled krmk 526 [memo] 527 chapter 23 external device expansion function 23.1 external device expansion functions the external device expansion functions connect external devices to areas other than the internal rom, ram, and sfr. the external device expansion function can be used in the following two modes: ? multiplexed bus mode ? separate bus mode (1) multiplexed bus mode external devices are connected via the multiplexed address/data bus. connecting external devices using this mode may reduce the number of ports to be used. in this mode, ports 4 through 6 are used for control of address/data, reafd/write strobe, wait, address strobe as shown below. table 23-1. pin functions in external memory expansion mode pin function at external device connection alternate function name function ad0 to ad7 multiplexed address/data bus p40 to p47 a8 to a15 upper address bus p50 to p57 rd read strobe signal p64 wr write strobe signal p65 wait wait signal p66 astb address strobe signal p67 table 23-2. state of port 4 to port 6 pins in external memory expansion mode ports and bits port 4 port 5 port 6 modes 0 to 7 0 1 2 3 4 5 6 7 0 to 3 4 to 7 single-chip mode port port port port 256-byte expansion mode address/data port port rd, wr, wait, astb 4-kbyte expansion mode address/data address port port rd, wr, wait, astb 16-kbyte expansion mode address/data address port port rd, wr, wait, astb full address mode address/data address port rd, wr, wait, astb caution when the external wait function is not used, the wait pin can be used as a port in all modes. 528 chapter 23 external device expansion function (2) separate bus mode external devices are connected using independent address and data buses. this connection requires no latches externally, resulting in reduction of external parts and area on the mounting board. in this mode, ports 4 through 6 and port 8 are used for control of address/data, reafd/write strobe, wait as shown below. table 23-3. pin functions in separate bus mode pin function in separate bus mode alternate function name function ad0 to ad7 multiplexed address/data bus p40 to p47 a0 to a7 lower address bus p80 to p87 a8 to a15 upper address bus p50 to p57 rd read strobe signal p64 wr write strobe signal p65 wait wait signal p66 caution in this mode, the address strobe signal is not required to be used though it is output from the astb/p67 pin. the output timings are shown in figures 23-9 through 23- 12. table 23-4. state of port 4 to port 6 and port 8 pins in separate bus mode ports and bits port 4 port 8 port 5 port 6 modes 0 to 7 0 to 7 0 1 2 3 4 5 6 7 0 to 3 4 to 7 single-chip mode port port port port port 256-byte expansion mode data address port port rd, wr, wait, (astb) 4-kbyte expansion mode data address address port port rd, wr, wait, (astb) 16-kbyte expansion mode data address address port port rd, wr, wait, (astb) full address mode data address address port rd, wr, wait, (astb) cautions 1. when the external wait function is not used, the wait pin can be used as a port in all modes. 2. in this mode, the address strobe signal is not required to be used though it is output from the astb/p67 pin. the output timings are shown in figures 23-9 through 23-12. 529 chapter 23 external device expansion function memory maps when using the external device expansion function are as follows. figure 23-1. memory map when using external device expansion function (1/2) (a) memory map of m pd78076, 78076y, and of m pd78p078, 78p078y when internal prom capacity is 48 kbytes ffffh sfr internal high-speed ram ff00h feffh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f400h f3ffh d000h cfffh c100h c0ffh c000h bfffh 0000h reserved buffer ram reserved internal expansion ram full-address mode (when mm2 to mm0 = 111) or 16-kbyte expansion mode (when mm2 to mm0 = 101) 4-kbyte expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode 530 chapter 23 external device expansion function figure 23-1. memory map when using external device expansion function (2/2) (b) memory map of m pd78078, 78078y, 78p078, (c) memory map of m pd78078, 78078y and of 78p078y when internal rom capacity (prom) m pd78p078, 78p078y when internal prom is 56 kbytes capacity is 60 kbytes caution when the internal rom (prom) size is 60 kbytes, the area from f000h to f3ffh cannot be used. f000h to f3ffh can be used as external memory by setting the internal rom size to less than 56 kbytes by the internal memory size switching register (ims). sfr internal high-speed ram ff00h feffh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f400h f3ffh f000h efffh e100h e0ffh e000h dfffh 0000h reserved buffer ram reserved internal expansion ram full-address mode (when mm2 to mm0 = 111) or 16-kbyte expansion mode (when mm2 to mm0 = 101) 4-kbyte expansion mode (when mm2 to mm0 = 100) 256-byte expansion mode (when mm2 to mm0 = 011) single-chip mode ffffh sfr internal high-speed ram ff00h feffh fb00h faffh fae0h fadfh fac0h fabfh f800h f7ffh f400h f3ffh f000h efffh 0000h reserved buffer ram reserved internal expansion ram single-chip mode reserved ffffh 531 chapter 23 external device expansion function 23.2 external device expansion function control register the external device expansion function is controlled by the memory expansion mode register (mm) and internal memory size switching register (ims). (1) memory expansion mode register (mm) mm sets the wait count and external expansion area, and also sets the input/output of port 4. mm is set with 1- or 8-bit memory manipulation instruction. reset input sets this register to 10h. figure 23-2. memory expansion mode register format notes 1. this can be used only in the separate bus mode. in the multiplexed bus mode, these pins enter the port mode. 2. the full address mode allows external expansion to the entire 64-kbyte address space except for the internal rom, ram, and sfr areas and the reserved area. remark p60 to p63 enter the port mode without regard to the mode (single-chip mode or memory expansion mode). 7 0 symbol mm 6 0 5 pw1 4 pw0 3 0 2 mm2 1 mm1 0 mm0 address fff8h 10h after reset r/w r/w mm2 mm1 mm0 single-chip/ memory expansion mode selection p40 to p47, p50 to p57, p64 to p67, p80 to p87 pin state p40 to p47 p80 to p87 p50 to p53 p54, p55 p56, p57 p64 to p67 000 001 011 100 101 111 single-chip mode 256-byte mode 4-kbyte mode 16-kbyte mode full address mode note 2 memory expansion mode port mode input output port mode port mode port mode port mode ad0 to ad7 a0 to a7 note 1 a8 to a11 a12, a13 a14, a15 p64 = rd p65 = wr p66 = wait p67 = astb other than above setting prohibited pw1 pw0 00 01 10 11 wait control no wait wait (one wait state insertion) setting prohibited wait control by external wait pin 532 chapter 23 external device expansion function 1 1 48 kbytes 56 kbytes note 2 1 1 0 1 0 0 7 ram2 symbol ims 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 address fff0h note 1 after reset r/w r/w internal rom size selection rom3 60 kbytes 1 rom2 1 rom1 1 rom0 0 setting prohibited other than above internal high-speed ram size selection ram2 ram1 ram0 1024 bytes 110 setting prohibited other than above (2) internal memory size switching register (ims) the m pd78p078, 78p078y can specify the internal memory size by internal memory size switching register (ims). ims is set with an 8-bit memory manipulation instruction. reset input sets this register to the value indicated in table 23-5. figure 23-3. internal memory size switching register format notes 1. the values after reset depend on the product. (see table 23-5) table 23-5. values when the internal memory size switching register is reset type number reset value m pd78076, 78076y cch m pd78078, 78078y cfh m pd78p078, 78p078y 2. when using the external device expansion function in the m pd78078, 78078y, 78p078, and 78p078y set the internal rom size to 56 kbytes. caution when using the mask rom products, do not set the values other than cch and cfh to the ims except for the cases where the external device extension function is used in m pd78078 and 78078y. remark ims should be set according to the internal rom capacity. 533 chapter 23 external device expansion function (3) external bus type select register (ebts) this register sets the operation mode of the external device expansion function. when the multiplexed bus mode is selected, the p80/a0 through p87/a7 pins can be used as an i/o port. it is set by an 8-bit memory manipulation instruction. reset signal input sets ebts to 00h. figure 23-4. external bus type select register format 7 0 symbol ebts 6 0 5 0 4 0 3 0 2 0 1 0 0 ebts0 address ff3fh 00h after reset r/w r/w 0 1 sets operation mode of external device expansion function multiplexed bus mode separate bus mode ebts0 534 chapter 23 external device expansion function 23.3 external device expansion function timing 23.3.1 timings in multiplexed bus mode timing control signal output pins in the multiplexed bus mode are as follows. (1) rd pin (alternate function: p64) read strobe signal output pin. the read strobe signal is output in data accesses and instruction fetches from external memory. during internal memory access, the read strobe signal is not output (maintains high level). (2) wr pin (alternate function: p65) write strobe signal output pin. the write strobe signal is output in data access to external memory. during internal memory access, the write strobe signal is not output (maintains high level). (3) wait pin (alternate function: p66) external wait signal input pin. when the external wait is not used, the wait pin can be used as an input/ output port. during internal memory access, the external wait signal is ignored. (4) astb pin (alternate function: p67) address strobe signal output pin. timing signal is output without regard to the data accesses and instruction fetches from external memory. the astb signal is also output when the internal memory is accessed. (5) ad0 to ad7, a8 to a15 pins (alternate function : p40 to p47, p80 to p87, p50 to p57) address/data signal output pin. valid signal is output or input during data accesses and instruction fetches from external memory. these signals change when the internal memory is accessed (output values are undefined). timing charts are shown in figure 23-5 to 23-8. 535 chapter 23 external device expansion function figure 23-5. instruction fetch from external memory in multiplexed bus mode (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting astb rd ad0 to ad7 a8 to a15 lower address operation code higher address astb rd ad0 to ad7 a8 to a15 lower address operation code higher address internal wait signal (1-clock wait) astb rd lower address operation code ad0 to ad7 a8 to a15 higher address wait 536 chapter 23 external device expansion function figure 23-6. external memory read timing in multiplexed bus mode (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting higher address astb rd ad0 to ad7 a8 to a15 lower address read data astb rd ad0 to ad7 a8 to a15 lower address read data higher address internal wait signal (1-clock wait) astb rd lower address read data ad0 to ad7 a8 to a15 higher address wait 537 chapter 23 external device expansion function figure 23-7. external memory write timing in multiplexed bus mode (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting astb wr ad0 to ad7 a8 to a15 lower address write data hi-z higher address astb wr ad0 to ad7 a8 to a15 lower address write data higher address internal wait signal (1-clock wait) hi-z astb wr higher address ad0 to ad7 a8 to a15 wait hi-z lower address write data 538 chapter 23 external device expansion function figure 23-8. external memory read modify write timing in multiplexed bus mode (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting astb rd wr ad0 to ad7 a8 to a15 lower address write data higher address hi-z read data lower address higher address internal wait signal (1-clock wait) hi-z astb rd wr ad0 to ad7 a8 to a15 write data read data astb rd wr higher address ad0 to ad7 a8 to a15 wait hi-z lower address write data read data 539 chapter 23 external device expansion function 23.3.2 timings in separate bus mode timing control signal output pins in the separate bus mode are as follows. (1) rd pin (alternate function: p64) read strobe signal output pin. the read strobe signal is output in data accesses and instruction fetches from external memory. during internal memory access, the read strobe signal is not output (maintains high level). (2) wr pin (alternate function: p65) write strobe signal output pin. the write strobe signal is output in data access to external memory. during internal memory access, the write strobe signal is not output (maintains high level). (3) wait pin (alternate function: p66) external wait signal input pin. when the external wait is not used, the wait pin can be used as an input/ output port. during internal memory access, the external wait signal is ignored. (4) ad0 to ad7, a0 to a7, a8 to a15 pins (alternate function : p40 to p47, p80 to p87, p50 to p57) address/data signal output pin. valid signal is output or input during data accesses and instruction fetches from external memory. these signals change when the internal memory is accessed (output values are undefined). timing charts are shown in figure 23-9 to 23-12. caution in the separate bus mode, use of the address strobe signal is not required though it is output from the astb/p67 pin. the output timings of the signals are shown in figure 23-9 to 23-12. 540 chapter 23 external device expansion function figure 23-9. instruction fetch from external memory in separate bus mode (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting note in the separate bus mode, use of the address strobe signal is not required though it is output from the astb/p67 pin. astb note rd ad0 to ad7 a0 to a7 a8 to a15 lower address operation code higher address lower address astb note rd ad0 to ad7 a0 to a7 a8 to a15 lower address operation code higher address lower address internal wait signal (1-clock wait) astb note rd lower address operation code higher address lower address ad0 to ad7 a0 to a7 a8 to a15 wait 541 chapter 23 external device expansion function figure 23-10. external memory read timing in separate bus mode (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting note in the separate bus mode, use of the address strobe signal is not required though it is output from the astb/p67 pin. astb note rd ad0 to ad7 a0 to a7 a8 to a15 lower address read data higher address lower address astb note rd ad0 to ad7 a0 to a7 a8 to a15 lower address read data higher address lower address internal wait signal (1-clock wait) astb note rd lower address read data higher address lower address ad0 to ad7 a0 to a7 a8 to a15 wait 542 chapter 23 external device expansion function figure 23-11. external memory write timing in separate bus mode (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting note in the separate bus mode, use of the address strobe signal is not required though it is output from the astb/p67 pin. astb note wr ad0 to ad7 a0 to a7 a8 to a15 lower address write data higher address lower address hi-z astb note wr ad0 to ad7 a0 to a7 a8 to a15 lower address write data higher address lower address internal wait signal (1-clock wait) hi-z astb note wr higher address lower address ad0 to ad7 a0 to a7 a8 to a15 wait hi-z lower address write data 543 chapter 23 external device expansion function figure 23-12. external memory read modify write timing in separate bus mode (a) no wait (pw1, pw0 = 0, 0) setting (b) wait (pw1, pw0 = 0, 1) setting (c) external wait (pw1, pw0 = 1, 1) setting note in the separate bus mode, use of the address strobe signal is not required though it is output from the astb/p67 pin. astb note rd wr ad0 to ad7 a0 to a7 a8 to a15 lower address write data higher address lower address hi-z read data lower address higher address lower address internal wait signal (1-clock wait) hi-z astb note rd wr ad0 to ad7 a0 to a7 a8 to a15 write data read data astb note rd wr higher address lower address ad0 to ad7 a0 to a7 a8 to a15 wait hi-z lower address write data read data 544 [memo] 545 chapter 24 standby function 24.1 standby function and configuration 24.1.1 standby function the standby function is designed to decrease power consumption of the system. the following two modes are available. (1) halt mode halt instruction execution sets the halt mode. the halt mode is intended to stop the cpu operation clock. system clock oscillator continues oscillation. in this mode, current consumption cannot be decreased as in the stop mode. the halt mode is valid to restart immediately upon interrupt request and to carry out intermittent operations such as watch applications. (2) stop mode stop instruction execution sets the stop mode. in the stop mode, the main system clock oscillator stops and the whole system stops. cpu current consumption can be considerably decreased. data memory low-voltage hold (down to v dd = 1.8 v) is possible. thus, the stop mode is effective to hold data memory contents with ultra-low current consumption. because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out. however, because a wait time is necessary to secure an oscillation stabilization time after the stop mode is cleared, select the halt mode if it is necessary to start processing immediately upon interrupt request. in any mode, all the contents of the register, flag, and data memory just before standby mode setting are held. the input/output port output latch and output buffer statuses are also held. cautions 1. the stop mode can be used only when the system operates with the main system clock (subsystem clock oscillation cannot be stopped). the halt mode can be used with either the main system clock or the subsystem clock. 2. when proceeding to the stop mode, be sure to stop the peripheral hardware operation and execute the stop instruction. 3. the following sequence is recommended for power consumption reduction of the a/d converter when the standby function is used: first clear bit 7 (cs) to 0 to stop the a/d conversion operation, and then execute the halt or stop instruction. 546 chapter 24 standby function 24.1.2 standby function control register a wait time after the stop mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (osts). osts is set with an 8-bit memory manipulation instruction. reset input sets osts to 04h. however, it takes 2 17 /f x , not 2 18 /f x , until the stop mode is cleared by reset input. figure 24-1. oscillation stabilization time select register format caution the wait time after stop mode clear does not include the time from stop mode clear to clock oscillation start (see a in the illustration below), whether the stop mode is cleared by reset input or by interrupt request generation. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency 3. mcs : bit 0 of oscillation mode select register (osms) 4. figures in parentheses apply to operation with f x = 5.0 mhz. stop mode clear x1 pin voltage waveform v ss a address fffah 04h after reset r/w r/w 0 0 0 0 1 selection of oscillation stabilization time wnen stop mode is released 2 12 /f xx 2 14 /f xx 2 15 /f xx 2 16 /f xx 2 17 /f xx osts2 7 0 symbol osts 6 0 5 0 4 0 3 0 2 osts2 1 osts1 0 osts0 0 0 1 1 0 other than above osts1 mcs = 1 mcs = 0 2 12 /f x (819 s) 2 14 /f x (3.28 ms) 2 15 /f x (6.55 ms) 2 16 /f x (13.1 ms) 2 17 /f x (26.2 ms) 2 13 /f x (1.64 ms) 2 15 /f x (6.55 ms) 2 16 /f x (13.1 ms) 2 17 /f x (26.2 ms) 2 18 /f x (52.4 ms) 0 1 0 1 0 osts0 setting prohibited 547 chapter 24 standby function 24.2 standby function operations 24.2.1 halt mode (1) halt mode set and operating status the halt mode is set by executing the halt instruction. it can be set with the main system clock or the subsystem clock. the operating status in the halt mode is described below. table 24-1. halt mode operating status halt mode setting halt execution during halt execution during main system clock operation subsystem clock operation w/ subsystem w/o. subsystem main system main system item clock note 1 clock note 2 clock oscillates clock stops clock generator both main system and subsystem clocks can be oscillated. clock supply to the cpu stops. cpu operation stops. port (output latch) status before halt mode setting is held. 16-bit timer/event counter operable. operable when watch timer output is used as count clock (with f xt selected as count clock of watch timer). 8-bit timer/event counter 1 and 2 operable. operable when ti1 or ti2 is selected as count clock. 8-bit timer/event counter 5 and 6 operable. operable when ti5 or ti6 is selected as count clock. watch timer operable when operable. operable when f xt is selected f xx /2 7 is selected as count clock. as count clock. watchdog timer operable. operation stops. a/d converter operable. operation stops. d/a converter operable. real-time output port operable. serial interface when a function other than operable operable at external sck. auto transmit/receive is used when auto transmit/receive operation stops. function is used external interrupt intp0 operable when a clock (f xx /2 5 , f xx /2 6 , f xx /2 7 ) for the operation stops. peripheral hardware is selected as sampling clock. intp1 to intp6 operable. bus lines in external expansion ad0 to ad7 enters high impedance state. a0 to a15 holds the state before halt mode is set. astb outputs low level. wr, rd outputs high level. wait enters high impedance state. notes 1. including case when external clock is supplied. 2. including case when external clock is not supplied. 548 chapter 24 standby function (2) halt mode release the halt mode can be released with the following four types of sources. (a) release by unmasked interrupt request an unmasked interrupt request is generated to release the halt mode. if interrupt request acknowledge is enabled, vectored interrupt service is carried out. if disabled, the next address instruction is executed. figure 24-2. halt mode released by interrupt request generation remarks 1. the broken line indicates the case when the interrupt request which has released the standby status is acknowledged. 2. wait time will be as follows: ? when vectored interrupt service is carried out: 8 to 9 clocks ? when vectored interrupt service is not carried out: 2 to 3 clocks (b) release by non-maskable interrupt request the halt mode is released and vectored interrupt service is carried out if non-maskable interrupt request is generated whether interrupt request acknowledge is enabled or disabled. (c) release by unmasked test input the halt mode is released by inputting an unmasked test signal and the next address instruction of the halt instruction is executed. halt instruction interrupt request wait standby release signal operating mode clock halt mode wait oscillation operating mode 549 chapter 24 standby function halt instruction reset signal operating mode clock reset period halt mode oscillation oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 26.2 ms) (d) release by reset input as is the case with normal reset operation, a program is executed after branch to the reset vector address. figure 24-3. halt mode released by reset input remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 5.0 mhz. table 24-2. operation after halt mode release release source mkxx prxx ie isp operation maskable interrupt 0 0 0 x next address instruction execution request 0 0 1 x interrupt service execution 0 1 0 1 next address instruction execution 01x0 0 1 1 1 interrupt service execution 1 x x x halt mode hold non-maskable interrupt C C x x interrupt service execution request test input 0 C x x next address instruction execution 1 C x x halt mode hold reset input C C x x reset processing x: dont care 550 chapter 24 standby function 24.2.2 stop mode (1) stop mode set and operating status the stop mode is set by executing the stop instruction. it can be set only with the main system clock. cautions 1. when the stop mode is set, the x2 pin is internally connected to v dd via a pull-up resistor to minimize leakage current at the crystal oscillator. thus, do not use the stop mode in a system where an external clock is used for the main system clock. 2. because the interrupt request signal is used to release the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. thus, the stop mode is reset to the halt mode immediately after execution of the stop instruction. after the wait set using the oscillation stabilization time select register (osts), the operating mode is set. the operating status in the stop mode is described below. table 24-3. stop mode operating status stop mode setting with subsystem clock without subsystem clock item clock generator only main system clock stops oscillation. cpu operation stops. port (output latch) status before stop mode setting is held. 16-bit timer/event counter operable when watch timer output is used operation stops. as count clock (f xt is selected as count clock for watch timer). 8-bit timer/event counters 1 and 2 operable when ti1 or ti2 is selected for the count clock. 8-bit timer/event counters 5 and 6 operable when ti5 or ti6 is selected for the count clock. watch timer operable when f xt is selected for the count clock. operation stops. watchdog timer operation stops. a/d converter operation stops. d/a converter operable. real-time output port operable when external trigger is used, or ti1 or ti2 is selected for the 8-bit timer/ event counter 1 or 2 count clock. serial interface when a function other than auto operable only when externally supplied clock is specified as the serial clock. transmit/receive & uart is used when auto transmit/receive operation stops. function or uart is used external interrupt intp0 operation disabled. intp1 to intp6 operable. bus lines in external expansion ad0 to ad7 enters high-impedance state. a0 to a15 holds the state before stop mode is set. astb outputs low level. wr, rd outputs high level. wait enters high-impedance state. 551 chapter 24 standby function stop instruction wait (time set by osts) oscillation stabilization wait status operating mode oscillation operationg mode stop mode oscillation stop oscillation standby release signal clock interrupt request (2) stop mode release the stop mode can be released with the following three types of sources. (a) release by unmasked interrupt request an unmasked interrupt request is used to release the stop mode. if interrupt request acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. if interrupt request acknowledge is disabled, the next address instruction is executed. figure 24-4. stop mode released by interrupt request generation remark the broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged. (b) release by unmasked test input the stop mode is released by inputting an unmasked test signal. after the lapse of oscillation stabilization time, the instruction at the next address of the stop instruction is executed. 552 chapter 24 standby function reset signal operating mode clock reset period stop mode oscillation stop oscillation stabilization wait status operating mode oscillation wait (2 17 /f x : 26.2 ms) stop instruction oscillation (c) release by reset input the stop mode is released and after the lapse of oscillation stabilization time, reset operation is carried out. figure 24-5. stop mode released by reset input remarks 1. f x : main system clock oscillation frequency 2. figures in parentheses apply to operation with f x = 5.0 mhz. table 24-4. operation after stop mode release release source mkxx prxx ie isp operation maskable interrupt request 0 0 0 x next address instruction execution 0 0 1 x interrupt service execution 0 1 0 1 next address instruction execution 01 x 0 0 1 1 1 interrupt service execution 1 x x x stop mode hold test input 0 C x x next address instruction execution 1 C x x stop mode hold reset input C C x x reset processing x: dont care 553 chapter 25 reset function 25.1 reset function the following two operations are available to generate the reset signal. (1) external reset input with reset pin (2) internal reset by watchdog timer overrun time detection external reset and internal reset have no functional differences. in both cases, program execution starts at the address at 0000h and 0001h by reset input. when a low level is input to the reset pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in table 25-1. each pin has high impedance during reset input or during oscillation stabilization time just after reset clear. when a high level is input to the reset input, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ). the reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2 17 /f x ) (see figures 25-2 to 25-4 ). cautions 1. for an external reset, input a low level for 10 m s or more to the reset pin. 2. during reset input, main system clock oscillation remains stopped but subsystem clock oscillation continues. 3. when the stop mode is released by reset, the stop mode contents are held during reset input. however, the port pin becomes high-impedance. figure 25-1. block diagram of reset function reset count clock reset control circuit watchdog timer stop over- flow reset signal interrupt function 554 chapter 25 reset function figure 25-2. timing of reset by reset input figure 25-3. timing of reset due to watchdog timer overflow figure 25-4. timing of reset by reset input in stop mode reset internal reset signal port pin delay delay hi-z x1 normal operation reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) x1 normal operation watchdog timer overflow internal reset signal port pin reset period (oscillation stop) oscillation stabilization time wait normal operation (reset processing) hi-z reset internal reset signal port pin delay delay hi-z x1 normal operation normal operation (reset processing) stop instruction execution reset period (oscillation stop) oscillation stabilization time wait stop status (oscillation stop) 555 chapter 25 reset function table 25-1. hardware status after reset (1/3) hardware status after reset program counter (pc) note 1 the contents of reset vector tables (0000h and 0001h) are set. stack pointer (sp) undefined program status word (psw) 02h data memory undefined note 2 general register undefined note 2 ports 0 to 3, port 7, 9, 10, 12, 13 00h (p0 to p3, p7, p9, p10, p12, p13) port 4 to port 6, port 8 (p4 to p6, p8) undefined port mode register (pm0 to pm3, pm5 to pm10, pm12, pm13) ffh pull-up resistor option register (puoh, puol) 00h processor clock control register (pcc) 04h oscillation mode selection register (osms) 00h memory size switching register (ims) note3 internal expansion ram size switching register (ixs) 0ah external bus type selection register (ebts) 00h memory expansion mode register (mm) 10h oscillation stabilization time select register (osts) 04h timer register (tm0) 00h capture/compare register (cr00, cr01) undefined clock selection register (tcl0) 00h mode control register (tmc0) 00h capture/compare control register 0 (crc0) 04h output control register (toc0) 00h timer register (tm1, tm2) 00h compare registers (cr10, cr20) undefined clock select register (tcl1) 00h mode control registers (tmc1) 00h output control register (toc1) 00h ram port (output latch) 16-bit timer/event counter 8-bit timer/event counter 1 and 2 notes 1. during reset input or oscillation stabilization time wait, only the pc contents among the hardware statuses become undefined. all other hardware statuses remains unchanged after reset. 2. in the standby mode, the status before the reset is held even after the reset. 3. the values after reset depend on the product. m pd78076, 78076y : cch m pd78078, 78078y : cfh m pd78p078, 78p078y : cfh 556 chapter 25 reset function table 25-1. hardware status after reset (2/3) hardware status after reset 8-bit timer/event counters timer register (tm5, tm6) 00h 5 and 6 compare register (cr50, cr60) 00h clock select register (tcl5, tcl6) 00h mode control register (tmc5, tmc6) 00h watch timer mode control register (tmc2) 00h watchdog timer clock select register (tcl2) 00h mode register (wdtm) 00h serial interface clock select register (tcl3) 88h shift registers (sio0, sio1) undefined mode registers (csim0, csim1, csim2) 00h serial bus interface control register (sbic) 00h slave address register (sva) undefined automatic data transmit/receive control 00h register (adtc) automatic data transmit/receive address 00h pointer (adtp) automatic data transmit/receive interval 00h specify register (adti) asynchronous serial interface mode 00h register (asim) asynchronous serial interface status 00h register (asis) baud rate generator control register (brgc) 00h transmit shift register (txs) ffh receive buffer register (rxb) interrupt timing specify register (sint) 00h a/d converter mode register (adm) 01h conversion result register (adcr) undefined input select register (adis) 00h d/a converter mode register (dam) 00h conversion value setting register 00h (dacs0, dacs1) real-time output port mode register (rtpm) 00h control register (rtpc) 00h buffer register (rtbl, rtbh) 00h rom correction correction address register (corad0, corad1) 00h correction control register (corcn) 00h 557 chapter 25 reset function table 25-1. hardware status after reset (3/3) hardware status after reset interrupt request flag register (if0l, if0h, if1l) 00h mask flag register (mk0l, mk0h, mk1l) ffh priority specify flag register ffh (pr0l, pr0h, pr1l) external interrupt mode register 00h (intm0, intm1) key return mode register (krm) 02h sampling clock select register (scs) 00h 558 [memo] 559 chapter 26 rom correction 26.1 rom correction functions the m pd78078, 78078y subseries can replace part of a program in the mask rom with a program in the internal expansion ram. instruction bugs found in the mask rom can be avoided, and program flow can be changed by using the rom correction. the rom correction can correct two places (max.) of the internal rom (program). caution the rom correction cannot be emulated by the in-circuit emulator (ie-78000-r, ie-78000-r-a ie-78001-r-a, ie-78k0-ns). 26.2 rom correction configuration the rom correction is executed by the following hardware. table 26-1. rom correction configuration item configuration register correction address registers 0 and 1 (corad0, corad1) control register correction control register (corcn) figure 26-1 shows a block diagram of the rom correction. figure 26-1. block diagram of rom correction remark n = 0, 1 match corenn corstn program counter (pc) comparator correction address register (coradn) internal bus correction control register correction branch request signal (br !7fdh) 560 chapter 26 rom correction (1) correction address registers 0 and 1 (corad0, corad1) these registers set the start address (correction address) of the instruction(s) to be corrected in the mask rom. the rom correction corrects two places (max.) of the program. addresses are set to two registers, corad0 and corad1. if only one place needs to be corrected, set the address to either of the registers. corad0 and corad1 are set with a 16-bit memory manipulation instruction. reset input sets corad0 and corad1 to 0000h. figure 26-2. correction address registers 0 and 1 format cautions 1. set the corad0 and corad1 when bit 1 (coren0) and bit 3 (coren1) of the correction control register (corcn : see figure 26-3) are 0. 2. only addresses where operation codes are stored can be set in corad0 and corad1. 3. do not set the following addresses to corad0 and corad1. ? address value in table area of table reference instruction (callt instruction) : 0040h to 007fh ? address value in vector table area : 0000h to 003fh (2) comparator the comparator always compares the correction address value set in correction address registers 0 and 1 (corad0, corad1) with the fetch address value. when bit 1 (coren0) or bit 3 (coren1) of the correction control register (corcn) is 1 and the correction address matches the fetch address value, the correction branch request signal (br !f7fdh) is generated from the rom correction circuit. ff3ah/ff3bh 0000h symbol 15 corad0 0 address ff38h/ff39h after reset 0000h r/w r/w corad1 r/w 561 chapter 26 rom correction 7 0 6 0 5 0 4 0 coren1 corst1 coren0 corst0 symbol corcn address ff8ah after reset coren0 0 1 corst0 0 1 coren1 0 1 corst1 0 1 r/w r/w note 00h correction address register 0 and fetch address match detection not detected detected correction address register 0 and fetch address match detection control disabled enabled correction address register 1 and fetch address match detection not detected detected correction address register 1 and fetch address match detection control disabled enabled r r/w r r/w <3> <2> <1> <0> 26.3 rom correction control registers the rom correction is controlled with the correction control register (corcn). (1) correction control register (corcn) this register controls whether or not the correction branch request signal is generated when the fetch address matches the correction address set in correction address registers 0 and 1. the correction control register consists of correction enable flags (coren0, coren1) and correction status flags (corst0, corst1). the correction enable flags enable or disable the comparator match detection signal, and correction status flags show the values are matched. corcn is set with a 1-bit or 8-bit memory manipulation instruction. reset input sets corcn to 00h. figure 26-3. correction control register format note bits 0 and 2 are read-only bits. 562 chapter 26 rom correction v dd v dd v dd pd78078, 78078y subseries eeprom sck0 sb1 p32 scl sda cs ce ra78k/0 eeprom source program 00 10 0d 02 9b 02 10 00h 01h 02h ffh cseg at 1000h add a, #2 br !1002h 26.4 rom correction application (1) store the correction address and instruction after correction (patch program) to nonvolatile memory (such as eeprom tm ) outside the microcontroller. when two places should be corrected, store the branch destination judgment program as well. the branch destination judgment program checks which one of the addresses set to corad0 or corad1 generates the correction branch. figure 26-4. storing example to eeprom (when one place is corrected) figure 26-5. connecting example with eeprom (using 2-wire serial i/o mode) 563 chapter 26 rom correction (2) assemble in advance the initialization routine as shown in figure 26-6 to correct the program. figure 26-6. initialization routine note whether the rom correction is used or not should be judged by the port input level. for example, when the p20 input level is high, the rom correction is used, otherwise, it is not used. (3) after reset, store the contents that have been previously stored in the external nonvolatile memory with initialization routine for rom correction of the user to internal expansion ram (see figure 26-6 ). set the start address of the instruction to be corrected to corad0 and corad1, and set bits 1 and 3 (coren0, coren1) of the correction control register (corcn) to 1. (4) set the entire-space branch instruction (br !addr16) to the specified address (f7fdh) of the internal expansion ram with the main program. (5) after the main program is started, the fetch address value and the values set in corad0 and corad1 are always compared by the comparator in the rom correction circuit. when these values match, the correction branch request signal is generated. simultaneously the corresponding correction status flag (corst0 or corst1) is set to 1. (6) branch to the address f7fdh by the correction branch request signal. (7) branch to the internal expansion ram address set with the main program by the entire-space branch instruction of the address f7fdh. (8) when one place is corrected, the correction program is executed. when two places are corrected, the correction status flag is checked with the branch destination judgment program, and branches to the correction program. no yes initialization load the contents of external nonvolatile memory into internal expansion ram correction address register setting rom correction enabled is rom correction used ? note rom correction main program 564 chapter 26 rom correction figure 26-7. rom correction operation no yes start of internal rom program does fetch address match with correction address? set correction status flag correction branch (branch to address f7fdh) execution of correction program rom correction 565 chapter 26 rom correction 26.5 rom correction example the example of rom correction when the instruction at address 1000h add a, #1 is changed to add a, #2 is as follows. figure 26-8. rom correction example (1) branches to address f7fdh when the preset value 1000h in the correction address register matches the fetch address value after the main program is started. (2) branches to any address (address f702h in this example) by setting the entire-space branch instruction (br !addr16) to address f7fdh with the main program. (3) returns to the internal rom program after executing the substitute instruction add a, #2. add a, #2 br !1002h br !f702h add a, #1 mov b, a 0000h 0080h program start 1000h 1002h internal rom internal expansion ram 0000h f702h f7fdh f7ffh (1) (2) (3) 566 chapter 26 rom correction 26.6 program execution flow figures 26-9 and 26-10 show the program transition diagrams when the rom correction is used. figure 26-9. program transition diagram (when one place is corrected) (1) branches to address f7fdh when fetch address matches correction address (2) branches to correction program (3) returns to internal rom program remark area filled with diagonal lines : internal expansion ram jump : correction program start address correction place internal rom internal rom jump ffffh f7ffh f7fdh xxxxh 0000h (1) (2) (3) br !jump correction program 567 chapter 26 rom correction figure 26-10. program transition diagram (when two places are corrected) (1) branches to address f7fdh when fetch address matches correction address (2) branches to branch destination judgment program (3) branches to correction program 1 by branch destination judgment program (btclr !corst0, $xxxxh) (4) returns to internal rom program (5) branches to address f7fdh when fetch address matches correction address (6) branches to branch destination judgment program (7) branches to correction program 2 by branch destination judgment program (btclr !corst1, $yyyyh) (8) returns to internal rom program remark area filled with diagonal lines : internal expansion ram jump : correction program start address internal rom correction place 1 internal rom jump internal rom (1) (2) (3) (4) (5) (6) (7) (8) ffffh f7ffh f7fdh yyyyh xxxxh 0000h br !jump destination judge program correction program 2 correction program 1 correction place 2 568 chapter 26 rom correction 26.7 cautions on rom correction (1) address values set in correction address registers 0 and 1 (corad0, corad1) must be addresses where instruction codes are stored. (2) correction address registers 0 and 1 (corad0, corad1) should be set when the correction enable flag (coren0, coren1) is 0 (when the correction branch is in disabled state). if address is set to corad0 or corad1 when coren0 or coren1 is 1 (when the correction branch is in enabled state), the correction branch may start with the different address from the set address value. (3) do not set the address value of instruction immediately after the instruction that sets the correction enable flag (coren0, coren1) to 1, to correction address register 0 or 1 (corad0, corad1) ; the correction branch may not start. (4) do not set the address value in table area of table reference instruction (callt instruction) (0040h to 007fh), and the address value in vector table area (0000h to 003fh) to correction address registers 0 and 1 (corad0, corad1). (5) do not set two addresses immediately after the instructions shown below to correction address registers 0 and 1 (corad0, corad1). (that is, when the mapped terminal address of these instructions is n, do not set the address values of n+1 and n+2.) ? ret ? reti ? retb ? br $addr16 ? stop ? halt 569 chapter 27 m pd78p078, 78p078y the m pd78p078 and 78p078y (prom versions) replace the internal mask rom of the mask rom versions ( m pd78074, 78075, 78076, 78078, and m pd78074y, 78075y, 78076y, 78078y) with one-time programmable rom or eprom, which enable program writing, erasure, and rewriting. table 27-1 lists differences between the prom versions and mask rom versions. table 27-1. differences between prom and mask rom versions item m pd78p078, 78p078y mask rom versions internal rom format one-time prom/eprom mask rom internal rom capacity 60 kbytes m pd78076, 78076y: 48 kbytes m pd78078, 78078y: 60 kbytes changing internal rom and internal high-speed ram yes note 1 no capacities by the internal memory size switching register (ims) changing internal expansion ram capacity by the yes note 2 no internal expansion ram size switching register (ixs) ic pin none available v pp pin available none p60 to p63 pins pull-up resistor internal mask option none available electrical specifications refer to the data sheet of individual product notes 1. internal prom capacity becomes 60 kbytes, and internal high-speed ram capacity becomes 1024 bytes by reset input. 2. internal expansion ram capacity becomes 1024 bytes by reset input. caution there are differences in noise immunity and noise radiation between the prom and mask rom versions. when pre-producing an application set with the prom version and then mass- producing it with the mask rom version, be sure to conduct sufficient evaluations for the consumer samples (not engineering samples) of the mask rom version. 570 chapter 27 m pd78p078, 78p078y 7 ram2 symbol ims 6 ram1 5 ram0 4 0 3 rom3 2 rom2 1 rom1 0 rom0 address fff0h cfh after reset r/w r/w 1 1 internal rom capacity selection 48 kbytes 56 kbytes note rom3 60 kbytes 1 1 1 rom2 1 0 1 rom1 1 0 0 rom0 1 setting prohibited other than above internal high-speed ram capacity selection ram2 ram1 ram0 1024 bytes 110 setting prohibited other than above 27.1 internal memory size switching register the m pd78p078 and 78p078y allow users to define its internal memory sizes using the internal memory size switching register (ims), so that the same memory mapping as that of a mask rom version with a different-size internal rom is possible. ims is set with an 8-bit memory manipulation instruction. reset input sets ims to cfh. figure 27-1. internal memory size switching register format note when using the external device extension function on the following devices, the internal rom capacity must be 56 kbytes or less: m pd78078, 78078y, 78p078, 78p078y. caution when using the mask rom versions, do not set the values other than cch and cfh to the ims except for the case where the external device extension function is used on the m pd78078 and 78078y. the ims settings to give the same memory map as mask rom versions are shown in table 27-2. table 27-2. examples of internal memory size switching register settings relevant mask rom version ims setting m pd78076, 78076y cch m pd78078, 78078y cfh 571 chapter 27 m pd78p078, 78p078y 7 0 symbol ixs 6 0 5 0 4 0 3 ixram3 2 ixram2 1 ixram1 0 ixram0 address fff4h 0ah after reset internal extension ram capacity selection ixram3 ixram2 ixram1 1024 bytes 101 setting prohibited other than above ixram0 0 r/w w 0 bytes 1100 27.2 internal extension ram size switching register the m pd78p078 and 78p078y allow users to define its internal extension ram size by using the internal extension ram size switching register (ixs), so that the same memory mapping as that of a mask rom version with a different internal extension ram is possible. the ixs is set by an 8-bit memory manipulation instruction. reset signal input sets ixs to 0ah. caution when the m pd78076, 78078, 78076y, or 78078y is used, be sure to set the value specified in table 27-3 to ixs. other settings are prohibited. figure 27-2. internal extension ram size switching register format the value which is set in the ixs that has the identical memory map to the mask rom versions is given in table 27-3. table 27-3. examples of internal extension ram size switching register settings relevant mask rom version ixs setting m pd78076, 78076y 0ah m pd78078, 78078y 572 chapter 27 m pd78p078, 78p078y 27.3 prom programming the m pd78p078 and 78p078y each incorporate a 60-kbyte prom as program memory. to write a program into the prom make the device enter the prom programming mode by setting the levels of the v pp and reset pins as specified. for the connection of unused pins, refer to 1.5 (2) prom programming mode and 2.5 pin configuration (top vew) . caution write the program in the range of addresses 0000h to efffh (specify the last address as efffh). the program cannot be written by a prom programmer in which the write address cannot be specified. 27.3.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low-level signal is applied to the reset pin, the device is set to the prom programming mode. this is one of the operating modes shown in table 27-4 below according to the setting of the ce, oe, and pgm pins. the prom contents can be read by setting the read mode. table 27-4. prom programming operating modes pin operating mode page data latch h l h data input page write h h l high impedance byte write l h l data input program verify l l h data output lxhh xll read l l h data output output disabled +5 v +5 v l h x high impedance standby h x x high impedance x: l or h (1) read mode read mode is set by setting ce to l and oe to l. (2) output disable mode if oe is set to h, data output becomes high impedance and the output disable mode is set. therefore, if multiple m pd78p078s or 78p078ys are connected to the data bus, data can be read from any one device by controlling the oe pin. reset v pp v dd ce oe pgm d0 to d7 program inhibit high impedance +12.5 v +6.5 v 573 chapter 27 m pd78p078, 78p078y (3) standby mode setting ce to h sets the standby mode. in this mode, data output becomes high impedance irrespective of the status of oe. (4) page data latch mode setting ce to h, pgm to h, and oe to l at the start of the page write mode sets the page data latch mode. in this mode, 1-page 4-byte data is latched in the internal address/data latch circuit. (5) page write mode after a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active-low) to the pgm pin while ce = h and oe = h. after this, program verification can be performed by setting ce to l and oe to l. if programming is not performed by one program pulse, repeated write and verify operations are executed x times (x 10). (6) byte write mode a byte write is executed by applying a 0.1-ms program pulse (active-low) to the pgm pin while ce = l and oe = h. after this, program verification can be performed by setting oe to l. if programming is not performed by one program pulse, repeated write and verify operations are executed x times (x 10). (7) program verify mode setting ce to l, pgm to h, and oe to l sets the program verify mode. after writing is performed, this mode should be used to check whether the data was written correctly. (8) program inhibit mode the program inhibit mode is used when the oe pins, v pp pins and pins d0 to d7 of multiple m pd78p078s or 78p078ys are connected in parallel, and you wish to write to one of these devices. the page write mode or byte write mode described above is used to perform a write. at this time, the write is not performed on the device which has the pgm pin driven high. 574 chapter 27 m pd78p078, 78p078y start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 0.1 ms program pulse verify 4 bytes pass address = n? no pass v dd = 4.5 to 5.5 v, v pp = v dd all bytes verified? end of write address = address + 1 no yes x = 10 ? fail fail yes all pass defective product g = start address n = last address of program 27.3.2 prom write procedure figure 27-3. page program mode flowchart 575 chapter 27 m pd78p078, 78p078y page data latch page program program verify data input data output hi-z a2 to a16 a0, a1 d0 to d7 v pp v dd v pp v dd + 1.5 v dd v pp v ih ce pgm oe v il v ih v il v ih v il figure 27-4. page program mode timing 576 chapter 27 m pd78p078, 78p078y start address = g v dd = 6.5 v, v pp = 12.5 v x = 0 x = x + 1 0.1 ms program pulse verify address = n ? v dd = 4.5 to 5.5 v, v pp = v dd all bytes verified? end of write fail fail pass yes all pass no pass defective product no yes x = 10 ? address = address + 1 g = start address n = last address of program figure 27-5. byte program mode flowchart 577 chapter 27 m pd78p078, 78p078y program program verify a0 to a16 d0 to d7 data input hi-z data output v pp v dd v dd + 1.5 v dd v ih v il v ih v il v ih v il v pp v dd ce pgm oe figure 27-6. byte program mode timing cautions 1. apply v dd before applying v pp , and remove it after removing v pp . 2. v pp must not exceed +13.5 v including overshoot voltage. 3. disconnecting/inserting the device from/to the on-board socket while +12.5 v is being applied to v pp may have an adverse affect on reliability. 578 chapter 27 m pd78p078, 78p078y 27.3.3 prom reading procedure prom contents can be read onto the external data bus (d0 to d7) using the following procedure. (1) fix the reset pin low, and supply +5 v to the v pp pin. unused pins are handled as shown in, 1.5 (2) prom programming mode and 2.5 pin configuration (top view) . (2) supply +5 v to the v dd and v pp pins. (3) input address of data to be read to pins a0 through a16. (4) read mode. (5) output data to pins d0 through d7. the timing for steps (2) through (5) above is shown in figure 27-7. figure 27-7. prom read timing address input a0 to a16 ce (input) oe (input) d0 to d7 hi-z hi-z data output 579 chapter 27 m pd78p078, 78p078y 27.4 erasure procedure ( m pd78p078kl-t and 78p078ykl-t only) with the m pd78p078kl-t or 78p078ykl-t, it is possible to erase (all contents to ffh) the data contents written in the program memory, and rewrite the memory. the data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter. typically, data is erased by 254-nm ultraviolet light rays. the minimum lighting level to completely erase the written data is shown below. uv intensity x erasure time: 30 ws/cm 2 or more erasure time: 40 minutes (using a 12 mw/cm 2 ultraviolet lamp. a longer erasure time may be required in case of deterioration of the ultraviolet lamp or dirt on the package window). when erasing written data, remove any filter on the window and place the device within 2.5 cm of the lamp tube. 27.5 opaque film masking window ( m pd78p078kl-t and 78p078ykl-t only) to prevent unintentional erasure of the eprom contents by light and to prevent internal circuits from malfunction due to light coming in through the erasure window, mask the window with the attached opaque film after writing the eprom. 27.6 screening of one-time prom versions one-time prom versions cannot be fully tested by nec before shipment due to the structure of one-time prom. therefore, after users have written data to the prom, screening should be implemented: that is, store devices under the following conditions. then verify their contents after the device have returned to room temperature. storage temperature storage time 125 c 24 hours for users who do not wish to implement screening by themselves, nec provides such users with a charged service in which nec performs a series of processes from writing one-time proms and screening them to verifying their contents for users by request. the prom version devices which provide this service are called qtop tm microcontrollers. this service will soon be available for the m pd78p078y. for details, please consult an nec sales representative. 580 [memo] 581 chapter 28 instruction set this chapter describes each instruction set of the m pd78078 and 78078y subseries as list table. for details of its operation and operation code, refer to the separate document 78k/0 series user?s manual ? instructions (u12326e). 582 chapter 28 instruction set 28.1 legends used in operation list 28.1.1 operand identifiers and description methods operands are described in operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). when there are two or more description methods, select one of them. alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. each symbol has the following meaning. ? # : immediate data specification ? ! : absolute address specification ? $ : relative address specification ? [ ] : indirect address specification in the case of immediate data, describe an appropriate numeric value or a label. when using a label, be sure to describe the #, !, $, and [ ] symbols. for operand register identifiers, r and rp, either function names (x, a, c, etc.) or absolute names (names in parentheses in the table below, r0, r1, r2, etc.) can be used for description. table 28-1. operand identifiers and description methods identifier description method r x (r0), a (r1), c (r2), b (r3), e (r4), d (r5), l (r6), h (r7), rp ax (rp0), bc (rp1), de (rp2), hl (rp3) sfr special-function register symbol note sfrp special-function register symbol (16-bit manipulatable register even addresses only) note saddr fe20h to ff1fh immediate data or labels saddrp fe20h to ff1fh immediate data or labels (even address only) addr16 0000h to ffffh immediate data or labels (only even addresses for 16-bit data transfer instructions) addr11 0800h to 0fffh immediate data or labels addr5 0040h to 007fh immediate data or labels (even address only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label rbn rb0 to rb3 note addresses from ffd0h to ffdfh cannot be accessed with these operands. remark for special-function register symbols, refer to table 5-3 special-function register list . 583 chapter 28 instruction set 28.1.2 description of operation column a : a register; 8-bit accumulator x : x register b : b register c : c register d : d register e : e register h : h register l : l register ax : ax register pair; 16-bit accumulator bc : bc register pair de : de register pair hl : hl register pair pc : program counter sp : stack pointer psw : program status word cy : carry flag ac : auxiliary carry flag z : zero flag rbs : register bank select flag ie : interrupt request enable flag nmis : non-maskable interrupt servicing flag ( ) : memory contents indicated by address or register contents in parentheses x h , x l : higher 8 bits and lower 8 bits of 16-bit register /\ : logical product (and) \/ : logical sum (or) \/ : exclusive logical sum (exclusive or) : inverted data addr16 : 16-bit immediate data or label jdisp8 : signed 8-bit data (displacement value) 23.1.3 description of flag operation column (blank) : not affected 0 : cleared to 0 1 : set to 1 x : set/cleared according to the result r : previously saved value is restored 584 chapter 28 instruction set 28.2 operation list instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 8-bit data mov r, #byte 2 4 r ? byte transfer saddr, #byte 3 6 7 (saddr) ? byte sfr, #byte 3 ? 7 sfr ? byte a, r note 3 12 a ? r r, a note 3 12 r ? a a, saddr 2 4 5 a ? (saddr) saddr, a 2 4 5 (saddr) ? a a, sfr 2 ? 5 a ? sfr sfr, a 2 ? 5 sfr ? a a, !addr16 3 8 9 + n a ? (addr16) !addr16, a 3 8 9 + m (addr16) ? a psw, #byte 3 ? 7 psw ? byte x x x a, psw 2 ? 5 a ? psw psw, a 2 ? 5 psw ? a xxx a, [de] 1 4 5 + n a ? (de) [de], a 1 4 5 + m (de) ? a a, [hl] 1 4 5 + n a ? (hl) [hl], a 1 4 5 + m (hl) ? a a, [hl + byte] 2 8 9 + n a ? (hl + byte) [hl + byte], a 2 8 9 + m (hl + byte) ? a a, [hl + b] 1 6 7 + n a ? (hl + b) [hl + b], a 1 6 7 + m (hl + b) ? a a, [hl + c] 1 6 7 + n a ? (hl + c) [hl + c], a 1 6 7 + m (hl + c) ? a xch a, r note 3 12 a ? r a, saddr 2 4 6 a ? (saddr) a, sfr 2 ? 6 a ? sfr a, !addr16 3 8 10 +n+m a ? (addr16) a, [de] 1 4 6 +n+m a ? (de) a, [hl] 1 4 6 +n+m a ? (hl) a, [hl + byte] 2 8 10 +n+m a ? (hl + byte) a, [hl + b] 2 8 10 +n+m a ? (hl + b) a, [hl + c] 2 8 10 +n+m a ? (hl + c) notes 1. for instructions that access the internal high-speed ram area or perform no data access 2. for instructions that access an area other than the internal high-speed ram area 3. except when r = a remarks 1. one clock in the clock columns is equal to one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the values in the clock column assumes that the internal rom area contains programs. 3. n indicates wait cycles to be inserted when an external expansion memory area is read from. 4. m indicates wait cycles to be inserted when an external expansion memory area is written to. 585 chapter 28 instruction set instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 16-bit data movw rp, #word 3 6 rp ? word transfer saddrp, #word 4 8 10 (saddrp) ? word sfrp, #word 4 ? 10 sfrp ? word ax, saddrp 2 6 8 ax ? (saddrp) saddrp, ax 2 6 8 (saddrp) ? ax ax, sfrp 2 ? 8 ax ? sfrp sfrp, ax 2 ? 8 sfrp ? ax ax, rp note 3 1 4 ax ? rp rp, ax note 3 1 4 rp ? ax ax, !addr16 3 10 12 + 2n ax ? (addr16) !addr16, ax 3 10 12 + 2m (addr16) ? ax xchw ax, rp note 3 1 4 ax ? rp 8-bit add a, #byte 2 4 ? a, cy ? a + byte x x x operation saddr, #byte 3 6 8 (saddr), cy ? (saddr) + byte x x x a, r note 4 2 4 a, cy ? a + r x x x r, a 2 4 ? r, cy ? r + a x x x a, saddr 2 4 5 a, cy ? a + (saddr) x x x a, !addr16 3 8 9 + n a, cy ? a + (addr16) x x x a, [hl] 1 4 5 + n a, cy ? a + (hl) x x x a, [hl + byte] 2 8 9 + n a, cy ? a + (hl + byte) x x x a, [hl + b] 2 8 9 + n a, cy ? a + (hl + b) x x x a, [hl + c] 2 8 9 + n a, cy ? a + (hl + c) x x x addc a, #byte 2 4 ? a, cy ? a + byte + cy x x x saddr, #byte 3 6 8 (saddr), cy ? (saddr) + byte + cy x x x a, r note 4 2 4 a, cy ? a + r + cy x x x r, a 2 4 ? r, cy ? r + a + cy x x x a, saddr 2 4 5 a, cy ? a + (saddr) + cy x x x a, !addr16 3 8 9 + n a, cy ? a + (addr16) + cy x x x a, [hl] 1 4 5 + n a, cy ? a + (hl) + cy x x x a, [hl + byte] 2 8 9 + n a, cy ? a + (hl + byte) + cy x x x a, [hl + b] 2 8 9 + n a, cy ? a + (hl + b) + cy x x x a, [hl + c] 2 8 9 + n a, cy ? a + (hl + c) + cy x x x notes 1. for instructions that access the internal high-speed ram area or perform no data access 2. for instructions that access an area other than the internal high-speed ram area 3. only when rp = bc, de, or hl 4. except when r = a remarks 1. one clock in the clock columns is equal to one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the values in the clock column assumes that the internal rom area contains programs. 3. n indicates wait cycles to be inserted when an external expansion memory area is read from. 4. m indicates wait cycles to be inserted when an external expansion memory area is written to. 586 chapter 28 instruction set instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 8-bit sub a, #byte 2 4 a, cy ? a e byte x x x operation saddr, #byte 3 6 8 (saddr), cy ? (saddr) e byte x x x a, r note 3 2 4 a, cy ? a e r x x x r, a 2 4 ? r, cy ? r e a x x x a, saddr 2 4 5 a, cy ? a e (saddr) x x x a, !addr16 3 8 9 + n a, cy ? a e (addr16) x x x a, [hl] 1 4 5 + n a, cy ? a e (hl) x x x a, [hl + byte] 2 8 9 + n a, cy ? a e (hl + byte) x x x a, [hl + b] 2 8 9 + n a, cy ? a e (hl + b) x x x a, [hl + c] 2 8 9 + n a, cy ? a e (hl + c) x x x subc a, #byte 2 4 ? a, cy ? a e byte e cy x x x saddr, #byte 3 6 8 (saddr), cy ? (saddr) e byte e cy x x x a, r note 3 2 4 a, cy ? a e r e cy x x x r, a 2 4 ? r, cy ? r e a e cy x x x a, saddr 2 4 5 a, cy ? a e (saddr) e cy x x x a, !addr16 3 8 9 + n a, cy ? a e (addr16) e cy x x x a, [hl] 1 4 5 + n a, cy ? a e (hl) e cy x x x a, [hl + byte] 2 8 9 + n a, cy ? a e (hl + byte) e cy x x x a, [hl + b] 2 8 9 + n a, cy ? a e (hl + b) e cy x x x a, [hl + c] 2 8 9 + n a, cy ? a e (hl + c) e cy x x x and a, #byte 2 4 ? a ? a /\ byte x saddr, #byte 3 6 8 (saddr) ? (saddr) /\ byte x a, r note 3 24 a ? a /\ r x r, a 2 4 ? r ? r /\ a x a, saddr 2 4 5 + n a ? a /\ (saddr) x a, !addr16 3 8 9 + n a ? a /\ (addr16) x a, [hl] 1 4 5 + n a ? a /\ (hl) x a, [hl + byte] 2 8 9 + n a ? a /\ (hl + byte) x a, [hl + b] 2 8 9 + n a ? a /\ (hl + b) x a, [hl + c] 2 8 9 + n a ? a /\ (hl + c) x notes 1. for instructions that access the internal high-speed ram area or perform no data access 2. for instructions that access an area other than the internal high-speed ram area 3. except when r = a remarks 1. one clock in the clock columns is equal to one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the values in the clock column assumes that the internal rom area contains programs. 3. n indicates wait cycles to be inserted when an external expansion memory area is read from. 587 chapter 28 instruction set instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 8-bit or a, #byte 2 4 a ? a \/ byte x operation saddr, #byte 3 6 8 (saddr) ? (saddr) \/ byte x a, r note 3 24 a ? a \/ r x r, a 2 4 ? r ? r \/ a x a, saddr 2 4 5 a ? a \/ (saddr) x a, !addr16 3 8 9 + n a ? a \/ (addr16) x a, [hl] 1 4 5 + n a ? a \/ (hl) x a, [hl + byte] 2 8 9 + n a ? a \/ (hl + byte) x a, [hl + b] 2 8 9 + n a ? a \/ (hl + b) x a, [hl + c] 2 8 9 + n a ? a \/ (hl + c) x xor a, #byte 2 4 ? a ? a \/ byte x saddr, #byte 3 6 8 (saddr) ? (saddr) \/ byte x a, r note 3 24 a ? a \/ rx r, a 2 4 ? r ? r \/ ax a, saddr 2 4 5 + n a ? a \/ (saddr) x a, !addr16 3 8 9 + n a ? a \/ (addr16) x a, [hl] 1 4 5 + n a ? a \/ (hl) x a, [hl + byte] 2 8 9 + n a ? a \/ (hl + byte) x a, [hl + b] 2 8 9 + n a ? a \/ (hl + b) x a, [hl + c] 2 8 9 + n a ? a \/ (hl + c) x cmp a, #byte 2 4 ? a e byte x x x saddr, #byte 3 6 8 (saddr) e byte x x x a, r note 3 24 a C r xxx r, a 2 4 r C a x x x a, saddr 2 4 5 + n a C (saddr) x x x a, !addr16 3 8 9 + n a C (addr16) x x x a, [hl] 1 4 5 + n a C (hl) x x x a, [hl + byte] 2 8 9 + n a C (hl + byte) x x x a, [hl + b] 2 8 9 + n a C (hl + b) x x x a, [hl + c] 2 8 9 + n a C (hl + c) x x x notes 1. for instructions that access the internal high-speed ram area or perform no data access 2. for instructions that access an area other than the internal high-speed ram area 3. except when r = a remarks 1. one clock in the clock columns is equal to one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the values in the clock column assumes that the internal rom area contains programs. 3. n indicates wait cycles to be inserted when an external expansion memory area is read from. 588 chapter 28 instruction set instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy 16-bit addw ax, #word 3 6 ax, cy ? ax + word x x x operation subw ax, #word 3 6 ? ax, cy ? ax e word x x x cmpw ax, #word 3 6 ? ax e word x x x multiply mulu x 2 16 ? ax ? a x x divide divuw c 2 25 ? ax (quotient), c (remainder) ? ax/c increment inc r 1 2 ? r ? r + 1 x x decrement saddr 2 4 6 (saddr) ? (saddr) + 1 x x dec r 1 2 ? r ? r e 1 x x saddr 2 4 6 (saddr) ? (saddr) e 1 x x incw rp 1 4 ? rp ? rp + 1 decw rp 1 4 ? rp ? rp e 1 rotate ror a, 1 1 2 ? (cy, a 7 ? a 0 , a m - 1 ? a m ) x 1 time x rol a, 1 1 2 ? (cy, a 0 ? a 7 , a m + 1 ? a m ) x 1 time x rorc a, 1 1 2 ? (cy ? a 0 , a 7 ? cy, a m - 1 ? a m ) x 1 time x rolc a, 1 1 2 ? (cy ? a 7 , a 0 ? cy, a m + 1 ? a m ) x 1 time x ror4 [hl] 2 10 12+n+m a 3 - 0 ? (hl) 3 - 0 , (hl) 7 - 4 ? a 3 - 0 , (hl) 3 - 0 ? (hl) 7 - 4 rol4 [hl] 2 10 12+n+m a 3 - 0 ? (hl) 7 - 4 , (hl) 3 - 0 ? a 3 - 0 , (hl) 7 - 4 ? (hl) 3 - 0 bcd adjba 2 4 ? decimal adjust accumulator after addition x x x adjust adjbs 2 4 ? decimal adjust accumulator after subtract x x x bit mani- mov1 cy, saddr.bit 3 6 7 cy ? (saddr.bit) x pulation cy, sfr.bit 3 ? 7 cy ? sfr.bit x cy, a.bit 2 4 ? cy ? a.bit x cy, psw.bit 3 ? 7 cy ? psw.bit x cy, [hl].bit 2 6 7 + n cy ? (hl).bit x saddr.bit, cy 3 6 8 (saddr.bit) ? cy sfr.bit, cy 3 ? 8 sfr.bit ? cy a.bit, cy 2 4 ? a.bit ? cy psw.bit, cy 3 ? 8 psw.bit ? cy x x [hl].bit, cy 2 6 8+n+m (hl).bit ? cy notes 1. for instructions that access the internal high-speed ram area or perform no data access 2. for instructions that access an area other than the internal high-speed ram area remarks 1. one clock in the clock columns is equal to one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the values in the clock column assumes that the internal rom area contains programs. 3. n indicates wait cycles to be inserted when an external expansion memory area is read from. 4. m indicates wait cycles to be inserted when an external expansion memory area is written to. 589 chapter 28 instruction set instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy bit mani- and1 cy, saddr.bit 3 6 7 cy ? cy /\ (saddr.bit) x pulation cy, sfr.bit 3 ? 7 cy ? cy /\ sfr.bit x cy, a.bit 2 4 ? cy ? cy /\ a.bit x cy, psw.bit 3 ? 7 cy ? cy /\ psw.bit x cy, [hl].bit 2 6 7 + n cy ? cy /\ (hl).bit x or1 cy, saddr.bit 3 6 7 cy ? cy \/ (saddr.bit) x cy, sfr.bit 3 ? 7 cy ? cy \/ sfr.bit x cy, a.bit 2 4 ? cy ? cy \/ a.bit x cy, psw.bit 3 ? 7 cy ? cy \/ psw.bit x cy, [hl].bit 2 6 7 + n cy ? cy \/ (hl).bit x xor1 cy, saddr.bit 3 6 7 cy ? cy \/ (saddr.bit) x cy, sfr.bit 3 ? 7 cy ? cy \/ sfr.bit x cy, a.bit 2 4 ? cy ? cy \/ a.bit x cy, psw. bit 3 ? 7 cy ? cy \/ psw.bit x cy, [hl].bit 2 6 7 + n cy ? cy \/ (hl).bit x set1 saddr.bit 2 4 6 (saddr.bit) ? 1 sfr.bit 3 ? 8 sfr.bit ? 1 a.bit 2 4 ? a.bit ? 1 psw.bit 2 ? 6 psw.bit ? 1xxx [hl].bit 2 6 8+n+m (hl).bit ? 1 clr1 saddr.bit 2 4 6 (saddr.bit) ? 0 sfr.bit 3 ? 8 sfr.bit ? 0 a.bit 2 4 ? a.bit ? 0 psw.bit 2 ? 6 psw.bit ? 0xxx [hl].bit 2 6 8+n+m (hl).bit ? 0 set1 cy 1 2 ? cy ? 11 clr1 cy 1 2 ? cy ? 00 not1 cy 1 2 ? cy ? cy x notes 1. for instructions that access the internal high-speed ram area or perform no data access 2. for instructions that access an area other than the internal high-speed ram area remarks 1. one clock in the clock columns is equal to one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the values in the clock column assumes that the internal rom area contains programs. 3. n indicates wait cycles to be inserted when an external expansion memory area is read from. 4. m indicates wait cycles to be inserted when an external expansion memory area is written to. 590 chapter 28 instruction set instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy call / call !addr16 3 7 (sp C 1) ? (pc + 3) h , (sp - 2) ? (pc + 3) l , return pc ? addr16, sp ? sp e 2 callf !addr11 2 5 ? (sp e 1) ? (pc + 2) h , (sp e 2) ? (pc + 2) l , pc 15 - 11 ? 00001, pc 10 - 0 ? addr11, sp ? sp e 2 callt [addr5] 1 6 ? (sp e 1) ? (pc + 1) h , (sp e 2) ? (pc + 1) l , pc h ? (00000000, addr5 + 1), pc l ? (00000000, addr5), sp ? sp e 2 brk 1 6 ? (sp e 1) ? psw, (sp e 2) ? (pc + 1) h , (sp e 3) ? (pc + 1) l , pc h ? (003fh), pc l ? (003eh), sp ? sp e 3, ie ? 0 ret 1 6 ? pc h ? (sp + 1), pc l ? (sp), sp ? sp + 2 reti 1 6 ? pc h ? (sp + 1), pc l ? (sp), r r r psw ? (sp + 2), sp ? sp + 3, nmis ? 0 retb 1 6 ? pc h ? (sp + 1), pc l ? (sp), r r r psw ? (sp + 2), sp ? sp + 3 stack push psw 1 2 ? (sp e 1) ? psw, sp ? sp e 1 manipulate rp 1 4 ? (sp e 1) ? rp h , (sp e 2) ? rp l , sp ? sp e 2 pop psw 1 2 ? psw ? (sp), sp ? sp + 1 r r r rp 1 4 ? rp h ? (sp + 1), rp l ? (sp), sp ? sp + 2 movw sp, #word 4 ? 10 sp ? word sp, ax 2 ? 8 sp ? ax ax, sp 2 ? 8 ax ? sp uncondi- br !addr16 3 6 ? pc ? addr16 tional $addr16 2 6 ? pc ? pc + 2 + jdisp8 branch ax 2 8 ? pc h ? a, pc l ? x conditional bc $addr16 2 6 ? pc ? pc + 2 + jdisp8 if cy = 1 branch bnc $addr16 2 6 ? pc ? pc + 2 + jdisp8 if cy = 0 bz $addr16 2 6 ? pc ? pc + 2 + jdisp8 if z = 1 bnz $addr16 2 6 ? pc ? pc + 2 + jdisp8 if z = 0 notes 1. for instructions that access the internal high-speed ram area or perform no data access 2. for instructions that access an area other than the internal high-speed ram area remarks 1. one clock in the clock columns is equal to one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the values in the clock column assumes that the internal rom area contains programs. 591 chapter 28 instruction set instruction mnemonic operands byte clock operation flag group note 1 note 2 zaccy conditional bt saddr.bit, $addr16 3 8 9 pc ? pc + 3 + jdisp8 if(saddr.bit) = 1 branch sfr.bit, $addr16 4 ? 11 pc ? pc + 4 + jdisp8 if sfr.bit = 1 a.bit, $addr16 3 8 ? pc ? pc + 3 + jdisp8 if a.bit = 1 psw.bit, $addr16 3 ? 9 pc ? pc + 3 + jdisp8 if psw.bit = 1 [hl].bit, $addr16 3 10 11 + n pc ? pc + 3 + jdisp8 if (hl).bit = 1 bf saddr.bit, $addr16 4 10 11 pc ? pc + 4 + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr16 4 ? 11 pc ? pc + 4 + jdisp8 if sfr.bit = 0 a.bit, $addr16 3 8 ? pc ? pc + 3 + jdisp8 if a.bit = 0 psw.bit, $addr16 4 ? 11 pc ? pc + 4 + jdisp8 if psw. bit = 0 [hl].bit, $addr16 3 10 11 + n pc ? pc + 3 + jdisp8 if (hl).bit = 0 btclr saddr.bit, $addr16 4 10 12 pc ? pc + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit) sfr.bit, $addr16 4 ? 12 pc ? pc + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit a.bit, $addr16 3 8 ? pc ? pc + 3 + jdisp8 if a.bit = 1 then reset a.bit psw.bit, $addr16 4 ? 12+n+m pc ? pc + 4 + jdisp8 if psw.bit = 1 x x x then reset psw.bit [hl].bit, $addr16 3 10 12 pc ? pc + 3 + jdisp8 if (hl).bit = 1 then reset (hl).bit dbnz b, $addr16 2 6 ? b ? b e 1, then pc ? pc + 2 + jdisp8 if b 1 0 c, $addr16 2 6 ? c ? c e1, then pc ? pc + 2 + jdisp8 if c 1 0 saddr. $addr16 3 8 10 (saddr) ? (saddr) e 1, then pc ? pc + 3 + jdisp8 if(saddr) 1 0 cpu sel rbn 2 4 ? rbs1, 0 ? n control nop 1 2 ? no operation ei 2 ? 6 ie ? 1 (enable interrupt) di 2 ? 6 ie ? 0 (disable interrupt) halt 2 6 ? set halt mode stop 2 6 ? set stop mode notes 1. for instructions that access the internal high-speed ram area or perform no data access 2. for instructions that access an area other than the internal high-speed ram area remarks 1. one clock in the clock columns is equal to one cycle of the cpu clock (f cpu ) selected by the processor clock control register (pcc). 2. the values in the clock column assumes that the internal rom area contains programs. 3. n indicates wait cycles to be inserted when an external expansion memory area is read from. 4. m indicates wait cycles to be inserted when an external expansion memory area is written to. 592 chapter 28 instruction set 28.3 instructions listed by addressing type (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 593 chapter 28 instruction set second operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none first operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except when r = a 594 chapter 28 instruction set (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw second operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr second operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none first operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 595 chapter 28 instruction set (4) call/instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz second operand ax !addr16 !addr11 [addr5] $addr16 first operand basic instruction br call callf callt br br bc bnc bz bnz compound bt instruction bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop 596 [memo] 597 appendix a differences between m pd78078, 78075b subseries, and m pd78070a the major differences between the m pd78078, 78075b subseries, and m pd78070a are shown in table a-1. table a-1. major differences between m pd78078, 78075b subseries, and m pd78070a part number m pd78078 subseries m pd78075b subseries m pd78070a item anti-emi noise measure not provided provided not provided product equipped with i 2 c bus available not available available supply voltage v dd = 1.8 to 5.5 v v dd = 2.7 to 5.5 v internal rom size m pd78076 : 48 kbytes m pd78074b : 32 kbytes not provided m pd78078, 78p078 m pd78075b : 40 kbytes : 60 kbytes internal expansion ram size 1024 bytes none i/o port total 88 61 cmos input 2 cmos i/o 78 51 n-ch open-drain i/o 8 pins with note 1 pin with pull-up resistor 86 (78 for m pd78p078) 51 additional medium-voltage pin 8 not provided functions led direct drive output 16 not provided 4 av dd pin provided not provided provided (av ref0 pin functions alternately) external bus mode selectable from multiplexed bus mode or separate only separate bus mode expansion bus mode function memory expansion mode selectable from four types of memory expansion modes only full-address mode rom correction function provided not provided package 100-pin plastic qfp 100-pin plastic qfp 100-pin plastic qfp (fine pitch) (14 x 14 mm) note 2 (fine pitch) (14 x 14 mm) (fine pitch) (14 x 14 mm) ? 100-pin plastic lqfp ? 100-pin plastic lqfp ? 100-pin plastic lqfp (fine pitch) (14 x 14 mm) (fine pitch) (14 x 14 mm) (fine pitch) (14 x 14 mm) note 4 ? 100-pin plastic qfp ? 100-pin plastic qfp ? 100-pin plastic qfp (14 x 20 mm) (14 x 20 mm) (14 x 20 mm) ? 100-pin ceramic wqfn note 3 electrical specifications refer to the data sheet of individual product. recommended soldering conditions notes 1. the number of i/o ports includes the pins with additional functions. 2. not available in the y subseries 3. prom version only 4. under development 598 [memo] 599 appendix b development tools the following development tools are available for the development of systems which employ the m pd78078 and 78078y subseries. figure b-1 shows the configuration example of the tools. 600 appendix b development tools figure b-1. development tool configuration (1/2) (1) when using in-circuit emulator ie-78k0-ns prom programming tool ?pg-1500 controller language processing software ?assembler package ?c compiler package ?c library source file ?device file debugging tool ?system simulator ?integrated debugger ?device file embedded software ?real-time os ?os host machine (pc) interface adapter, pc card interface, etc. prom programming environment prom programmer programmer adapter prom-contained version in-circuit emulator emulation board emulation probe power supply unit conversion socket or conversion adapter target system 601 appendix b development tools figure b-1. development tool configuration (2/2) (2) when using in-circuit emulator ie-78001-r-a prom programming tool ?pg-1500 controller language processing software ?assembler package ?c compiler package ?c library source file ?device file debugging tool ?system simulator ?integrated debugger ?device file embedded software ?real-time os ?os host machine (pc or ews) interface board prom programming environment prom programmer programmer adapter prom-contained version in-circuit emulator emulation board emulation probe conversion socket or conversion adapter target system i/o board probe board emulation probe conversion board interface adapter remark the parts shown within broken lines differ depending on the developing environment. refer to b.3.1 hardware . 602 appendix b development tools b.1 language processing software ra78k/0 a program that converts a program written in mnemonic into object assembler package codes that microcomputers can process. provided with functions to automatically perform generation of symbol table, optimizing processing of branch instructions, etc. used in combination with separately available device file (df78078). 603 appendix b development tools remark xxxx in the part number differs depending on the host machine and os used. m sxxxx ra78k0 m sxxxx cc78k0 m sxxxx df78078 m sxxxx cc78k0-l xxxx host machine os supply media aa13 pc-9800 series japanese windows notes 1, 2 3.5-inch 2hd fd ab13 ibm pc/at? and japanese windows notes 1, 2 3.5-inch 2hc fd bb13 compatibles english windows notes 1, 2 3p16 hp9000 series 700? hp-ux? (rel. 9.05) dat (dds) 3k13 sparcstation? sunos? (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news? (risc) news-os? (rel. 6.1) 3.5-inch 2hc fd notes 1. operates also in dos environment. 2. does not support windowsnt? 604 appendix b development tools b.2 prom writing tools b.2.1 hardware pg-1500 prom programmer pa-78p078gc pa-78p078gf pa-78p078kl-t prom programmer adapter a prom programmer that, by connecting the attached board and separately available prom programmer adapter, is capable of programming single- chip microcomputers incorporating a prom on stand-alone basis or through operation from the host machine. also capable of programming typical 256-kbit to 4-mbit prom. a prom programmer adapter for the m pd78p078 and m pd78p078y. used connected to the pg-1500. pa-78p078gc : 100-pin plastic qfp (gc-7ea, gc-8eu type) pa-78p078gf : 100-pin plastic qfp (gf-3ba type) pa-78p078kl-t : 100-pin ceramic wqfn (kl-t type) b.2.2 software pg-1500 controller connects pg-1500 and the host machine with serial and parallel interface, and controls the pg-1500 on the host machine. the pg-1500 controller is a dos-based application. use it with the dos prompt on windows. part number: m sxxxxpg1500 remark xxxx in the part number differs depending on the host machine and os used. m sxxxx pg1500 xxxx host machine os supply media 5a13 pc-9800 series ms-dos 3.5-inch 2hd fd (ver. 3.30 to ver. 6.2 note ) 5b13 ibm pc/at and refer to b.4 3.5-inch 2hc fd compatibles note ms-dos ver. 5.0 or later has a task swap function, but it cannot be used with the above software. 605 appendix b development tools an in-circuit emulator to debug hardware and software when developing application systems that use the 78k/0 series. supports integrated debugger (id78k0-ns). used in combination with a power supply unit, emulation probe, and interface adapter to connect to the host machine. an adapter to supply voltage from ac100 to 240-v outlet. an adapter required for using a pc-9800 series computer (except notebook- type personal computer) as the host machine for the ie-78k0-ns. a pc card and an interface cable required for using pc-9800 series notebook-type personal computer as the host machine for the ie-78k0- ns. an adapter required when using an ibm pc/at and compatible as the host machine for the ie-78k0-ns. a board to emulate peripheral hardware peculiar to the device. used in combination with an in-circuit emulator. a probe to connect an in-circuit emulator and a target system. for 100-pin plastic qfp (gc-7ea, gc-8eu type) a conversion adapter to connect the board of a target system that is designed to mount 100-pin plastic qfp (gc-7ea, gc-8eu type) and the np-100gc. the m pd78p078kl-t and 78p078ykl-t (ceramic wqfn) can be mounted instead of connecting np-100gc. a probe to connect an in-circuit emulator and the target system. for 100-pin plastic qfp (gf-3ba type). a conversion socket to connect the board of a target system designed to mount 100-pin plastic qfp (gf-3ba type) to the np-100gf. b.3 debugging tools b.3.1 hardware (1/2) (1) when using in-circuit emulator ie-78k0-ns note under development remarks 1. the np-100gc and np-100gf are products of naito densei machidaseisakusho co., ltd. contact: naito densei machidaseisakusho co., ltd (tel: (044)822-3813) 2. the tgc-100sdw is a product of tokyo eletech corporation. contact: daimaru kogyo co., ltd. tokyo electronic component department (tel: (03)3820-7112) osaka electronic component department (tel: (06)244-6672) 3. the tgc-100sdw is sold singly. 4. the ev-9200gf-100 is sold in a set of five. ie-78k0-ns note in-circuit emulator ie-70000-mc-ps-b power supply adapter ie-70000-98-if-c note interface adapter ie-70000-cd-if note pc card interface ie-70000-pc-if-c note interface adapter ie-78078-ns-em1 note emulation board np-100gc emulation probe tgc-100sdw conversion adapter (refer to figure b-2 ) np-100gf emulation probe ev-9200gf-100 conversion socket (refer to figure b-3 ) 606 appendix b development tools b.3.1 hardware (2/2) (2) when using in-circuit emulator ie-78001-r-a ie-78001-r-a note in-circuit emulator ie-70000-98-if-b or ie-70000-98- if-c note interface adapter ie-70000-pc-if-b or ie-70000-pc- if-c note interface adapter ie-78000-r-sv3 interface adapter ie-78078-ns-em1 note emulation board ie-78k0-r-ex1 note emulation probe conversion board ie-78078-r-em emulation board ep-78064gc-r emulation probe tgc-100sdw conversion adapter (refer to figure b-2 ) ep-78064gf-r emulation probe ev-9200gf-100 conversion socket (refer to figure b-3 ) an in-circuit emulator to debug hardware and software when developing application systems that use the 78k/0 series. supports integrated debugger (id78k0). used in combination with an interface adapter to connect to an emulation probe and the host machine. an adapter required for using a pc-9800 series (except notebook-type personal computer) as the host machine for the ie-78001-r-a. an adapter required for using an ibm pc/at or compatible as the host machine for the ie-78001-r-a. an adapter and a cable required for using ews as the host machine for the ie-78001-r-a. used connected to the board in the ie-78001-r-a. supports 10base-5 for ethernet tm . a separately available adapter required for other systems. a board to emulate peripheral hardware peculiar to the device. used in combination with an in-circuit emulator and emulation probe conversion board. a board required for using the ie-78078-ns-em1 with the ie-78001-r-a a board to emulate peripheral hardware peculiar to the device (supports 3.0 to 5.5 v). used in combination with the ie-78001-r-a. a probe to connect an in-circuit emulator and the target system. for 100-pin plastic qfp (gc-7ea, gc-8eu type). a conversion adapter to connect the board of a target system designed to mount 100-pin plastic qfp (gc-7ea, gc-8eu type) and the ep- 78064gc-r. the m pd78p078kl-t or 78p078ykl-t (ceramic wqfn) can be mounted instead of connecting the ep-78064gc-r. a probe to connect an in-circuit emulator and the target system. for 100-pin plastic qfp (gf-3ba type). a conversion socket to connect the board of a target system designed to mount 100-pin plastic qfp (gf-3ba type) to the ep-78064gf-r. note under development remarks 1. the tgk-100sdw is a product of tokyo eletech corporation. contact: daimaru kogyo co., ltd. tokyo electronic component department (tel: (03)3820-7112) osaka electronic component department (tel: (06)244-6672) 2. the tgc-100sdw is sold singly. 3. the ev-9200gf-100 is sold in a set of five. 607 appendix b development tools b.3.2 software (1/2) sm78k0 capable of debugging in c source level or assembler level while simulating system simulator the operation of the target system on the host machine. the sm78k0 operates on windows. the use of the sm78k0 enables the verification of logic and performance of applications independently from hardware development without using in-circuit emulator and improves the development efficiency and the software quality. used in combination with separately available device file (df78078). part number: m sxxxxsm78k0 remark xxxx in the part number differs depending on the host machine and os used. m sxxxx sm78k0 xxxx host machine os supply media aa13 pc-9800 series japanese windows notes 1, 2 3.5-inch 2hd fd ab13 ibm pc/at and japanese windows notes 1, 2 3.5-inch 2hc fd bb13 compatible english windows note note does not support windowsnt. 608 appendix b development tools b.3.2 software (2/2) id78k0-ns note integrated debugger (supporting in-circuit emulator ie-78k0-ns) id78k0 integrated debugger (supporting in-circuit emulator ie-78001-r-a) note under development remark xxxx in the part number differs depending on the host machine and os used. m sxxxx id78k0-ns xxxx host machine os supply media aa13 pc-9800 series japanese windows note 3.5-inch 2hd fd ab13 ibm pc/at and japanese windows note 3.5-inch 2hc fd bb13 compatible english windows note note does not support windowsnt. m sxxxx id78k0 xxxx host machine os supply media aa13 pc-9800 series japanese windows note 3.5-inch 2hd fd ab13 ibm pc/at and japanese windows note 3.5-inch 2hc fd bb13 compatible english windows note 3p16 hp9000 series 700 hp-ux (rel. 9.05) dat (dds) 3k13 sparcstation sunos (rel. 4.1.4) 3.5-inch 2hc fd 3k15 1/4-inch cgmt 3r13 news (risc) news-os (rel. 6.1) 3.5-inch 2hc fd note does not support windowsnt. a control program to debug the 78k/0 series. adopting windows on personal computers and osf/motif? on ews as graphical user interface, presents the appearance and the operability conforming to them. enhancing the debugging function that supports c language, the trace result can be displayed in the c language level by using window integration function which correlates the source program, disassembly display, and memory display to the trace result. in addition, the debugging efficiency of programs using real-time os can be improved by integrating function extension modules such as task debuggers and system performance analyzers. used in combination with separately available device file (df78078). part number: m sxxxxid78k0-ns, m sxxxxid78k0. 609 appendix b development tools b.4 os for ibm pc the following oss are supported for ibm pc. table b-1. os for ibm pc os version pc dos ver. 5.02 to ver. 6.3 j6.1/v note to j6.3/v note ibm dos? j5.02/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note note only english mode is supported. caution ms-dos ver. 5.0 or later has a task swap function, but it cannot be used with the above software. b.5 system upgrading from former-type in-circuit emulator for 78k/0 series to ie-78001-r-a if the user already owns a former-type in-circuit emulator for the 78k/0 series (ie-78000-r or ie-78000-r-a), it can be used in the same manner as the ie-78001-r-a by replacing the break board inside the main unit with the ie-78001-r-bk (under development). table b-2. system upgrading from former-type in-circuit emulator for 78k/0 series to ie-78001-r-a in-circuit unit owned system upgrading of enclosure note board to be purchased ie-78000-r required ie-78001-r-bk ie-78000-r-a not required note to system up-grade the enclosure, the unit must be brought to nec. 610 appendix b development tools item millimeters inches b 1.85 0.25 0.073 0.010 c 3.5 0.138 a 14.45 0.569 d 2.0 0.079 h 16.0 0.630 i 1.125 0.3 0.044 0.012 j 0~5 0.000~0.197 e 3.9 0.154 f 0.25 g 4.5 0.177 tgc-100sdw-g1e 0.010 k 5.9 0.232 l 0.8 0.031 m 2.4 0.094 n 2.7 0.106 item millimeters inches b 0.5x24=12 0.020x0.945=0.472 c 0.5 0.020 a 21.55 0.848 d 0.5x24=12 0.020x0.945=0.472 h 10.9 0.429 i 13.3 0.524 j 15.7 0.618 e 15.0 0.591 f 21.55 g 3.55 0.140 0.848 k 18.1 0.713 l 13.75 0.541 m 0.5x24=12.0 0.020x0.945=0.472 q 10.0 0.394 r 11.3 0.445 s 18.1 0.713 n 1.125 0.3 0.044 0.012 o 1.125 0.2 p 7.5 0.295 0.044 0.008 w 1.8 0.071 x c 2.0 c 0.079 y 0.9 0.035 t 5.0 0.197 u 5.0 v 4- 1.3 4- 0.051 0.197 z 0.3 0.012 f ff f f f f f f f ff tgc-100sdw (tqpack100sd + tqsocket100sdw) package dimension (unit: mm) h a b c i j k g f e d n o l m x p q r s u protrusion height w v k i m n z j g i h a e d c b y f x t note : product by tokyo eletech corporation. drawing for conversion adapter (tgc-100sdw) figure b-2. tgc-100sdw drawing (for reference only) 611 appendix b development tools ev-9200gf-100 a d e b f 1 no.1 pin index m n o l k s r q i h g p c j ev-9200gf-100-g0 item millimeters inches a b c d e f g h i j k l m n o p q r s 24.6 21 15 18.6 4-c 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.969 0.827 0.591 0.732 4-c 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f f f f socket drawing and recommended footprints (ev-9200gf-100) figure b-3. ev-9200gf-100 drawing (for reference only) 612 appendix b development tools f h e d a b c i j k l 0.026 x 1.142 = 0.742 0.026 x 0.748 = 0.486 ev-9200gf-100-p1 item millimeters inches a b c d e f g h i j k l 26.3 21.6 15.6 20.3 12 0.05 6 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 1.035 0.85 0.614 0.799 0.472 0.236 0.014 0.093 0.091 0.062 0.65 0.02 x 29 = 18.85 0.05 0.65 0.02 x 19 = 12.35 0.05 f +0.001 ?.002 +0.002 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 f +0.001 ?.002 f f g f f based on ev-9200gf-100 (2) pad drawing (in mm) dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to ?emiconductor device mounting technology manual?(c10535e). caution figure b-4. ev-9200gf-100 recommended footprints (for reference only) 613 appendix c embedded software for efficient program development and maintenance of the m pd78078, 78078y subseries, the following embedded software is available. real-time os (1/2) rx78k/0 a real-time os conforming to m itron specifications. real-time os added with the tool (configurator) to create the rx78k/0 nucleus and multiple information table. used in combination with separately available assembler package (ra78k/0) and device file (df78078). 614 appendix c embedded software real-time os (2/2) mx78k0 a m itron specification subset os. added with mx78k0 nucleus. os performs task management, event management, and time management. in task management, controls the execution order of tasks and performs processing to change the task to the one executed next. 615 appendix d register index d.1 register name index [a] a/d conversion result register (adcr) ... 295 a/d converter input select register (adis) ... 298 a/d converter mode register (adm) ... 296 asynchronous serial interface mode register (asim) ... 462 asynchronous serial interface status register (asis) ... 464 automatic data transmit/receive address pointer (adtp) ... 417 automatic data transmit/receive interval specify register (adti) ... 421 automatic data transmit/receive control register (adtc) ... 420 [b] baud rate generator control register (brgc) ... 465 [c] capture/compare control register 0 (crc0) ... 193 capture/compare register 00 (cr00) ... 188 capture/compare register 01 (cr01) ... 188 compare register 10 (cr10) ... 230 compare register 20 (cr20) ... 230 compare register 50 (cr50) ... 253 compare register 60 (cr60) ... 253 correction address register 0 (corad0) ... 560 correction address register 1 (corad1) ... 560 correction control register (corcn) ... 561 [d] d/a conversion value set register 0 (dacs0) ... 311 d/a conversion value set register 1 (dacs1) ... 311 d/a converter mode register (dam) ... 312 616 appendix d register index [e] 8-bit timer mode control register 1 (tmc1) ... 233 8-bit timer mode control register 5 (tmc5) ... 256 8-bit timer mode control register 6 (tmc6) ... 257 8-bit timer output control register (toc1) ... 234 8-bit timer register 1 (tm1) ... 230 8-bit timer register 2 (tm2) ... 230 8-bit timer register 5 (tm5) ... 253 8-bit timer register 6 (tm6) ... 253 external bus type select register (ebts) ... 533 external interrupt mode register 0 (intm0) ... 196, 508 external interrupt mode register 1 (intm1) ... 299, 508 [ i ] internal extension ram size switching register (ixs) ... 571 internal memory size switching register (ims) ... 532, 570 interrupt mask flag register 0h (mk0h) ... 506 interrupt mask flag register 0l (mk0l) ... 506 interrupt mask flag register 1l (mk1l) ... 506, 524 interrupt request flag register 0h (if0h) ... 505 interrupt request flag register 0l (if0l) ... 505 interrupt request flag register 1l (if1l) ... 505, 524 interrupt timing specify register (sint) ... 327, 378 [k] key return mode register (krm) ... 162, 525 [m] memory expansion mode register (mm) ... 161, 531 [o] oscillation mode selection register (osms) ... 170 oscillation stabilization time select register (osts) ... 546 617 appendix d register index [p] port 0 (p0) ... 136 port 1 (p1) ... 138 port 2 (p2) ... 139, 141 port 3 (p3) ... 143 port 4 (p4) ... 144 port 5 (p5) ... 145 port 6 (p6) ... 146 port 7 (p7) ... 148 port 8 (p8) ... 150 port 9 (p9) ... 151 port 10 (p10) ... 153 port 12 (p12) ... 155 port 13 (p13) ... 156 port mode register 0 (pm0) ... 157 port mode register 1 (pm1) ... 157 port mode register 2 (pm2) ... 157 port mode register 3 (pm3) ... 157, 195, 235, 287, 292 port mode register 5 (pm5) ... 157 port mode register 6 (pm6) ... 157 port mode register 7 (pm7) ... 157 port mode register 8 (pm8) ... 157 port mode register 9 (pm9) ... 157 port mode register 10 (pm10) ... 157, 258 port mode register 12 (pm12) ... 157, 497 port mode register 13 (pm13) ... 157 priority specify flag register 0h (pr0h) ... 507 priority specify flag register 0l (pr0l) ... 507 priority specify flag register 1l (pr1l) ... 507 processor clock control register (pcc) ... 167 pull-up resistor option register h (puoh) ... 160 pull-up resistor option register l (puol) ... 160 [r] real-time output buffer register h (rtbh) ... 496 real-time output buffer register l (rtbl) ... 496 real-time output port control register (rtpc) ... 498 real-time output port mode register (rtpm) ... 497 receive buffer register (rxb) ... 460 receive shift register (rxs) ... 460 618 appendix d register index [s] sampling clock select register (scs) ... 197, 510 serial bus interface control register (sbic) ... 325, 376 serial i/o shift register 0 (sio0) ... 319, 370 serial i/o shift register 1 (sio1) ... 417 serial operating mode register 0 (csim0) ... 323, 374 serial operating mode register 1 (csim1) ... 419 serial operating mode register 2 (csim2) ... 461 16-bit timer mode control register (tmc0) ... 192 16-bit timer output control register (toc0) ... 194 16-bit timer register (tm0) ... 189 16-bit timer register (tms) ... 230 slave address register (sva) ... 319, 370 successive approximation register (sar) ... 295 [t] timer clock select register 0 (tcl0) ... 190, 285 timer clock select register 1 (tcl1) ... 231 timer clock select register 2 (tcl2) ... 271, 278, 290 timer clock select register 3 (tcl3) ... 321, 373, 418 timer clock select register 5 (tcl5) ... 254 timer clock select register 6 (tcl6) ... 255 transmit shift register (txs) ... 460 [w] watchdog timer mode register (wdtm) ... 280 watch timer mode control register (tmc2) ... 273 619 appendix d register index d.2 register symbol index [a] adcr: a/d conversion result register ... 295 adis: a/d converter input select register ... 298 adm: a/d converter mode register ... 296 adtc: automatic data transmit/receive control register ... 420 adti: automatic data transmit/receive interval specify register ... 421 adtp: automatic data transmit/receive address pointer ... 417 asim: asynchronous serial interface mode register ... 462 asis: asynchronous serial interface status register ... 464 [b] brgc: baud rate generator control register ... 465 [c] corad0: correction address register 0 ... 560 corad1: correction address register 1 ... 560 corcn: correction control register ... 561 cr00: capture/compare register 00 ... 188 cr01: capture/compare register 01 ... 188 cr10: compare register 10 ... 230 cr20: compare register 20 ... 230 cr50: compare register 50 ... 253 cr60: compare register 60 ... 253 crc0: capture/compare control register 0 ... 193 csim0: serial operating mode register 0 ... 323, 374 csim1: serial operating mode register 1 ... 419 csim2: serial operating mode register 2 ... 461 [d] dacs0: d/a conversion value set register 0 ... 311 dacs1: d/a conversion value set register 1 ... 311 dam: d/a converter mode register ... 312 [e] ebts: external bus type select register ... 533 [i] if0h: interrupt request flag register 0h ... 505 if0l: interrupt request flag register 0l ... 505 if1l: interrupt request flag register 1l ... 505, 524 620 appendix d register index ims: internal memory size switching register ... 532, 570 intm0: external interrupt mode register 0 ... 196, 508 intm1: external interrupt mode register 1 ... 299, 508 ixs: internal extension ram size switching register ... 571 [k] krm: key return mode register ... 162, 525 [m] mk0h: interrupt mask flag register 0h ... 506 mk0l: interrupt mask flag register 0l ... 506 mk1l: interrupt mask flag register 1l ... 506, 524 mm: memory expansion mode register ... 161, 531 [o] osms: oscillation mode selection register ... 170 osts: oscillation stabilization time select register ... 546 [p] p0: port 0 ... 136 p1: port 1 ... 138 p2: port 2 ... 139, 141 p3: port 3 ... 143 p4: port 4 ... 144 p5: port 5 ... 145 p6: port 6 ... 146 p7: port 7 ... 148 p8: port 8 ... 150 p9: port 9 ... 151 p10: port 10 ... 153 p12: port 12 ... 155 p13: port 13 ... 156 pcc: processor clock control register ... 167 pm0: port mode register 0 ... 157 pm1: port mode register 1 ... 157 pm2: port mode register 2 ... 157 pm3: port mode register 3 ... 157, 195, 235, 287, 292 pm5: port mode register 5 ... 157 pm6: port mode register 6 ... 157 pm7: port mode register 7 ... 157 pm8: port mode register 8 ... 157 pm9: port mode register 9 ... 157 621 appendix d register index pm10: port mode register 10 ... 157, 258 pm12: port mode register 12 ... 157, 497 pm13: port mode register 13 ... 157 pr0h: priority specify flag register 0h ... 507 pr0l: priority specify flag register 0l ... 507 pr1l: priority specify flag register 1l ... 507 puoh: pull-up resistor option register h ... 160 puol: pull-up resistor option register l ... 160 [r] rtbh: real-time output buffer register h ... 496 rtbl: real-time output buffer register l ... 496 rtpc: real-time output port control register ... 498 rtpm: real-time output port mode register ... 497 rxb: receive buffer register ... 460 rxs: receive shift register ... 460 [s] sar: successive approximation register ... 295 sbic: serial bus interface control register ... 325, 376 scs: sampling clock select register ... 197, 510 sint: interrupt timing specify register ... 327, 378 sio0: serial i/o shift register 0 ... 319, 370 sio1: serial i/o shift register 1 ... 417 sva: slave address register ... 319, 370 [t] tcl0: timer clock select register 0 ... 190, 285 tcl1: timer clock select register 1 ... 231 tcl2: timer clock select register 2 ... 271, 278, 290 tcl3: timer clock select register 3 ... 321, 373, 418 tcl5: timer clock select register 5 ... 254 tcl6: timer clock select register 6 ... 255 tm0: 16-bit timer register ... 189 tm1: 8-bit timer register 1 ... 230 tm2: 8-bit timer register 2 ... 230 tm5: 8-bit timer register 5 ... 253 tm6: 8-bit timer register 6 ... 253 tmc0: 16-bit timer mode control register ... 192 tmc1: 8-bit timer mode control register 1 ... 233 tmc2: watch timer mode control register ... 273 tmc5: 8-bit timer mode control register 5 ... 256 622 appendix d register index tmc6: 8-bit timer mode control register 6 ... 257 tms: 16-bit timer register ... 230 toc0: 16-bit timer output control register ... 194 toc1: 8-bit timer output control register ... 234 txs: transmit shift register ... 460 [w] wdtm: watchdog timer mode register ... 280 623 appendix e revision history the revision history is shown below. the chapters appearing in the chapter column indicate those of the corresponding edition. version major revisions from previous version chapter second m pd78076, 78078, 78p078: under development ? developed m pd78074, 78075, 78074y, 78075y, 78076y, 78078y, 78p078y have been added as new members of this subseries. supply voltage (v dd ) range has been changed: 2.0 to 6.0 v ? 1.8 to 5.5 v 1.9 mask options has been added. 1.10 differences with m pd78054 subseries has been added. cautions on using the alternate function of port 13 pins have been added. change has been made to recommended connection of unused pins. change has been made to recommended connection of unused pins for p130/ano0 and p131/ano1 pins. caution when mask option pull-up resistor is not used has been added. caution has been added to figure 7-4. oscillation mode selection register format . caution when an external clock is used as the main system clock source has been corrected. the count clocks of 8-bit timer/event counters 5 and 6 have been corrected. a/d converter mode register format has been modified. 15.5 (7) av dd pin has been modified, and figure 15-12. handling of av dd pin has been added. serial operating mode register 0 format has been modified. figure 17-34. sck0/p27 pin configuration has been corrected. the baud rate transmit/receive clock range that can be generated using the main system clock has been modified: 75 bps to 38400 ? 75 bps to 76800 bps chapter 23 external device expansion function has been re-arranged so that the multiplexed bus mode and the separate bus mode are explained separately. 23.4 example of connection with memory has been modified. throughout this document chapter 1 outline ( m pd78078 subseries) chapter 3 pin function ( m pd78078 subseries) chapter 6 port functions chapter 16 d/a converter chapter 3 pin function ( m pd78078 subseries) chapter 6 port functions chapter 7 clock generater chapter 24 standby function chapter 10 8-bit timer/ event counters 5 and 6 chapter 15 a/d converter chapter 17 serial interface channel 0 ( m pd78078 subseries) chapter 20 serial interface channel 2 chapter 23 external device expansion function 624 appendix e revision history version major revisions from previous version chapter second table 24-1. halt mode operating status has been modified. table 24-3. stop mode operating status has been modified. chapter 26 rom correction has been added. the development statuses for the following products have been changed from under development to developed. pa-78p078gc, pa-78p078gf, pa-78p078kl-t, ie-78078-r-em, df78078 the following products have been defined as products for maintenance purposes only. ie-75000-r, ie-78230-r, ie-78240-r, ie-78320-r, ie-78330-r a system simulator (sm78k0) has been added. a.4 operating systems for ibm pc has been added. hp9000 series 700 has been added as a host machine on which the software can run. an operating system (mx78k0) has been added. third the m pd78074 and 78075 have been deleted. the following package has been added to the m pd78078 subseries. 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) (planned) description has been added to the caution of figure 8-6. 16- bit timer output control register format . figure 12-3. watchdog timer mode register format has been changed, and caution has been added. caution has been added to serial i/o shift register 0 (sio0) of m pd78078y subseries. figure 18-22. example of communication from master to slave (with 9-clock wait selected for both master and slave) has been corrected. figure 18-23. example of communication from slave to master (with 9-clock wait selected for both master and slave) has been corrected. 18.4.6 restrictions in i 2 c bus mode has been added. caution has been added to figure 19-5. automatic data transmit/receive interval specify register format . caution has been added to 19.4.3 (3) (d) busy control option . description related to the port mode register 12 (pm12) has been added. the following products have been added. ie-78000-r-a, ie-70000-98-if-b, ie-70000-98n-if-b, ie-70000-pc-if-b, ie-78000-r-sv3, id78k0 the versions of the supported os have been changed. chapter 24 standby function appendix a development tools appendix b embedded software throughout this document chapter 8 16-bit timer/ event counter chapter 12 watchdog timer chapter 18 serial interface channel 0 ( m pd78078y subseries) chapter 19 serial interface channel 1 chapter 21 real-time output port appendix a development tools, appendix b embedded software 625 appendix e revision history edition major revisions from previous edition chapter fourth the following products have been changed from under development to already developed. m pd78078y subseries: m pd78076y, 78078y, 78p078y the following package has been added to the m pd78078y subseries. 100-pin plastic lqfp (fine pitch) (14 x 14 mm, resin thickness 1.4 mm) block diagrams of ports have been changed. figure 6-5. block diagram of p20, p21, p23 to p26, figure 6-6. block diagram of p22 and p27, figure 6-7. block diagram of p20, p21, p23 to p26, figure 6-8. block diagram of p22 and p27, figure 6-9. block diagram of p30 to p37, figure 6-16. block diagram of p71 and p72, figure 6-20. block diagram of p100 and p101 table 7-2. relationship between cpu clock and minimum instruction execution time has been added. precautions for changing the operation mode of the serial interface channel 0 have been added. release conditions of busy mode of the serial interface channel 0 (in sbi mode) have been changed. cautions for the case that bus release signal (rel) and command signal (cmd) are misrecognized due to the bus line changing timing has been added. conditions and timings for the generation of interrupt request (intsr, intser) when a reception error is generated have been corrected. precautions for using uart mode have been added. precautions for replacing prom versions with mask rom versions have been added. appendix a differences between m pd78078, 78075b subseries and m pd78070a has been added. entirely revised: supports in-circuit emulator ie-78k0-ns entirely revised: fuzzy inference developing support system has been deleted. throughout chapter 6 port function chapter 7 clock generation circuit chapter 17 serial interface channel 0 ( m pd78078 subseries), chapter 18 serial interface channel 0 ( m pd78078y subseries) chapter 17 serial interface channel 0 ( m pd78078 subseries) chapter 20 serial interface channel 2 chapter 27 m pd78p078, 78p078y appendix a differences between m pd78078, 78075b subseries and m pd78070a appendix b development tools appendix c embedded software 626 [memo] although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6465-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec corporation semiconductor solution engineering division technical information support dept. fax: 044-548-7900 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 97.8 name company from: tel. fax facsimile message |
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